2006-08-13 23:44:09 +02:00
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/*
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* TI OMAP I2C master mode driver
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*
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* Copyright (C) 2003 MontaVista Software, Inc.
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* Copyright (C) 2005 Nokia Corporation
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2008-11-21 22:39:47 +01:00
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* Copyright (C) 2004 - 2007 Texas Instruments.
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2006-08-13 23:44:09 +02:00
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*
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2008-11-21 22:39:47 +01:00
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* Originally written by MontaVista Software, Inc.
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* Additional contributions by:
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* Tony Lindgren <tony@atomide.com>
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* Imre Deak <imre.deak@nokia.com>
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* Juha Yrjölä <juha.yrjola@solidboot.com>
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* Syed Khasim <x0khasim@ti.com>
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* Nishant Menon <nm@ti.com>
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2006-08-13 23:44:09 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/completion.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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2008-11-21 22:39:47 +01:00
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#include <linux/io.h>
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2011-12-22 15:56:36 +01:00
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#include <linux/of.h>
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#include <linux/of_i2c.h>
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#include <linux/of_device.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 09:04:11 +01:00
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#include <linux/slab.h>
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2010-05-11 20:35:08 +02:00
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#include <linux/i2c-omap.h>
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2010-09-28 17:32:58 +02:00
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#include <linux/pm_runtime.h>
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2006-08-13 23:44:09 +02:00
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2008-11-21 22:39:55 +01:00
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/* I2C controller revisions */
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2011-05-30 16:43:07 +02:00
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#define OMAP_I2C_OMAP1_REV_2 0x20
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2008-11-21 22:39:55 +01:00
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/* I2C controller revisions present on specific hardware */
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#define OMAP_I2C_REV_ON_2430 0x36
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2012-06-28 17:11:31 +02:00
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#define OMAP_I2C_REV_ON_3430_3530 0x3C
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#define OMAP_I2C_REV_ON_3630_4430 0x40
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2008-11-21 22:39:55 +01:00
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2006-08-13 23:44:09 +02:00
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/* timeout waiting for the controller to respond */
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#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
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2008-11-21 22:39:55 +01:00
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/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
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2010-05-11 20:35:04 +02:00
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enum {
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OMAP_I2C_REV_REG = 0,
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OMAP_I2C_IE_REG,
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OMAP_I2C_STAT_REG,
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OMAP_I2C_IV_REG,
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OMAP_I2C_WE_REG,
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OMAP_I2C_SYSS_REG,
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OMAP_I2C_BUF_REG,
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OMAP_I2C_CNT_REG,
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OMAP_I2C_DATA_REG,
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OMAP_I2C_SYSC_REG,
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OMAP_I2C_CON_REG,
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OMAP_I2C_OA_REG,
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OMAP_I2C_SA_REG,
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OMAP_I2C_PSC_REG,
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OMAP_I2C_SCLL_REG,
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OMAP_I2C_SCLH_REG,
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OMAP_I2C_SYSTEST_REG,
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OMAP_I2C_BUFSTAT_REG,
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2011-05-30 16:43:04 +02:00
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/* only on OMAP4430 */
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OMAP_I2C_IP_V2_REVNB_LO,
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OMAP_I2C_IP_V2_REVNB_HI,
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OMAP_I2C_IP_V2_IRQSTATUS_RAW,
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OMAP_I2C_IP_V2_IRQENABLE_SET,
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OMAP_I2C_IP_V2_IRQENABLE_CLR,
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2010-05-11 20:35:04 +02:00
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};
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2006-08-13 23:44:09 +02:00
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/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
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2008-11-21 22:39:46 +01:00
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#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
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#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
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2006-08-13 23:44:09 +02:00
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#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
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#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
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#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
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#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
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#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
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/* I2C Status Register (OMAP_I2C_STAT): */
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2008-11-21 22:39:46 +01:00
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#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
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#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
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2006-08-13 23:44:09 +02:00
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#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
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#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
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#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
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#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
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#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
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#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
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#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
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#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
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#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
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#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
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2008-11-21 22:39:55 +01:00
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/* I2C WE wakeup enable register */
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#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
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#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
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#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
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#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
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#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
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#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
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#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
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#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
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#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
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#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
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#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
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OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
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OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
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OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
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OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
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2006-08-13 23:44:09 +02:00
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/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
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#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
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2008-11-21 22:39:46 +01:00
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#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
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2006-08-13 23:44:09 +02:00
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#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
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2008-11-21 22:39:46 +01:00
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#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
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2006-08-13 23:44:09 +02:00
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/* I2C Configuration Register (OMAP_I2C_CON): */
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#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
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#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
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2008-11-21 22:39:46 +01:00
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#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
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2006-08-13 23:44:09 +02:00
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#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
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#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
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#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
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#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
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#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
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#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
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#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
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2008-11-21 22:39:45 +01:00
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/* I2C SCL time value when Master */
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#define OMAP_I2C_SCLL_HSSCLL 8
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#define OMAP_I2C_SCLH_HSSCLH 8
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2006-08-13 23:44:09 +02:00
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/* I2C System Test Register (OMAP_I2C_SYSTEST): */
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#ifdef DEBUG
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#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
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#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
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#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
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#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
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#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
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#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
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#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
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#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
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#endif
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2008-11-21 22:39:55 +01:00
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/* OCP_SYSSTATUS bit definitions */
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#define SYSS_RESETDONE_MASK (1 << 0)
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/* OCP_SYSCONFIG bit definitions */
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#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
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#define SYSC_SIDLEMODE_MASK (0x3 << 3)
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#define SYSC_ENAWAKEUP_MASK (1 << 2)
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#define SYSC_SOFTRESET_MASK (1 << 1)
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#define SYSC_AUTOIDLE_MASK (1 << 0)
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#define SYSC_IDLEMODE_SMART 0x2
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#define SYSC_CLOCKACTIVITY_FCLK 0x2
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2006-08-13 23:44:09 +02:00
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2010-05-11 20:35:20 +02:00
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/* Errata definitions */
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#define I2C_OMAP_ERRATA_I207 (1 << 0)
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2012-05-29 12:56:22 +02:00
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#define I2C_OMAP_ERRATA_I462 (1 << 1)
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2006-08-13 23:44:09 +02:00
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struct omap_i2c_dev {
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struct device *dev;
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void __iomem *base; /* virtual */
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int irq;
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2009-12-13 02:54:02 +01:00
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int reg_shift; /* bit shift for I2C register addresses */
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2006-08-13 23:44:09 +02:00
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struct completion cmd_complete;
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struct resource *ioarea;
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2010-05-11 20:35:08 +02:00
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u32 latency; /* maximum mpu wkup latency */
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void (*set_mpu_wkup_lat)(struct device *dev,
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long latency);
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2011-12-22 15:56:36 +01:00
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u32 speed; /* Speed of bus in kHz */
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u32 dtrev; /* extra revision from DT */
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u32 flags;
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2006-08-13 23:44:09 +02:00
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u16 cmd_err;
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u8 *buf;
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2010-05-11 20:35:04 +02:00
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u8 *regs;
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2006-08-13 23:44:09 +02:00
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size_t buf_len;
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struct i2c_adapter adapter;
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2008-11-21 22:39:46 +01:00
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u8 fifo_size; /* use as flag and value
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* fifo_size==0 implies no fifo
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* if set, should be trsh+1
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*/
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2008-11-21 22:39:55 +01:00
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u8 rev;
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2008-11-21 22:39:46 +01:00
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unsigned b_hw:1; /* bad h/w fixes */
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2008-03-23 20:28:20 +01:00
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u16 iestate; /* Saved interrupt register */
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2009-11-23 17:59:18 +01:00
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u16 pscstate;
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u16 scllstate;
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u16 sclhstate;
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u16 bufstate;
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u16 syscstate;
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u16 westate;
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2010-05-11 20:35:20 +02:00
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u16 errata;
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2006-08-13 23:44:09 +02:00
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};
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2011-05-30 16:43:06 +02:00
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static const u8 reg_map_ip_v1[] = {
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2010-05-11 20:35:04 +02:00
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[OMAP_I2C_REV_REG] = 0x00,
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[OMAP_I2C_IE_REG] = 0x01,
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[OMAP_I2C_STAT_REG] = 0x02,
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[OMAP_I2C_IV_REG] = 0x03,
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[OMAP_I2C_WE_REG] = 0x03,
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[OMAP_I2C_SYSS_REG] = 0x04,
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[OMAP_I2C_BUF_REG] = 0x05,
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[OMAP_I2C_CNT_REG] = 0x06,
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[OMAP_I2C_DATA_REG] = 0x07,
|
|
|
|
[OMAP_I2C_SYSC_REG] = 0x08,
|
|
|
|
[OMAP_I2C_CON_REG] = 0x09,
|
|
|
|
[OMAP_I2C_OA_REG] = 0x0a,
|
|
|
|
[OMAP_I2C_SA_REG] = 0x0b,
|
|
|
|
[OMAP_I2C_PSC_REG] = 0x0c,
|
|
|
|
[OMAP_I2C_SCLL_REG] = 0x0d,
|
|
|
|
[OMAP_I2C_SCLH_REG] = 0x0e,
|
|
|
|
[OMAP_I2C_SYSTEST_REG] = 0x0f,
|
|
|
|
[OMAP_I2C_BUFSTAT_REG] = 0x10,
|
|
|
|
};
|
|
|
|
|
2011-05-30 16:43:06 +02:00
|
|
|
static const u8 reg_map_ip_v2[] = {
|
2010-05-11 20:35:04 +02:00
|
|
|
[OMAP_I2C_REV_REG] = 0x04,
|
|
|
|
[OMAP_I2C_IE_REG] = 0x2c,
|
|
|
|
[OMAP_I2C_STAT_REG] = 0x28,
|
|
|
|
[OMAP_I2C_IV_REG] = 0x34,
|
|
|
|
[OMAP_I2C_WE_REG] = 0x34,
|
|
|
|
[OMAP_I2C_SYSS_REG] = 0x90,
|
|
|
|
[OMAP_I2C_BUF_REG] = 0x94,
|
|
|
|
[OMAP_I2C_CNT_REG] = 0x98,
|
|
|
|
[OMAP_I2C_DATA_REG] = 0x9c,
|
2011-12-08 15:43:53 +01:00
|
|
|
[OMAP_I2C_SYSC_REG] = 0x10,
|
2010-05-11 20:35:04 +02:00
|
|
|
[OMAP_I2C_CON_REG] = 0xa4,
|
|
|
|
[OMAP_I2C_OA_REG] = 0xa8,
|
|
|
|
[OMAP_I2C_SA_REG] = 0xac,
|
|
|
|
[OMAP_I2C_PSC_REG] = 0xb0,
|
|
|
|
[OMAP_I2C_SCLL_REG] = 0xb4,
|
|
|
|
[OMAP_I2C_SCLH_REG] = 0xb8,
|
|
|
|
[OMAP_I2C_SYSTEST_REG] = 0xbC,
|
|
|
|
[OMAP_I2C_BUFSTAT_REG] = 0xc0,
|
2011-05-30 16:43:04 +02:00
|
|
|
[OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
|
|
|
|
[OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
|
|
|
|
[OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
|
|
|
|
[OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
|
|
|
|
[OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
|
2010-05-11 20:35:04 +02:00
|
|
|
};
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
|
|
|
|
int reg, u16 val)
|
|
|
|
{
|
2010-05-11 20:35:04 +02:00
|
|
|
__raw_writew(val, i2c_dev->base +
|
|
|
|
(i2c_dev->regs[reg] << i2c_dev->reg_shift));
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
|
|
|
|
{
|
2010-05-11 20:35:04 +02:00
|
|
|
return __raw_readw(i2c_dev->base +
|
|
|
|
(i2c_dev->regs[reg] << i2c_dev->reg_shift));
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_i2c_init(struct omap_i2c_dev *dev)
|
|
|
|
{
|
2009-11-23 17:59:18 +01:00
|
|
|
u16 psc = 0, scll = 0, sclh = 0, buf = 0;
|
2008-11-21 22:39:45 +01:00
|
|
|
u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
|
2006-08-13 23:44:09 +02:00
|
|
|
unsigned long fclk_rate = 12000000;
|
|
|
|
unsigned long timeout;
|
2008-11-21 22:39:45 +01:00
|
|
|
unsigned long internal_clk = 0;
|
2010-09-28 17:32:58 +02:00
|
|
|
struct clk *fclk;
|
2006-08-13 23:44:09 +02:00
|
|
|
|
2011-05-30 16:43:07 +02:00
|
|
|
if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
|
2009-12-11 06:39:08 +01:00
|
|
|
/* Disable I2C controller before soft reset */
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
|
|
|
|
omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
|
|
|
|
~(OMAP_I2C_CON_EN));
|
|
|
|
|
2008-11-21 22:39:55 +01:00
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
|
2006-08-13 23:44:09 +02:00
|
|
|
/* For some reason we need to set the EN bit before the
|
|
|
|
* reset done bit gets set. */
|
|
|
|
timeout = jiffies + OMAP_I2C_TIMEOUT;
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
|
|
|
|
while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
|
2008-11-21 22:39:55 +01:00
|
|
|
SYSS_RESETDONE_MASK)) {
|
2006-08-13 23:44:09 +02:00
|
|
|
if (time_after(jiffies, timeout)) {
|
2007-12-12 13:45:24 +01:00
|
|
|
dev_warn(dev->dev, "timeout waiting "
|
2006-08-13 23:44:09 +02:00
|
|
|
"for controller reset\n");
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
msleep(1);
|
|
|
|
}
|
2008-11-21 22:39:55 +01:00
|
|
|
|
|
|
|
/* SYSC register is cleared by the reset; rewrite it */
|
|
|
|
if (dev->rev == OMAP_I2C_REV_ON_2430) {
|
|
|
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
|
|
|
|
SYSC_AUTOIDLE_MASK);
|
|
|
|
|
2012-06-28 17:11:31 +02:00
|
|
|
} else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
|
2009-11-23 17:59:18 +01:00
|
|
|
dev->syscstate = SYSC_AUTOIDLE_MASK;
|
|
|
|
dev->syscstate |= SYSC_ENAWAKEUP_MASK;
|
|
|
|
dev->syscstate |= (SYSC_IDLEMODE_SMART <<
|
2008-11-21 22:39:55 +01:00
|
|
|
__ffs(SYSC_SIDLEMODE_MASK));
|
2009-11-23 17:59:18 +01:00
|
|
|
dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
|
2008-11-21 22:39:55 +01:00
|
|
|
__ffs(SYSC_CLOCKACTIVITY_MASK));
|
|
|
|
|
2009-11-23 17:59:18 +01:00
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
|
|
|
|
dev->syscstate);
|
2008-11-21 22:39:55 +01:00
|
|
|
/*
|
|
|
|
* Enabling all wakup sources to stop I2C freezing on
|
|
|
|
* WFI instruction.
|
|
|
|
* REVISIT: Some wkup sources might not be needed.
|
|
|
|
*/
|
2009-11-23 17:59:18 +01:00
|
|
|
dev->westate = OMAP_I2C_WE_ALL;
|
2011-08-03 10:28:08 +02:00
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
|
|
|
|
dev->westate);
|
2008-11-21 22:39:55 +01:00
|
|
|
}
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
|
|
|
|
|
2011-12-22 15:56:36 +01:00
|
|
|
if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
|
2009-01-22 20:31:46 +01:00
|
|
|
/*
|
|
|
|
* The I2C functional clock is the armxor_ck, so there's
|
|
|
|
* no need to get "armxor_ck" separately. Now, if OMAP2420
|
|
|
|
* always returns 12MHz for the functional clock, we can
|
|
|
|
* do this bit unconditionally.
|
|
|
|
*/
|
2010-09-28 17:32:58 +02:00
|
|
|
fclk = clk_get(dev->dev, "fck");
|
|
|
|
fclk_rate = clk_get_rate(fclk);
|
|
|
|
clk_put(fclk);
|
2009-01-22 20:31:46 +01:00
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
/* TRM for 5912 says the I2C clock must be prescaled to be
|
|
|
|
* between 7 - 12 MHz. The XOR input clock is typically
|
|
|
|
* 12, 13 or 19.2 MHz. So we should have code that produces:
|
|
|
|
*
|
|
|
|
* XOR MHz Divider Prescaler
|
|
|
|
* 12 1 0
|
|
|
|
* 13 2 1
|
|
|
|
* 19.2 2 1
|
|
|
|
*/
|
2006-12-10 21:21:34 +01:00
|
|
|
if (fclk_rate > 12000000)
|
|
|
|
psc = fclk_rate / 12000000;
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
|
|
|
|
2011-12-22 15:56:36 +01:00
|
|
|
if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
|
2008-11-21 22:39:45 +01:00
|
|
|
|
2009-05-27 16:54:46 +02:00
|
|
|
/*
|
|
|
|
* HSI2C controller internal clk rate should be 19.2 Mhz for
|
|
|
|
* HS and for all modes on 2430. On 34xx we can use lower rate
|
|
|
|
* to get longer filter period for better noise suppression.
|
|
|
|
* The filter is iclk (fclk for HS) period.
|
|
|
|
*/
|
2011-05-30 16:43:09 +02:00
|
|
|
if (dev->speed > 400 ||
|
2011-12-22 15:56:36 +01:00
|
|
|
dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
|
2009-05-27 16:54:46 +02:00
|
|
|
internal_clk = 19200;
|
|
|
|
else if (dev->speed > 100)
|
|
|
|
internal_clk = 9600;
|
|
|
|
else
|
|
|
|
internal_clk = 4000;
|
2010-09-28 17:32:58 +02:00
|
|
|
fclk = clk_get(dev->dev, "fck");
|
|
|
|
fclk_rate = clk_get_rate(fclk) / 1000;
|
|
|
|
clk_put(fclk);
|
2008-11-21 22:39:45 +01:00
|
|
|
|
|
|
|
/* Compute prescaler divisor */
|
|
|
|
psc = fclk_rate / internal_clk;
|
|
|
|
psc = psc - 1;
|
|
|
|
|
|
|
|
/* If configured for High Speed */
|
|
|
|
if (dev->speed > 400) {
|
2009-05-27 16:54:45 +02:00
|
|
|
unsigned long scl;
|
|
|
|
|
2008-11-21 22:39:45 +01:00
|
|
|
/* For first phase of HS mode */
|
2009-05-27 16:54:45 +02:00
|
|
|
scl = internal_clk / 400;
|
|
|
|
fsscll = scl - (scl / 3) - 7;
|
|
|
|
fssclh = (scl / 3) - 5;
|
2008-11-21 22:39:45 +01:00
|
|
|
|
|
|
|
/* For second phase of HS mode */
|
2009-05-27 16:54:45 +02:00
|
|
|
scl = fclk_rate / dev->speed;
|
|
|
|
hsscll = scl - (scl / 3) - 7;
|
|
|
|
hssclh = (scl / 3) - 5;
|
|
|
|
} else if (dev->speed > 100) {
|
|
|
|
unsigned long scl;
|
|
|
|
|
|
|
|
/* Fast mode */
|
|
|
|
scl = internal_clk / dev->speed;
|
|
|
|
fsscll = scl - (scl / 3) - 7;
|
|
|
|
fssclh = (scl / 3) - 5;
|
2008-11-21 22:39:45 +01:00
|
|
|
} else {
|
2009-05-27 16:54:45 +02:00
|
|
|
/* Standard mode */
|
|
|
|
fsscll = internal_clk / (dev->speed * 2) - 7;
|
|
|
|
fssclh = internal_clk / (dev->speed * 2) - 5;
|
2008-11-21 22:39:45 +01:00
|
|
|
}
|
|
|
|
scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
|
|
|
|
sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
|
|
|
|
} else {
|
|
|
|
/* Program desired operating rate */
|
|
|
|
fclk_rate /= (psc + 1) * 1000;
|
|
|
|
if (psc > 2)
|
|
|
|
psc = 2;
|
|
|
|
scll = fclk_rate / (dev->speed * 2) - 7 + psc;
|
|
|
|
sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
|
|
|
|
}
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
|
|
|
|
|
2008-11-21 22:39:45 +01:00
|
|
|
/* SCL low and high time values */
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
|
2006-08-13 23:44:09 +02:00
|
|
|
|
2009-11-23 17:59:18 +01:00
|
|
|
if (dev->fifo_size) {
|
|
|
|
/* Note: setup required fifo size - 1. RTRSH and XTRSH */
|
|
|
|
buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
|
|
|
|
(dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
|
|
|
|
}
|
2008-11-21 22:39:46 +01:00
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
/* Take the I2C module out of reset: */
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
|
|
|
|
|
|
|
|
/* Enable interrupts */
|
2009-11-23 17:59:18 +01:00
|
|
|
dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
|
2008-11-21 22:39:47 +01:00
|
|
|
OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
|
|
|
|
OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
|
2009-11-23 17:59:18 +01:00
|
|
|
(OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
|
2011-12-22 15:56:36 +01:00
|
|
|
if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
|
2009-11-23 17:59:18 +01:00
|
|
|
dev->pscstate = psc;
|
|
|
|
dev->scllstate = scll;
|
|
|
|
dev->sclhstate = sclh;
|
|
|
|
dev->bufstate = buf;
|
|
|
|
}
|
2006-08-13 23:44:09 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Waiting on Bus Busy
|
|
|
|
*/
|
|
|
|
static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
|
|
|
|
{
|
|
|
|
unsigned long timeout;
|
|
|
|
|
|
|
|
timeout = jiffies + OMAP_I2C_TIMEOUT;
|
|
|
|
while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
|
|
|
|
if (time_after(jiffies, timeout)) {
|
|
|
|
dev_warn(dev->dev, "timeout waiting for bus ready\n");
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
msleep(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Low level master read/write transaction.
|
|
|
|
*/
|
|
|
|
static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
|
|
|
|
struct i2c_msg *msg, int stop)
|
|
|
|
{
|
|
|
|
struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
|
2012-05-29 12:56:17 +02:00
|
|
|
unsigned long timeout;
|
2006-08-13 23:44:09 +02:00
|
|
|
u16 w;
|
|
|
|
|
|
|
|
dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
|
|
|
|
msg->addr, msg->len, msg->flags, stop);
|
|
|
|
|
|
|
|
if (msg->len == 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
|
|
|
|
|
|
|
|
/* REVISIT: Could the STB bit of I2C_CON be used with probing? */
|
|
|
|
dev->buf = msg->buf;
|
|
|
|
dev->buf_len = msg->len;
|
|
|
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
|
|
|
|
|
2008-11-21 22:39:46 +01:00
|
|
|
/* Clear the FIFO Buffers */
|
|
|
|
w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
|
|
|
|
w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
|
|
|
|
|
2012-06-28 17:11:29 +02:00
|
|
|
INIT_COMPLETION(dev->cmd_complete);
|
2006-08-13 23:44:09 +02:00
|
|
|
dev->cmd_err = 0;
|
|
|
|
|
|
|
|
w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
|
2008-11-21 22:39:45 +01:00
|
|
|
|
|
|
|
/* High speed configuration */
|
|
|
|
if (dev->speed > 400)
|
2008-11-21 22:39:46 +01:00
|
|
|
w |= OMAP_I2C_CON_OPMODE_HS;
|
2008-11-21 22:39:45 +01:00
|
|
|
|
2012-07-24 14:13:59 +02:00
|
|
|
if (msg->flags & I2C_M_STOP)
|
|
|
|
stop = 1;
|
2006-08-13 23:44:09 +02:00
|
|
|
if (msg->flags & I2C_M_TEN)
|
|
|
|
w |= OMAP_I2C_CON_XA;
|
|
|
|
if (!(msg->flags & I2C_M_RD))
|
|
|
|
w |= OMAP_I2C_CON_TRX;
|
2008-11-21 22:39:47 +01:00
|
|
|
|
2008-11-21 22:39:46 +01:00
|
|
|
if (!dev->b_hw && stop)
|
2006-08-13 23:44:09 +02:00
|
|
|
w |= OMAP_I2C_CON_STP;
|
2008-11-21 22:39:47 +01:00
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
|
|
|
|
|
2008-11-21 22:39:46 +01:00
|
|
|
/*
|
|
|
|
* Don't write stt and stp together on some hardware.
|
|
|
|
*/
|
|
|
|
if (dev->b_hw && stop) {
|
|
|
|
unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
|
|
|
|
u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
|
|
|
|
while (con & OMAP_I2C_CON_STT) {
|
|
|
|
con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
|
|
|
|
|
|
|
|
/* Let the user know if i2c is in a bad state */
|
|
|
|
if (time_after(jiffies, delay)) {
|
|
|
|
dev_err(dev->dev, "controller timed out "
|
|
|
|
"waiting for start condition to finish\n");
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
|
|
|
|
w |= OMAP_I2C_CON_STP;
|
|
|
|
w &= ~OMAP_I2C_CON_STT;
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
|
|
|
|
}
|
|
|
|
|
2008-11-21 22:39:45 +01:00
|
|
|
/*
|
|
|
|
* REVISIT: We should abort the transfer on signals, but the bus goes
|
|
|
|
* into arbitration and we're currently unable to recover from it.
|
|
|
|
*/
|
2012-05-29 12:56:17 +02:00
|
|
|
timeout = wait_for_completion_timeout(&dev->cmd_complete,
|
|
|
|
OMAP_I2C_TIMEOUT);
|
2006-08-13 23:44:09 +02:00
|
|
|
dev->buf_len = 0;
|
2012-05-29 12:56:17 +02:00
|
|
|
if (timeout == 0) {
|
2006-08-13 23:44:09 +02:00
|
|
|
dev_err(dev->dev, "controller timed out\n");
|
|
|
|
omap_i2c_init(dev);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (likely(!dev->cmd_err))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* We have an error */
|
|
|
|
if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
|
|
|
|
OMAP_I2C_STAT_XUDF)) {
|
|
|
|
omap_i2c_init(dev);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
|
|
|
|
if (msg->flags & I2C_M_IGNORE_NAK)
|
|
|
|
return 0;
|
|
|
|
if (stop) {
|
|
|
|
w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
|
|
|
|
w |= OMAP_I2C_CON_STP;
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
|
|
|
|
}
|
|
|
|
return -EREMOTEIO;
|
|
|
|
}
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Prepare controller for a transaction and call omap_i2c_xfer_msg
|
|
|
|
* to do the work during IRQ processing.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
|
|
|
|
{
|
|
|
|
struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
|
|
int i;
|
|
|
|
int r;
|
|
|
|
|
2012-05-29 12:56:19 +02:00
|
|
|
r = pm_runtime_get_sync(dev->dev);
|
|
|
|
if (IS_ERR_VALUE(r))
|
2012-06-27 03:45:32 +02:00
|
|
|
goto out;
|
2006-08-13 23:44:09 +02:00
|
|
|
|
2008-11-21 22:39:47 +01:00
|
|
|
r = omap_i2c_wait_for_bb(dev);
|
|
|
|
if (r < 0)
|
2006-08-13 23:44:09 +02:00
|
|
|
goto out;
|
|
|
|
|
2010-11-18 11:04:20 +01:00
|
|
|
if (dev->set_mpu_wkup_lat != NULL)
|
|
|
|
dev->set_mpu_wkup_lat(dev->dev, dev->latency);
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
for (i = 0; i < num; i++) {
|
|
|
|
r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
|
|
|
|
if (r != 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-11-18 11:04:20 +01:00
|
|
|
if (dev->set_mpu_wkup_lat != NULL)
|
|
|
|
dev->set_mpu_wkup_lat(dev->dev, -1);
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
if (r == 0)
|
|
|
|
r = num;
|
2010-08-26 09:36:44 +02:00
|
|
|
|
|
|
|
omap_i2c_wait_for_bb(dev);
|
2006-08-13 23:44:09 +02:00
|
|
|
out:
|
2011-05-17 16:31:38 +02:00
|
|
|
pm_runtime_put(dev->dev);
|
2006-08-13 23:44:09 +02:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32
|
|
|
|
omap_i2c_func(struct i2c_adapter *adap)
|
|
|
|
{
|
2012-07-24 14:13:59 +02:00
|
|
|
return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
|
|
|
|
I2C_FUNC_PROTOCOL_MANGLING;
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
|
|
|
|
{
|
|
|
|
dev->cmd_err |= err;
|
|
|
|
complete(&dev->cmd_complete);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
|
|
|
|
{
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
|
|
|
|
}
|
|
|
|
|
2010-05-11 20:35:20 +02:00
|
|
|
static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
|
|
|
|
* Not applicable for OMAP4.
|
|
|
|
* Under certain rare conditions, RDR could be set again
|
|
|
|
* when the bus is busy, then ignore the interrupt and
|
|
|
|
* clear the interrupt.
|
|
|
|
*/
|
|
|
|
if (stat & OMAP_I2C_STAT_RDR) {
|
|
|
|
/* Step 1: If RDR is set, clear it */
|
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
|
|
|
|
|
|
|
|
/* Step 2: */
|
|
|
|
if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
|
|
|
|
& OMAP_I2C_STAT_BB)) {
|
|
|
|
|
|
|
|
/* Step 3: */
|
|
|
|
if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
|
|
|
|
& OMAP_I2C_STAT_RDR) {
|
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
|
|
|
|
dev_dbg(dev->dev, "RDR when bus is busy.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-11-21 22:39:47 +01:00
|
|
|
/* rev1 devices are apparently only on some 15xx */
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
static irqreturn_t
|
2011-05-30 16:43:07 +02:00
|
|
|
omap_i2c_omap1_isr(int this_irq, void *dev_id)
|
2006-08-13 23:44:09 +02:00
|
|
|
{
|
|
|
|
struct omap_i2c_dev *dev = dev_id;
|
|
|
|
u16 iv, w;
|
|
|
|
|
2011-05-17 16:31:38 +02:00
|
|
|
if (pm_runtime_suspended(dev->dev))
|
2008-03-23 20:28:20 +01:00
|
|
|
return IRQ_NONE;
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
|
|
|
|
switch (iv) {
|
|
|
|
case 0x00: /* None */
|
|
|
|
break;
|
|
|
|
case 0x01: /* Arbitration lost */
|
|
|
|
dev_err(dev->dev, "Arbitration lost\n");
|
|
|
|
omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
|
|
|
|
break;
|
|
|
|
case 0x02: /* No acknowledgement */
|
|
|
|
omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
|
|
|
|
break;
|
|
|
|
case 0x03: /* Register access ready */
|
|
|
|
omap_i2c_complete_cmd(dev, 0);
|
|
|
|
break;
|
|
|
|
case 0x04: /* Receive data ready */
|
|
|
|
if (dev->buf_len) {
|
|
|
|
w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
|
|
|
|
*dev->buf++ = w;
|
|
|
|
dev->buf_len--;
|
|
|
|
if (dev->buf_len) {
|
|
|
|
*dev->buf++ = w >> 8;
|
|
|
|
dev->buf_len--;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
dev_err(dev->dev, "RRDY IRQ while no data requested\n");
|
|
|
|
break;
|
|
|
|
case 0x05: /* Transmit data ready */
|
|
|
|
if (dev->buf_len) {
|
|
|
|
w = *dev->buf++;
|
|
|
|
dev->buf_len--;
|
|
|
|
if (dev->buf_len) {
|
|
|
|
w |= *dev->buf++ << 8;
|
|
|
|
dev->buf_len--;
|
|
|
|
}
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
|
|
|
|
} else
|
|
|
|
dev_err(dev->dev, "XRDY IRQ while no data to send\n");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2008-11-21 22:39:47 +01:00
|
|
|
#else
|
2011-05-30 16:43:07 +02:00
|
|
|
#define omap_i2c_omap1_isr NULL
|
2008-11-21 22:39:47 +01:00
|
|
|
#endif
|
2006-08-13 23:44:09 +02:00
|
|
|
|
2010-05-11 20:35:14 +02:00
|
|
|
/*
|
2012-05-29 12:56:22 +02:00
|
|
|
* OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
|
2010-05-11 20:35:14 +02:00
|
|
|
* data to DATA_REG. Otherwise some data bytes can be lost while transferring
|
|
|
|
* them from the memory to the I2C interface.
|
|
|
|
*/
|
2012-09-12 12:58:01 +02:00
|
|
|
static int errata_omap3_i462(struct omap_i2c_dev *dev)
|
2010-05-11 20:35:14 +02:00
|
|
|
{
|
2010-05-11 20:35:17 +02:00
|
|
|
unsigned long timeout = 10000;
|
2012-09-12 12:58:01 +02:00
|
|
|
u16 stat;
|
2010-05-11 20:35:17 +02:00
|
|
|
|
2012-09-12 12:58:01 +02:00
|
|
|
do {
|
|
|
|
stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
|
|
|
|
if (stat & OMAP_I2C_STAT_XUDF)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
|
i2c: omap: simplify omap_i2c_ack_stat()
stat & BIT(1) is the same as BIT(1), so let's
simplify things a bit by removing "stat &" from
all omap_i2c_ack_stat() calls.
Code snippet (extremely simplified):
if (stat & NACK) {
...
omap_i2c_ack_stat(dev, stat & NACK);
}
if (stat & RDR) {
...
omap_i2c_ack_stat(dev, stat & RDR);
}
and so on. The tricky place is only WRT errata handling, for example:
if (*stat & (NACK | AL)) {
omap_i2c_ack_stat(dev, *stat & (XRDY | XDR));
...
}
but in this case, the errata says we must clear XRDY and XDR if that
errata triggers, so if they just got enabled or not, it doesn't matter.
Another tricky place is RDR | RRDY (likewise for XDR | XRDY):
if (stat & (RDR | RRDY)) {
...
omap_i2c_ack_stat(dev, stat & (RDR | RRDY));
}
again here there will be no issues because those IRQs never fire
simultaneously and one will only after after we have handled the
previous, that's because the same FIFO is used anyway and we won't shift
data into FIFO until we tell the IP "hey, I'm done with the FIFO, you
can shift more data"
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by : Santosh Shilimkar <santosh.shilimkar@ti.com>
[Added the explaination from the discurssion to the commit logs]
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
2012-09-12 12:57:59 +02:00
|
|
|
omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
|
2010-05-11 20:35:14 +02:00
|
|
|
OMAP_I2C_STAT_XDR));
|
2012-09-12 12:58:01 +02:00
|
|
|
return -EIO;
|
2010-05-11 20:35:14 +02:00
|
|
|
}
|
2010-05-11 20:35:17 +02:00
|
|
|
|
2010-05-11 20:35:14 +02:00
|
|
|
cpu_relax();
|
2012-09-12 12:58:01 +02:00
|
|
|
} while (--timeout);
|
2010-05-11 20:35:14 +02:00
|
|
|
|
2010-05-11 20:35:17 +02:00
|
|
|
if (!timeout) {
|
|
|
|
dev_err(dev->dev, "timeout waiting on XUDF bit\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-05-11 20:35:14 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-09-12 12:58:02 +02:00
|
|
|
static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
|
|
|
|
bool is_rdr)
|
|
|
|
{
|
|
|
|
u16 w;
|
|
|
|
|
|
|
|
while (num_bytes--) {
|
|
|
|
if (!dev->buf_len) {
|
|
|
|
dev_err(dev->dev, "%s without data",
|
|
|
|
is_rdr ? "RDR" : "RRDY");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
|
|
|
|
*dev->buf++ = w;
|
|
|
|
dev->buf_len--;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Data reg in 2430, omap3 and
|
|
|
|
* omap4 is 8 bit wide
|
|
|
|
*/
|
|
|
|
if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
|
|
|
|
if (dev->buf_len) {
|
|
|
|
*dev->buf++ = w >> 8;
|
|
|
|
dev->buf_len--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
|
|
|
|
bool is_xdr)
|
|
|
|
{
|
|
|
|
u16 w;
|
|
|
|
|
|
|
|
while (num_bytes--) {
|
|
|
|
if (!dev->buf_len) {
|
|
|
|
dev_err(dev->dev, "%s without data",
|
|
|
|
is_xdr ? "XDR" : "XRDY");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
w = *dev->buf++;
|
|
|
|
dev->buf_len--;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Data reg in 2430, omap3 and
|
|
|
|
* omap4 is 8 bit wide
|
|
|
|
*/
|
|
|
|
if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
|
|
|
|
if (dev->buf_len) {
|
|
|
|
w |= *dev->buf++ << 8;
|
|
|
|
dev->buf_len--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->errata & I2C_OMAP_ERRATA_I462) {
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = errata_omap3_i462(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
static irqreturn_t
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 15:55:46 +02:00
|
|
|
omap_i2c_isr(int this_irq, void *dev_id)
|
2006-08-13 23:44:09 +02:00
|
|
|
{
|
|
|
|
struct omap_i2c_dev *dev = dev_id;
|
|
|
|
u16 bits;
|
2012-09-12 12:58:02 +02:00
|
|
|
u16 stat;
|
2012-09-12 12:58:03 +02:00
|
|
|
int err = 0, count = 0;
|
2006-08-13 23:44:09 +02:00
|
|
|
|
2011-05-17 16:31:38 +02:00
|
|
|
if (pm_runtime_suspended(dev->dev))
|
2008-03-23 20:28:20 +01:00
|
|
|
return IRQ_NONE;
|
|
|
|
|
2012-09-12 12:58:03 +02:00
|
|
|
do {
|
|
|
|
bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
|
|
|
|
stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
|
|
|
|
stat &= bits;
|
|
|
|
|
|
|
|
if (!stat) {
|
|
|
|
/* my work here is done */
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
|
|
|
|
if (count++ == 100) {
|
|
|
|
dev_warn(dev->dev, "Too much work in one IRQ\n");
|
2012-09-12 12:58:03 +02:00
|
|
|
omap_i2c_complete_cmd(dev, err);
|
|
|
|
return IRQ_HANDLED;
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
|
|
|
|
2009-07-21 17:15:12 +02:00
|
|
|
complete:
|
2012-09-12 12:58:04 +02:00
|
|
|
if (stat & OMAP_I2C_STAT_NACK) {
|
2008-11-21 22:39:46 +01:00
|
|
|
err |= OMAP_I2C_STAT_NACK;
|
2012-09-12 12:58:04 +02:00
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
|
|
|
|
omap_i2c_complete_cmd(dev, err);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2011-12-07 20:50:16 +01:00
|
|
|
|
2008-11-21 22:39:46 +01:00
|
|
|
if (stat & OMAP_I2C_STAT_AL) {
|
|
|
|
dev_err(dev->dev, "Arbitration lost\n");
|
|
|
|
err |= OMAP_I2C_STAT_AL;
|
2012-09-12 12:58:04 +02:00
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
|
|
|
|
omap_i2c_complete_cmd(dev, err);
|
|
|
|
return IRQ_HANDLED;
|
2008-11-21 22:39:46 +01:00
|
|
|
}
|
2012-09-12 12:57:58 +02:00
|
|
|
|
2011-02-23 01:43:55 +01:00
|
|
|
/*
|
2011-02-16 05:54:16 +01:00
|
|
|
* ProDB0017052: Clear ARDY bit twice
|
2011-02-23 01:43:55 +01:00
|
|
|
*/
|
2008-11-21 22:39:46 +01:00
|
|
|
if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
|
2009-07-21 17:14:40 +02:00
|
|
|
OMAP_I2C_STAT_AL)) {
|
i2c: omap: simplify omap_i2c_ack_stat()
stat & BIT(1) is the same as BIT(1), so let's
simplify things a bit by removing "stat &" from
all omap_i2c_ack_stat() calls.
Code snippet (extremely simplified):
if (stat & NACK) {
...
omap_i2c_ack_stat(dev, stat & NACK);
}
if (stat & RDR) {
...
omap_i2c_ack_stat(dev, stat & RDR);
}
and so on. The tricky place is only WRT errata handling, for example:
if (*stat & (NACK | AL)) {
omap_i2c_ack_stat(dev, *stat & (XRDY | XDR));
...
}
but in this case, the errata says we must clear XRDY and XDR if that
errata triggers, so if they just got enabled or not, it doesn't matter.
Another tricky place is RDR | RRDY (likewise for XDR | XRDY):
if (stat & (RDR | RRDY)) {
...
omap_i2c_ack_stat(dev, stat & (RDR | RRDY));
}
again here there will be no issues because those IRQs never fire
simultaneously and one will only after after we have handled the
previous, that's because the same FIFO is used anyway and we won't shift
data into FIFO until we tell the IP "hey, I'm done with the FIFO, you
can shift more data"
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by : Santosh Shilimkar <santosh.shilimkar@ti.com>
[Added the explaination from the discurssion to the commit logs]
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
2012-09-12 12:57:59 +02:00
|
|
|
omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
|
|
|
|
OMAP_I2C_STAT_RDR |
|
|
|
|
OMAP_I2C_STAT_XRDY |
|
|
|
|
OMAP_I2C_STAT_XDR |
|
|
|
|
OMAP_I2C_STAT_ARDY));
|
2008-11-21 22:39:46 +01:00
|
|
|
omap_i2c_complete_cmd(dev, err);
|
2009-07-21 17:14:40 +02:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2012-09-12 12:57:58 +02:00
|
|
|
|
2012-09-12 12:58:00 +02:00
|
|
|
if (stat & OMAP_I2C_STAT_RDR) {
|
2008-11-21 22:39:46 +01:00
|
|
|
u8 num_bytes = 1;
|
2010-05-11 20:35:20 +02:00
|
|
|
|
2012-09-12 12:58:00 +02:00
|
|
|
if (dev->fifo_size)
|
|
|
|
num_bytes = dev->buf_len;
|
|
|
|
|
2012-09-12 12:58:02 +02:00
|
|
|
omap_i2c_receive_data(dev, num_bytes, true);
|
2012-09-12 12:58:00 +02:00
|
|
|
|
2010-05-11 20:35:20 +02:00
|
|
|
if (dev->errata & I2C_OMAP_ERRATA_I207)
|
|
|
|
i2c_omap_errata_i207(dev, stat);
|
|
|
|
|
2012-09-12 12:58:00 +02:00
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (stat & OMAP_I2C_STAT_RRDY) {
|
|
|
|
u8 num_bytes = 1;
|
|
|
|
|
|
|
|
if (dev->fifo_size)
|
|
|
|
num_bytes = dev->fifo_size;
|
|
|
|
|
2012-09-12 12:58:02 +02:00
|
|
|
omap_i2c_receive_data(dev, num_bytes, false);
|
2012-09-12 12:58:00 +02:00
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
|
2006-08-13 23:44:09 +02:00
|
|
|
continue;
|
|
|
|
}
|
2012-09-12 12:57:58 +02:00
|
|
|
|
2012-09-12 12:58:00 +02:00
|
|
|
if (stat & OMAP_I2C_STAT_XDR) {
|
2008-11-21 22:39:46 +01:00
|
|
|
u8 num_bytes = 1;
|
2012-09-12 12:58:02 +02:00
|
|
|
int ret;
|
2012-09-12 12:58:00 +02:00
|
|
|
|
|
|
|
if (dev->fifo_size)
|
|
|
|
num_bytes = dev->buf_len;
|
|
|
|
|
2012-09-12 12:58:02 +02:00
|
|
|
ret = omap_i2c_transmit_data(dev, num_bytes, true);
|
|
|
|
stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
|
|
|
|
if (ret < 0)
|
|
|
|
goto complete;
|
2012-09-12 12:58:00 +02:00
|
|
|
|
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (stat & OMAP_I2C_STAT_XRDY) {
|
|
|
|
u8 num_bytes = 1;
|
2012-09-12 12:58:02 +02:00
|
|
|
int ret;
|
2012-09-12 12:58:00 +02:00
|
|
|
|
|
|
|
if (dev->fifo_size)
|
|
|
|
num_bytes = dev->fifo_size;
|
|
|
|
|
2012-09-12 12:58:02 +02:00
|
|
|
ret = omap_i2c_transmit_data(dev, num_bytes, false);
|
|
|
|
stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
|
|
|
|
if (ret < 0)
|
|
|
|
goto complete;
|
2012-09-12 12:58:00 +02:00
|
|
|
|
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
|
2006-08-13 23:44:09 +02:00
|
|
|
continue;
|
|
|
|
}
|
2012-09-12 12:57:58 +02:00
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
if (stat & OMAP_I2C_STAT_ROVR) {
|
|
|
|
dev_err(dev->dev, "Receive overrun\n");
|
2012-09-12 12:58:04 +02:00
|
|
|
err |= OMAP_I2C_STAT_ROVR;
|
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
|
|
|
|
omap_i2c_complete_cmd(dev, err);
|
|
|
|
return IRQ_HANDLED;
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
2012-09-12 12:57:58 +02:00
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
if (stat & OMAP_I2C_STAT_XUDF) {
|
2008-11-21 22:39:46 +01:00
|
|
|
dev_err(dev->dev, "Transmit underflow\n");
|
2012-09-12 12:58:04 +02:00
|
|
|
err |= OMAP_I2C_STAT_XUDF;
|
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
|
|
|
|
omap_i2c_complete_cmd(dev, err);
|
|
|
|
return IRQ_HANDLED;
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
2012-09-12 12:58:03 +02:00
|
|
|
} while (stat);
|
2006-08-13 23:44:09 +02:00
|
|
|
|
|
|
|
return count ? IRQ_HANDLED : IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
2006-09-03 22:39:46 +02:00
|
|
|
static const struct i2c_algorithm omap_i2c_algo = {
|
2006-08-13 23:44:09 +02:00
|
|
|
.master_xfer = omap_i2c_xfer,
|
|
|
|
.functionality = omap_i2c_func,
|
|
|
|
};
|
|
|
|
|
2011-12-22 15:56:36 +01:00
|
|
|
#ifdef CONFIG_OF
|
|
|
|
static struct omap_i2c_bus_platform_data omap3_pdata = {
|
|
|
|
.rev = OMAP_I2C_IP_VERSION_1,
|
|
|
|
.flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
|
|
|
|
OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
|
|
|
|
OMAP_I2C_FLAG_BUS_SHIFT_2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_i2c_bus_platform_data omap4_pdata = {
|
|
|
|
.rev = OMAP_I2C_IP_VERSION_2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct of_device_id omap_i2c_of_match[] = {
|
|
|
|
{
|
|
|
|
.compatible = "ti,omap4-i2c",
|
|
|
|
.data = &omap4_pdata,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "ti,omap3-i2c",
|
|
|
|
.data = &omap3_pdata,
|
|
|
|
},
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
|
|
|
|
#endif
|
|
|
|
|
2010-02-04 20:56:53 +01:00
|
|
|
static int __devinit
|
2006-08-13 23:44:09 +02:00
|
|
|
omap_i2c_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct omap_i2c_dev *dev;
|
|
|
|
struct i2c_adapter *adap;
|
2012-09-12 12:57:55 +02:00
|
|
|
struct resource *mem, *irq;
|
2010-05-11 20:35:08 +02:00
|
|
|
struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
|
2011-12-22 15:56:36 +01:00
|
|
|
struct device_node *node = pdev->dev.of_node;
|
|
|
|
const struct of_device_id *match;
|
2008-12-16 23:08:08 +01:00
|
|
|
irq_handler_t isr;
|
2006-08-13 23:44:09 +02:00
|
|
|
int r;
|
|
|
|
|
|
|
|
/* NOTE: driver uses the static register mapping */
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!mem) {
|
|
|
|
dev_err(&pdev->dev, "no mem resource?\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
|
|
if (!irq) {
|
|
|
|
dev_err(&pdev->dev, "no irq resource?\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2012-09-12 12:57:55 +02:00
|
|
|
dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
|
|
|
|
if (!dev) {
|
|
|
|
dev_err(&pdev->dev, "Menory allocation failed\n");
|
|
|
|
return -ENOMEM;
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
|
|
|
|
2012-09-12 12:57:55 +02:00
|
|
|
dev->base = devm_request_and_ioremap(&pdev->dev, mem);
|
|
|
|
if (!dev->base) {
|
|
|
|
dev_err(&pdev->dev, "I2C region already claimed\n");
|
|
|
|
return -ENOMEM;
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
|
|
|
|
2012-01-20 16:55:04 +01:00
|
|
|
match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
|
2011-12-22 15:56:36 +01:00
|
|
|
if (match) {
|
|
|
|
u32 freq = 100000; /* default to 100000 Hz */
|
|
|
|
|
|
|
|
pdata = match->data;
|
|
|
|
dev->dtrev = pdata->rev;
|
|
|
|
dev->flags = pdata->flags;
|
|
|
|
|
|
|
|
of_property_read_u32(node, "clock-frequency", &freq);
|
|
|
|
/* convert DT freq value in Hz into kHz for speed */
|
|
|
|
dev->speed = freq / 1000;
|
|
|
|
} else if (pdata != NULL) {
|
|
|
|
dev->speed = pdata->clkrate;
|
|
|
|
dev->flags = pdata->flags;
|
2010-05-11 20:35:08 +02:00
|
|
|
dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
|
2011-12-22 15:56:36 +01:00
|
|
|
dev->dtrev = pdata->rev;
|
2010-05-11 20:35:08 +02:00
|
|
|
}
|
2008-11-21 22:39:45 +01:00
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
dev->dev = &pdev->dev;
|
|
|
|
dev->irq = irq->start;
|
2008-09-04 15:07:22 +02:00
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
platform_set_drvdata(pdev, dev);
|
2012-06-28 17:11:29 +02:00
|
|
|
init_completion(&dev->cmd_complete);
|
2006-08-13 23:44:09 +02:00
|
|
|
|
2011-12-22 15:56:36 +01:00
|
|
|
dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
|
2010-03-23 11:12:56 +01:00
|
|
|
|
2011-12-22 15:56:36 +01:00
|
|
|
if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
|
2011-05-30 16:43:06 +02:00
|
|
|
dev->regs = (u8 *)reg_map_ip_v2;
|
2010-05-11 20:35:04 +02:00
|
|
|
else
|
2011-05-30 16:43:06 +02:00
|
|
|
dev->regs = (u8 *)reg_map_ip_v1;
|
2010-05-11 20:35:04 +02:00
|
|
|
|
2011-05-17 16:31:37 +02:00
|
|
|
pm_runtime_enable(dev->dev);
|
2012-05-29 12:56:19 +02:00
|
|
|
r = pm_runtime_get_sync(dev->dev);
|
|
|
|
if (IS_ERR_VALUE(r))
|
|
|
|
goto err_free_mem;
|
2006-08-13 23:44:09 +02:00
|
|
|
|
2008-11-21 22:39:55 +01:00
|
|
|
dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
|
2006-08-13 23:44:09 +02:00
|
|
|
|
2012-05-29 12:56:20 +02:00
|
|
|
dev->errata = 0;
|
|
|
|
|
|
|
|
if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
|
|
|
|
dev->errata |= I2C_OMAP_ERRATA_I207;
|
|
|
|
|
2012-06-28 17:11:31 +02:00
|
|
|
if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
|
2012-05-29 12:56:22 +02:00
|
|
|
dev->errata |= I2C_OMAP_ERRATA_I462;
|
2010-05-11 20:35:23 +02:00
|
|
|
|
2011-12-22 15:56:36 +01:00
|
|
|
if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
|
2008-11-21 22:39:46 +01:00
|
|
|
u16 s;
|
|
|
|
|
|
|
|
/* Set up the fifo size - Get total size */
|
|
|
|
s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
|
|
|
|
dev->fifo_size = 0x8 << s;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set up notification threshold as half the total available
|
|
|
|
* size. This is to ensure that we can handle the status on int
|
|
|
|
* call back latencies.
|
|
|
|
*/
|
2011-12-06 19:25:58 +01:00
|
|
|
|
|
|
|
dev->fifo_size = (dev->fifo_size / 2);
|
|
|
|
|
2012-06-28 17:11:31 +02:00
|
|
|
if (dev->rev >= OMAP_I2C_REV_ON_3630_4430)
|
2010-05-11 20:35:04 +02:00
|
|
|
dev->b_hw = 0; /* Disable hardware fixes */
|
2011-12-06 19:25:58 +01:00
|
|
|
else
|
2010-05-11 20:35:04 +02:00
|
|
|
dev->b_hw = 1; /* Enable hardware fixes */
|
2011-12-06 19:25:58 +01:00
|
|
|
|
2010-05-11 20:35:08 +02:00
|
|
|
/* calculate wakeup latency constraint for MPU */
|
|
|
|
if (dev->set_mpu_wkup_lat != NULL)
|
|
|
|
dev->latency = (1000000 * dev->fifo_size) /
|
2011-12-22 15:56:36 +01:00
|
|
|
(1000 * dev->speed / 8);
|
2008-11-21 22:39:46 +01:00
|
|
|
}
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
/* reset ASAP, clearing any IRQs */
|
|
|
|
omap_i2c_init(dev);
|
|
|
|
|
2011-05-30 16:43:07 +02:00
|
|
|
isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
|
|
|
|
omap_i2c_isr;
|
2012-09-12 12:57:55 +02:00
|
|
|
r = devm_request_irq(&pdev->dev, dev->irq, isr, IRQF_NO_SUSPEND,
|
|
|
|
pdev->name, dev);
|
2006-08-13 23:44:09 +02:00
|
|
|
|
|
|
|
if (r) {
|
|
|
|
dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
|
|
|
|
goto err_unuse_clocks;
|
|
|
|
}
|
2008-11-21 22:39:55 +01:00
|
|
|
|
2011-05-30 16:43:10 +02:00
|
|
|
dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
|
2011-12-22 15:56:36 +01:00
|
|
|
dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
|
2006-08-13 23:44:09 +02:00
|
|
|
|
|
|
|
adap = &dev->adapter;
|
|
|
|
i2c_set_adapdata(adap, dev);
|
|
|
|
adap->owner = THIS_MODULE;
|
|
|
|
adap->class = I2C_CLASS_HWMON;
|
2009-07-17 15:24:00 +02:00
|
|
|
strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
|
2006-08-13 23:44:09 +02:00
|
|
|
adap->algo = &omap_i2c_algo;
|
|
|
|
adap->dev.parent = &pdev->dev;
|
2011-12-22 15:56:36 +01:00
|
|
|
adap->dev.of_node = pdev->dev.of_node;
|
2006-08-13 23:44:09 +02:00
|
|
|
|
|
|
|
/* i2c device drivers may be active on return from add_adapter() */
|
2007-05-01 23:26:32 +02:00
|
|
|
adap->nr = pdev->id;
|
|
|
|
r = i2c_add_numbered_adapter(adap);
|
2006-08-13 23:44:09 +02:00
|
|
|
if (r) {
|
|
|
|
dev_err(dev->dev, "failure adding adapter\n");
|
2012-09-12 12:57:55 +02:00
|
|
|
goto err_unuse_clocks;
|
2006-08-13 23:44:09 +02:00
|
|
|
}
|
|
|
|
|
2011-12-22 15:56:36 +01:00
|
|
|
of_i2c_register_devices(adap);
|
|
|
|
|
2012-05-29 12:56:16 +02:00
|
|
|
pm_runtime_put(dev->dev);
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_unuse_clocks:
|
2008-01-14 21:53:30 +01:00
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
|
2011-05-17 16:31:38 +02:00
|
|
|
pm_runtime_put(dev->dev);
|
2012-05-29 12:56:14 +02:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
2006-08-13 23:44:09 +02:00
|
|
|
err_free_mem:
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-06-28 17:11:27 +02:00
|
|
|
static int __devexit omap_i2c_remove(struct platform_device *pdev)
|
2006-08-13 23:44:09 +02:00
|
|
|
{
|
|
|
|
struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
|
2012-05-29 12:56:19 +02:00
|
|
|
int ret;
|
2006-08-13 23:44:09 +02:00
|
|
|
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
|
|
|
|
i2c_del_adapter(&dev->adapter);
|
2012-05-29 12:56:19 +02:00
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
|
|
if (IS_ERR_VALUE(ret))
|
|
|
|
return ret;
|
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
|
2012-05-29 12:56:18 +02:00
|
|
|
pm_runtime_put(&pdev->dev);
|
2012-05-29 12:56:14 +02:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
2006-08-13 23:44:09 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-06-28 17:11:28 +02:00
|
|
|
#ifdef CONFIG_PM
|
2011-05-17 16:31:38 +02:00
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
|
|
static int omap_i2c_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
|
2012-05-29 12:56:13 +02:00
|
|
|
u16 iv;
|
|
|
|
|
|
|
|
_dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
|
2012-05-29 12:56:15 +02:00
|
|
|
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
|
2011-05-17 16:31:38 +02:00
|
|
|
|
2012-05-29 12:56:13 +02:00
|
|
|
if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
|
|
|
|
iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
|
|
|
|
} else {
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
|
2011-05-17 16:31:38 +02:00
|
|
|
|
2012-05-29 12:56:13 +02:00
|
|
|
/* Flush posted write */
|
|
|
|
omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
|
|
|
|
}
|
2011-05-17 16:31:38 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_i2c_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
|
|
|
|
|
2012-05-29 12:56:13 +02:00
|
|
|
if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Don't write to this register if the IE state is 0 as it can
|
|
|
|
* cause deadlock.
|
|
|
|
*/
|
|
|
|
if (_dev->iestate)
|
|
|
|
omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
|
2011-05-17 16:31:38 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2012-06-28 17:11:28 +02:00
|
|
|
#endif /* CONFIG_PM_RUNTIME */
|
2011-05-17 16:31:38 +02:00
|
|
|
|
|
|
|
static struct dev_pm_ops omap_i2c_pm_ops = {
|
2012-06-28 17:11:28 +02:00
|
|
|
SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
|
|
|
|
omap_i2c_runtime_resume, NULL)
|
2011-05-17 16:31:38 +02:00
|
|
|
};
|
|
|
|
#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
|
|
|
|
#else
|
|
|
|
#define OMAP_I2C_PM_OPS NULL
|
2012-06-28 17:11:28 +02:00
|
|
|
#endif /* CONFIG_PM */
|
2011-05-17 16:31:38 +02:00
|
|
|
|
2006-08-13 23:44:09 +02:00
|
|
|
static struct platform_driver omap_i2c_driver = {
|
|
|
|
.probe = omap_i2c_probe,
|
2012-06-28 17:11:27 +02:00
|
|
|
.remove = __devexit_p(omap_i2c_remove),
|
2006-08-13 23:44:09 +02:00
|
|
|
.driver = {
|
2010-12-09 15:24:16 +01:00
|
|
|
.name = "omap_i2c",
|
2006-08-13 23:44:09 +02:00
|
|
|
.owner = THIS_MODULE,
|
2011-05-17 16:31:38 +02:00
|
|
|
.pm = OMAP_I2C_PM_OPS,
|
2011-12-22 15:56:36 +01:00
|
|
|
.of_match_table = of_match_ptr(omap_i2c_of_match),
|
2006-08-13 23:44:09 +02:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* I2C may be needed to bring up other drivers */
|
|
|
|
static int __init
|
|
|
|
omap_i2c_init_driver(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&omap_i2c_driver);
|
|
|
|
}
|
|
|
|
subsys_initcall(omap_i2c_init_driver);
|
|
|
|
|
|
|
|
static void __exit omap_i2c_exit_driver(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&omap_i2c_driver);
|
|
|
|
}
|
|
|
|
module_exit(omap_i2c_exit_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
|
|
|
|
MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
|
|
|
|
MODULE_LICENSE("GPL");
|
2010-12-09 15:24:16 +01:00
|
|
|
MODULE_ALIAS("platform:omap_i2c");
|