2008-08-19 10:08:43 +02:00
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/*
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2010-01-27 04:13:13 +01:00
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* OMAP3 powerdomain definitions
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2008-08-19 10:08:43 +02:00
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*
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2011-09-14 19:34:21 +02:00
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* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
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2011-03-08 03:28:15 +01:00
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* Copyright (C) 2007-2011 Nokia Corporation
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2008-08-19 10:08:43 +02:00
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*
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2010-12-22 04:01:20 +01:00
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* Paul Walmsley, Jouni Högander
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2008-08-19 10:08:43 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2010-12-22 04:01:20 +01:00
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#include <linux/kernel.h>
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#include <linux/init.h>
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2012-03-08 02:28:01 +01:00
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#include <linux/bug.h>
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2008-08-19 10:08:43 +02:00
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2012-08-31 19:59:07 +02:00
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#include "soc.h"
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2010-12-22 05:05:16 +01:00
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#include "powerdomain.h"
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2010-12-22 04:01:20 +01:00
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#include "powerdomains2xxx_3xxx_data.h"
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2008-08-19 10:08:43 +02:00
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#include "prcm-common.h"
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2010-12-21 23:30:55 +01:00
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#include "prm2xxx_3xxx.h"
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2008-08-19 10:08:43 +02:00
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#include "prm-regbits-34xx.h"
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2010-12-21 23:30:55 +01:00
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#include "cm2xxx_3xxx.h"
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2008-08-19 10:08:43 +02:00
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#include "cm-regbits-34xx.h"
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/*
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* 34XX-specific powerdomains, dependencies
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*/
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/*
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* Powerdomains
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*/
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static struct powerdomain iva2_pwrdm = {
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.name = "iva2_pwrdm",
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.prcm_offs = OMAP3430_IVA2_MOD,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 4,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET,
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[1] = PWRSTS_OFF_RET,
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[2] = PWRSTS_OFF_RET,
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[3] = PWRSTS_OFF_RET,
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},
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.pwrsts_mem_on = {
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2011-03-08 03:28:15 +01:00
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[0] = PWRSTS_ON,
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[1] = PWRSTS_ON,
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2008-08-19 10:08:43 +02:00
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[2] = PWRSTS_OFF_ON,
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2011-03-08 03:28:15 +01:00
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[3] = PWRSTS_ON,
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2008-08-19 10:08:43 +02:00
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "mpu_iva" },
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2008-08-19 10:08:43 +02:00
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};
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2010-01-27 04:13:13 +01:00
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static struct powerdomain mpu_3xxx_pwrdm = {
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2008-08-19 10:08:43 +02:00
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.name = "mpu_pwrdm",
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.prcm_offs = MPU_MOD,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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2009-12-09 00:33:15 +01:00
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.flags = PWRDM_HAS_MPU_QUIRK,
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2008-08-19 10:08:43 +02:00
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET,
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_ON,
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "mpu_iva" },
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2008-08-19 10:08:43 +02:00
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};
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2012-06-28 02:43:59 +02:00
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static struct powerdomain mpu_am35x_pwrdm = {
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.name = "mpu_pwrdm",
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.prcm_offs = MPU_MOD,
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.pwrsts = PWRSTS_ON,
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.pwrsts_logic_ret = PWRSTS_ON,
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.flags = PWRDM_HAS_MPU_QUIRK,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_ON,
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON,
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "mpu_iva" },
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2012-06-28 02:43:59 +02:00
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};
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2010-07-14 15:38:49 +02:00
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/*
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* The USBTLL Save-and-Restore mechanism is broken on
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2011-03-31 03:57:33 +02:00
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* 3430s up to ES3.0 and 3630ES1.0. Hence this feature
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2010-07-14 15:38:49 +02:00
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* needs to be disabled on these chips.
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* Refer: 3430 errata ID i459 and 3630 errata ID i579
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2010-11-17 18:52:11 +01:00
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*
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* Note: setting the SAR flag could help for errata ID i478
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* which applies to 3430 <= ES3.1, but since the SAR feature
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* is broken, do not use it.
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2010-07-14 15:38:49 +02:00
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*/
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2010-01-27 04:13:13 +01:00
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static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
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2008-08-19 10:08:43 +02:00
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.name = "core_pwrdm",
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.prcm_offs = CORE_MOD,
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2009-02-06 04:45:28 +01:00
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.pwrsts = PWRSTS_OFF_RET_ON,
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2010-02-24 20:05:50 +01:00
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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2009-02-06 04:45:28 +01:00
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
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[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
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[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2009-02-06 04:45:28 +01:00
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};
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2010-01-27 04:13:13 +01:00
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static struct powerdomain core_3xxx_es3_1_pwrdm = {
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2009-02-06 04:45:28 +01:00
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.name = "core_pwrdm",
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.prcm_offs = CORE_MOD,
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2008-08-19 10:08:43 +02:00
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.pwrsts = PWRSTS_OFF_RET_ON,
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2010-02-24 20:05:50 +01:00
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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2010-11-17 18:52:11 +01:00
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/*
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* Setting the SAR flag for errata ID i478 which applies
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* to 3430 <= ES3.1
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*/
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2009-02-06 04:45:28 +01:00
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.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
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2008-08-19 10:08:43 +02:00
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
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[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
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[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2008-08-19 10:08:43 +02:00
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};
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2012-06-28 02:43:59 +02:00
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static struct powerdomain core_am35x_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = CORE_MOD,
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.pwrsts = PWRSTS_ON,
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.pwrsts_logic_ret = PWRSTS_ON,
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_ON, /* MEM1RETSTATE */
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[1] = PWRSTS_ON, /* MEM2RETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* MEM1ONSTATE */
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[1] = PWRSTS_ON, /* MEM2ONSTATE */
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2012-06-28 02:43:59 +02:00
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};
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2008-08-19 10:08:43 +02:00
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static struct powerdomain dss_pwrdm = {
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.name = "dss_pwrdm",
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.prcm_offs = OMAP3430_DSS_MOD,
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.pwrsts = PWRSTS_OFF_RET_ON,
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2011-03-08 03:28:15 +01:00
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.pwrsts_logic_ret = PWRSTS_RET,
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2008-08-19 10:08:43 +02:00
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.banks = 1,
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.pwrsts_mem_ret = {
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2011-03-08 03:28:15 +01:00
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[0] = PWRSTS_RET, /* MEMRETSTATE */
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2008-08-19 10:08:43 +02:00
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},
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.pwrsts_mem_on = {
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2011-03-08 03:28:15 +01:00
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[0] = PWRSTS_ON, /* MEMONSTATE */
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2008-08-19 10:08:43 +02:00
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2008-08-19 10:08:43 +02:00
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};
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2012-06-28 02:43:59 +02:00
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static struct powerdomain dss_am35x_pwrdm = {
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.name = "dss_pwrdm",
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.prcm_offs = OMAP3430_DSS_MOD,
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.pwrsts = PWRSTS_ON,
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.pwrsts_logic_ret = PWRSTS_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_ON, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* MEMONSTATE */
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2012-06-28 02:43:59 +02:00
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};
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2009-01-28 03:44:28 +01:00
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/*
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* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
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* possible SGX powerstate, the SGX device itself does not support
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* retention.
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*/
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2008-08-19 10:08:43 +02:00
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static struct powerdomain sgx_pwrdm = {
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.name = "sgx_pwrdm",
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.prcm_offs = OMAP3430ES2_SGX_MOD,
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/* XXX This is accurate for 3430 SGX, but what about GFX? */
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2009-01-28 03:44:28 +01:00
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.pwrsts = PWRSTS_OFF_ON,
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2011-03-08 03:28:15 +01:00
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.pwrsts_logic_ret = PWRSTS_RET,
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2008-08-19 10:08:43 +02:00
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.banks = 1,
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.pwrsts_mem_ret = {
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2011-03-08 03:28:15 +01:00
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[0] = PWRSTS_RET, /* MEMRETSTATE */
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2008-08-19 10:08:43 +02:00
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},
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.pwrsts_mem_on = {
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2011-03-08 03:28:15 +01:00
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[0] = PWRSTS_ON, /* MEMONSTATE */
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2008-08-19 10:08:43 +02:00
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2008-08-19 10:08:43 +02:00
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};
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2012-06-28 02:43:59 +02:00
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static struct powerdomain sgx_am35x_pwrdm = {
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.name = "sgx_pwrdm",
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.prcm_offs = OMAP3430ES2_SGX_MOD,
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.pwrsts = PWRSTS_ON,
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.pwrsts_logic_ret = PWRSTS_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_ON, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* MEMONSTATE */
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2012-06-28 02:43:59 +02:00
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};
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2008-08-19 10:08:43 +02:00
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static struct powerdomain cam_pwrdm = {
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.name = "cam_pwrdm",
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.prcm_offs = OMAP3430_CAM_MOD,
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.pwrsts = PWRSTS_OFF_RET_ON,
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2011-03-08 03:28:15 +01:00
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.pwrsts_logic_ret = PWRSTS_RET,
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2008-08-19 10:08:43 +02:00
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.banks = 1,
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.pwrsts_mem_ret = {
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2011-03-08 03:28:15 +01:00
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[0] = PWRSTS_RET, /* MEMRETSTATE */
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2008-08-19 10:08:43 +02:00
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},
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.pwrsts_mem_on = {
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2011-03-08 03:28:15 +01:00
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[0] = PWRSTS_ON, /* MEMONSTATE */
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2008-08-19 10:08:43 +02:00
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2008-08-19 10:08:43 +02:00
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};
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static struct powerdomain per_pwrdm = {
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.name = "per_pwrdm",
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.prcm_offs = OMAP3430_PER_MOD,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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2011-03-08 03:28:15 +01:00
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[0] = PWRSTS_RET, /* MEMRETSTATE */
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2008-08-19 10:08:43 +02:00
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},
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.pwrsts_mem_on = {
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2011-03-08 03:28:15 +01:00
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[0] = PWRSTS_ON, /* MEMONSTATE */
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2008-08-19 10:08:43 +02:00
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2008-08-19 10:08:43 +02:00
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};
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2012-06-28 02:43:59 +02:00
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static struct powerdomain per_am35x_pwrdm = {
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.name = "per_pwrdm",
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.prcm_offs = OMAP3430_PER_MOD,
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.pwrsts = PWRSTS_ON,
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.pwrsts_logic_ret = PWRSTS_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_ON, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* MEMONSTATE */
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},
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2012-06-28 02:43:59 +02:00
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};
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2008-08-19 10:08:43 +02:00
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static struct powerdomain emu_pwrdm = {
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.name = "emu_pwrdm",
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.prcm_offs = OMAP3430_EMU_MOD,
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "core" },
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2008-08-19 10:08:43 +02:00
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};
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static struct powerdomain neon_pwrdm = {
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.name = "neon_pwrdm",
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.prcm_offs = OMAP3430_NEON_MOD,
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.pwrsts = PWRSTS_OFF_RET_ON,
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2011-03-08 03:28:15 +01:00
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.pwrsts_logic_ret = PWRSTS_RET,
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2013-01-26 08:58:17 +01:00
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.voltdm = { .name = "mpu_iva" },
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2008-08-19 10:08:43 +02:00
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};
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2012-06-28 02:43:59 +02:00
|
|
|
static struct powerdomain neon_am35x_pwrdm = {
|
|
|
|
.name = "neon_pwrdm",
|
|
|
|
.prcm_offs = OMAP3430_NEON_MOD,
|
|
|
|
.pwrsts = PWRSTS_ON,
|
|
|
|
.pwrsts_logic_ret = PWRSTS_ON,
|
2013-01-26 08:58:17 +01:00
|
|
|
.voltdm = { .name = "mpu_iva" },
|
2012-06-28 02:43:59 +02:00
|
|
|
};
|
|
|
|
|
2008-08-19 10:08:43 +02:00
|
|
|
static struct powerdomain usbhost_pwrdm = {
|
|
|
|
.name = "usbhost_pwrdm",
|
|
|
|
.prcm_offs = OMAP3430ES2_USBHOST_MOD,
|
|
|
|
.pwrsts = PWRSTS_OFF_RET_ON,
|
2011-03-08 03:28:15 +01:00
|
|
|
.pwrsts_logic_ret = PWRSTS_RET,
|
2009-04-23 12:58:51 +02:00
|
|
|
/*
|
|
|
|
* REVISIT: Enabling usb host save and restore mechanism seems to
|
|
|
|
* leave the usb host domain permanently in ACTIVE mode after
|
|
|
|
* changing the usb host power domain state from OFF to active once.
|
|
|
|
* Disabling for now.
|
|
|
|
*/
|
|
|
|
/*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
|
2008-08-19 10:08:43 +02:00
|
|
|
.banks = 1,
|
|
|
|
.pwrsts_mem_ret = {
|
2011-03-08 03:28:15 +01:00
|
|
|
[0] = PWRSTS_RET, /* MEMRETSTATE */
|
2008-08-19 10:08:43 +02:00
|
|
|
},
|
|
|
|
.pwrsts_mem_on = {
|
2011-03-08 03:28:15 +01:00
|
|
|
[0] = PWRSTS_ON, /* MEMONSTATE */
|
2008-08-19 10:08:43 +02:00
|
|
|
},
|
2013-01-26 08:58:17 +01:00
|
|
|
.voltdm = { .name = "core" },
|
2008-08-19 10:08:43 +02:00
|
|
|
};
|
|
|
|
|
2009-01-28 03:44:18 +01:00
|
|
|
static struct powerdomain dpll1_pwrdm = {
|
|
|
|
.name = "dpll1_pwrdm",
|
|
|
|
.prcm_offs = MPU_MOD,
|
2013-01-26 08:58:17 +01:00
|
|
|
.voltdm = { .name = "mpu_iva" },
|
2009-01-28 03:44:18 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain dpll2_pwrdm = {
|
|
|
|
.name = "dpll2_pwrdm",
|
|
|
|
.prcm_offs = OMAP3430_IVA2_MOD,
|
2013-01-26 08:58:17 +01:00
|
|
|
.voltdm = { .name = "mpu_iva" },
|
2009-01-28 03:44:18 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain dpll3_pwrdm = {
|
|
|
|
.name = "dpll3_pwrdm",
|
|
|
|
.prcm_offs = PLL_MOD,
|
2013-01-26 08:58:17 +01:00
|
|
|
.voltdm = { .name = "core" },
|
2009-01-28 03:44:18 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain dpll4_pwrdm = {
|
|
|
|
.name = "dpll4_pwrdm",
|
|
|
|
.prcm_offs = PLL_MOD,
|
2013-01-26 08:58:17 +01:00
|
|
|
.voltdm = { .name = "core" },
|
2009-01-28 03:44:18 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain dpll5_pwrdm = {
|
|
|
|
.name = "dpll5_pwrdm",
|
|
|
|
.prcm_offs = PLL_MOD,
|
2013-01-26 08:58:17 +01:00
|
|
|
.voltdm = { .name = "core" },
|
2009-01-28 03:44:18 +01:00
|
|
|
};
|
|
|
|
|
2013-08-23 12:48:42 +02:00
|
|
|
static struct powerdomain alwon_81xx_pwrdm = {
|
|
|
|
.name = "alwon_pwrdm",
|
|
|
|
.prcm_offs = TI81XX_PRM_ALWON_MOD,
|
|
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
|
|
.voltdm = { .name = "core" },
|
|
|
|
};
|
|
|
|
|
2013-05-30 17:04:50 +02:00
|
|
|
static struct powerdomain device_81xx_pwrdm = {
|
|
|
|
.name = "device_pwrdm",
|
|
|
|
.prcm_offs = TI81XX_PRM_DEVICE_MOD,
|
|
|
|
.voltdm = { .name = "core" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain active_816x_pwrdm = {
|
|
|
|
.name = "active_pwrdm",
|
|
|
|
.prcm_offs = TI816X_PRM_ACTIVE_MOD,
|
|
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
|
|
.voltdm = { .name = "core" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain default_816x_pwrdm = {
|
|
|
|
.name = "default_pwrdm",
|
|
|
|
.prcm_offs = TI81XX_PRM_DEFAULT_MOD,
|
|
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
|
|
.voltdm = { .name = "core" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain ivahd0_816x_pwrdm = {
|
|
|
|
.name = "ivahd0_pwrdm",
|
|
|
|
.prcm_offs = TI816X_PRM_IVAHD0_MOD,
|
|
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
|
|
.voltdm = { .name = "mpu_iva" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain ivahd1_816x_pwrdm = {
|
|
|
|
.name = "ivahd1_pwrdm",
|
|
|
|
.prcm_offs = TI816X_PRM_IVAHD1_MOD,
|
|
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
|
|
.voltdm = { .name = "mpu_iva" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain ivahd2_816x_pwrdm = {
|
|
|
|
.name = "ivahd2_pwrdm",
|
|
|
|
.prcm_offs = TI816X_PRM_IVAHD2_MOD,
|
|
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
|
|
.voltdm = { .name = "mpu_iva" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain sgx_816x_pwrdm = {
|
|
|
|
.name = "sgx_pwrdm",
|
|
|
|
.prcm_offs = TI816X_PRM_SGX_MOD,
|
|
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
|
|
.voltdm = { .name = "core" },
|
|
|
|
};
|
|
|
|
|
2010-12-22 04:01:20 +01:00
|
|
|
/* As powerdomains are added or removed above, this list must also be changed */
|
2011-09-14 19:34:21 +02:00
|
|
|
static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
|
2010-12-22 04:01:20 +01:00
|
|
|
&wkup_omap2_pwrdm,
|
|
|
|
&iva2_pwrdm,
|
|
|
|
&mpu_3xxx_pwrdm,
|
|
|
|
&neon_pwrdm,
|
|
|
|
&cam_pwrdm,
|
|
|
|
&dss_pwrdm,
|
|
|
|
&per_pwrdm,
|
|
|
|
&emu_pwrdm,
|
|
|
|
&dpll1_pwrdm,
|
|
|
|
&dpll2_pwrdm,
|
|
|
|
&dpll3_pwrdm,
|
|
|
|
&dpll4_pwrdm,
|
2011-09-14 19:34:21 +02:00
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
|
|
|
|
&gfx_omap2_pwrdm,
|
|
|
|
&core_3xxx_pre_es3_1_pwrdm,
|
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
/* also includes 3630ES1.0 */
|
|
|
|
static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
|
|
|
|
&core_3xxx_pre_es3_1_pwrdm,
|
|
|
|
&sgx_pwrdm,
|
|
|
|
&usbhost_pwrdm,
|
2010-12-22 04:01:20 +01:00
|
|
|
&dpll5_pwrdm,
|
|
|
|
NULL
|
|
|
|
};
|
2008-08-19 10:08:43 +02:00
|
|
|
|
2011-09-14 19:34:21 +02:00
|
|
|
/* also includes 3630ES1.1+ */
|
|
|
|
static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
|
|
|
|
&core_3xxx_es3_1_pwrdm,
|
|
|
|
&sgx_pwrdm,
|
|
|
|
&usbhost_pwrdm,
|
|
|
|
&dpll5_pwrdm,
|
|
|
|
NULL
|
|
|
|
};
|
2008-08-19 10:08:43 +02:00
|
|
|
|
2012-06-28 02:43:59 +02:00
|
|
|
static struct powerdomain *powerdomains_am35x[] __initdata = {
|
|
|
|
&wkup_omap2_pwrdm,
|
|
|
|
&mpu_am35x_pwrdm,
|
|
|
|
&neon_am35x_pwrdm,
|
|
|
|
&core_am35x_pwrdm,
|
|
|
|
&sgx_am35x_pwrdm,
|
|
|
|
&dss_am35x_pwrdm,
|
|
|
|
&per_am35x_pwrdm,
|
|
|
|
&emu_pwrdm,
|
|
|
|
&dpll1_pwrdm,
|
|
|
|
&dpll3_pwrdm,
|
|
|
|
&dpll4_pwrdm,
|
|
|
|
&dpll5_pwrdm,
|
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
2013-05-30 17:04:50 +02:00
|
|
|
static struct powerdomain *powerdomains_ti81xx[] __initdata = {
|
2013-08-23 12:48:42 +02:00
|
|
|
&alwon_81xx_pwrdm,
|
2013-05-30 17:04:50 +02:00
|
|
|
&device_81xx_pwrdm,
|
|
|
|
&active_816x_pwrdm,
|
|
|
|
&default_816x_pwrdm,
|
|
|
|
&ivahd0_816x_pwrdm,
|
|
|
|
&ivahd1_816x_pwrdm,
|
|
|
|
&ivahd2_816x_pwrdm,
|
|
|
|
&sgx_816x_pwrdm,
|
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
2010-12-22 04:01:20 +01:00
|
|
|
void __init omap3xxx_powerdomains_init(void)
|
|
|
|
{
|
2011-09-14 19:34:21 +02:00
|
|
|
unsigned int rev;
|
|
|
|
|
2015-01-15 02:37:16 +01:00
|
|
|
if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
|
2011-09-14 19:34:21 +02:00
|
|
|
return;
|
|
|
|
|
2011-09-15 00:01:21 +02:00
|
|
|
pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
|
2011-09-14 19:34:21 +02:00
|
|
|
|
|
|
|
rev = omap_rev();
|
|
|
|
|
2012-06-28 02:43:59 +02:00
|
|
|
if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
|
|
|
|
pwrdm_register_pwrdms(powerdomains_am35x);
|
2013-05-30 17:04:50 +02:00
|
|
|
} else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
|
|
|
|
|| rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
|
|
|
|
pwrdm_register_pwrdms(powerdomains_ti81xx);
|
2012-06-28 02:43:59 +02:00
|
|
|
} else {
|
|
|
|
pwrdm_register_pwrdms(powerdomains_omap3430_common);
|
|
|
|
|
|
|
|
switch (rev) {
|
|
|
|
case OMAP3430_REV_ES1_0:
|
|
|
|
pwrdm_register_pwrdms(powerdomains_omap3430es1);
|
|
|
|
break;
|
|
|
|
case OMAP3430_REV_ES2_0:
|
|
|
|
case OMAP3430_REV_ES2_1:
|
|
|
|
case OMAP3430_REV_ES3_0:
|
|
|
|
case OMAP3630_REV_ES1_0:
|
|
|
|
pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
|
|
|
|
break;
|
|
|
|
case OMAP3430_REV_ES3_1:
|
|
|
|
case OMAP3430_REV_ES3_1_2:
|
|
|
|
case OMAP3630_REV_ES1_1:
|
|
|
|
case OMAP3630_REV_ES1_2:
|
|
|
|
pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
|
|
|
|
}
|
|
|
|
}
|
2011-09-14 19:34:21 +02:00
|
|
|
|
2011-09-15 00:01:21 +02:00
|
|
|
pwrdm_complete_init();
|
2010-12-22 04:01:20 +01:00
|
|
|
}
|