2006-01-17 16:33:01 +01:00
|
|
|
/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
|
|
|
|
* Copyright (C) 2006 Kyle McMartin <kyle@parisc-linux.org>
|
|
|
|
*/
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
#ifndef _ASM_PARISC_ATOMIC_H_
|
|
|
|
#define _ASM_PARISC_ATOMIC_H_
|
|
|
|
|
2006-01-17 16:33:01 +01:00
|
|
|
#include <linux/types.h>
|
2007-05-08 09:34:38 +02:00
|
|
|
#include <asm/system.h>
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Atomic operations that C can't guarantee us. Useful for
|
|
|
|
* resource counting etc..
|
|
|
|
*
|
|
|
|
* And probably incredibly slow on parisc. OTOH, we don't
|
|
|
|
* have to write any serious assembly. prumpf
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
#include <asm/spinlock.h>
|
|
|
|
#include <asm/cache.h> /* we use L1_CACHE_BYTES */
|
|
|
|
|
|
|
|
/* Use an array of spinlocks for our atomic_ts.
|
|
|
|
* Hash function to index into a different SPINLOCK.
|
|
|
|
* Since "a" is usually an address, use one spinlock per cacheline.
|
|
|
|
*/
|
|
|
|
# define ATOMIC_HASH_SIZE 4
|
|
|
|
# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
|
|
|
|
|
[PATCH] spinlock consolidation
This patch (written by me and also containing many suggestions of Arjan van
de Ven) does a major cleanup of the spinlock code. It does the following
things:
- consolidates and enhances the spinlock/rwlock debugging code
- simplifies the asm/spinlock.h files
- encapsulates the raw spinlock type and moves generic spinlock
features (such as ->break_lock) into the generic code.
- cleans up the spinlock code hierarchy to get rid of the spaghetti.
Most notably there's now only a single variant of the debugging code,
located in lib/spinlock_debug.c. (previously we had one SMP debugging
variant per architecture, plus a separate generic one for UP builds)
Also, i've enhanced the rwlock debugging facility, it will now track
write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too.
All locks have lockup detection now, which will work for both soft and hard
spin/rwlock lockups.
The arch-level include files now only contain the minimally necessary
subset of the spinlock code - all the rest that can be generalized now
lives in the generic headers:
include/asm-i386/spinlock_types.h | 16
include/asm-x86_64/spinlock_types.h | 16
I have also split up the various spinlock variants into separate files,
making it easier to see which does what. The new layout is:
SMP | UP
----------------------------|-----------------------------------
asm/spinlock_types_smp.h | linux/spinlock_types_up.h
linux/spinlock_types.h | linux/spinlock_types.h
asm/spinlock_smp.h | linux/spinlock_up.h
linux/spinlock_api_smp.h | linux/spinlock_api_up.h
linux/spinlock.h | linux/spinlock.h
/*
* here's the role of the various spinlock/rwlock related include files:
*
* on SMP builds:
*
* asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the
* initializers
*
* linux/spinlock_types.h:
* defines the generic type and initializers
*
* asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel
* implementations, mostly inline assembly code
*
* (also included on UP-debug builds:)
*
* linux/spinlock_api_smp.h:
* contains the prototypes for the _spin_*() APIs.
*
* linux/spinlock.h: builds the final spin_*() APIs.
*
* on UP builds:
*
* linux/spinlock_type_up.h:
* contains the generic, simplified UP spinlock type.
* (which is an empty structure on non-debug builds)
*
* linux/spinlock_types.h:
* defines the generic type and initializers
*
* linux/spinlock_up.h:
* contains the __raw_spin_*()/etc. version of UP
* builds. (which are NOPs on non-debug, non-preempt
* builds)
*
* (included on UP-non-debug builds:)
*
* linux/spinlock_api_up.h:
* builds the _spin_*() APIs.
*
* linux/spinlock.h: builds the final spin_*() APIs.
*/
All SMP and UP architectures are converted by this patch.
arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via
crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should
be mostly fine.
From: Grant Grundler <grundler@parisc-linux.org>
Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU).
Builds 32-bit SMP kernel (not booted or tested). I did not try to build
non-SMP kernels. That should be trivial to fix up later if necessary.
I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids
some ugly nesting of linux/*.h and asm/*.h files. Those particular locks
are well tested and contained entirely inside arch specific code. I do NOT
expect any new issues to arise with them.
If someone does ever need to use debug/metrics with them, then they will
need to unravel this hairball between spinlocks, atomic ops, and bit ops
that exist only because parisc has exactly one atomic instruction: LDCW
(load and clear word).
From: "Luck, Tony" <tony.luck@intel.com>
ia64 fix
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjanv@infradead.org>
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Cc: Matthew Wilcox <willy@debian.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se>
Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-10 09:25:56 +02:00
|
|
|
extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
[PATCH] spinlock consolidation
This patch (written by me and also containing many suggestions of Arjan van
de Ven) does a major cleanup of the spinlock code. It does the following
things:
- consolidates and enhances the spinlock/rwlock debugging code
- simplifies the asm/spinlock.h files
- encapsulates the raw spinlock type and moves generic spinlock
features (such as ->break_lock) into the generic code.
- cleans up the spinlock code hierarchy to get rid of the spaghetti.
Most notably there's now only a single variant of the debugging code,
located in lib/spinlock_debug.c. (previously we had one SMP debugging
variant per architecture, plus a separate generic one for UP builds)
Also, i've enhanced the rwlock debugging facility, it will now track
write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too.
All locks have lockup detection now, which will work for both soft and hard
spin/rwlock lockups.
The arch-level include files now only contain the minimally necessary
subset of the spinlock code - all the rest that can be generalized now
lives in the generic headers:
include/asm-i386/spinlock_types.h | 16
include/asm-x86_64/spinlock_types.h | 16
I have also split up the various spinlock variants into separate files,
making it easier to see which does what. The new layout is:
SMP | UP
----------------------------|-----------------------------------
asm/spinlock_types_smp.h | linux/spinlock_types_up.h
linux/spinlock_types.h | linux/spinlock_types.h
asm/spinlock_smp.h | linux/spinlock_up.h
linux/spinlock_api_smp.h | linux/spinlock_api_up.h
linux/spinlock.h | linux/spinlock.h
/*
* here's the role of the various spinlock/rwlock related include files:
*
* on SMP builds:
*
* asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the
* initializers
*
* linux/spinlock_types.h:
* defines the generic type and initializers
*
* asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel
* implementations, mostly inline assembly code
*
* (also included on UP-debug builds:)
*
* linux/spinlock_api_smp.h:
* contains the prototypes for the _spin_*() APIs.
*
* linux/spinlock.h: builds the final spin_*() APIs.
*
* on UP builds:
*
* linux/spinlock_type_up.h:
* contains the generic, simplified UP spinlock type.
* (which is an empty structure on non-debug builds)
*
* linux/spinlock_types.h:
* defines the generic type and initializers
*
* linux/spinlock_up.h:
* contains the __raw_spin_*()/etc. version of UP
* builds. (which are NOPs on non-debug, non-preempt
* builds)
*
* (included on UP-non-debug builds:)
*
* linux/spinlock_api_up.h:
* builds the _spin_*() APIs.
*
* linux/spinlock.h: builds the final spin_*() APIs.
*/
All SMP and UP architectures are converted by this patch.
arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via
crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should
be mostly fine.
From: Grant Grundler <grundler@parisc-linux.org>
Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU).
Builds 32-bit SMP kernel (not booted or tested). I did not try to build
non-SMP kernels. That should be trivial to fix up later if necessary.
I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids
some ugly nesting of linux/*.h and asm/*.h files. Those particular locks
are well tested and contained entirely inside arch specific code. I do NOT
expect any new issues to arise with them.
If someone does ever need to use debug/metrics with them, then they will
need to unravel this hairball between spinlocks, atomic ops, and bit ops
that exist only because parisc has exactly one atomic instruction: LDCW
(load and clear word).
From: "Luck, Tony" <tony.luck@intel.com>
ia64 fix
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjanv@infradead.org>
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Cc: Matthew Wilcox <willy@debian.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se>
Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-10 09:25:56 +02:00
|
|
|
/* Can't use raw_spin_lock_irq because of #include problems, so
|
2005-04-17 00:20:36 +02:00
|
|
|
* this is the substitute */
|
|
|
|
#define _atomic_spin_lock_irqsave(l,f) do { \
|
[PATCH] spinlock consolidation
This patch (written by me and also containing many suggestions of Arjan van
de Ven) does a major cleanup of the spinlock code. It does the following
things:
- consolidates and enhances the spinlock/rwlock debugging code
- simplifies the asm/spinlock.h files
- encapsulates the raw spinlock type and moves generic spinlock
features (such as ->break_lock) into the generic code.
- cleans up the spinlock code hierarchy to get rid of the spaghetti.
Most notably there's now only a single variant of the debugging code,
located in lib/spinlock_debug.c. (previously we had one SMP debugging
variant per architecture, plus a separate generic one for UP builds)
Also, i've enhanced the rwlock debugging facility, it will now track
write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too.
All locks have lockup detection now, which will work for both soft and hard
spin/rwlock lockups.
The arch-level include files now only contain the minimally necessary
subset of the spinlock code - all the rest that can be generalized now
lives in the generic headers:
include/asm-i386/spinlock_types.h | 16
include/asm-x86_64/spinlock_types.h | 16
I have also split up the various spinlock variants into separate files,
making it easier to see which does what. The new layout is:
SMP | UP
----------------------------|-----------------------------------
asm/spinlock_types_smp.h | linux/spinlock_types_up.h
linux/spinlock_types.h | linux/spinlock_types.h
asm/spinlock_smp.h | linux/spinlock_up.h
linux/spinlock_api_smp.h | linux/spinlock_api_up.h
linux/spinlock.h | linux/spinlock.h
/*
* here's the role of the various spinlock/rwlock related include files:
*
* on SMP builds:
*
* asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the
* initializers
*
* linux/spinlock_types.h:
* defines the generic type and initializers
*
* asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel
* implementations, mostly inline assembly code
*
* (also included on UP-debug builds:)
*
* linux/spinlock_api_smp.h:
* contains the prototypes for the _spin_*() APIs.
*
* linux/spinlock.h: builds the final spin_*() APIs.
*
* on UP builds:
*
* linux/spinlock_type_up.h:
* contains the generic, simplified UP spinlock type.
* (which is an empty structure on non-debug builds)
*
* linux/spinlock_types.h:
* defines the generic type and initializers
*
* linux/spinlock_up.h:
* contains the __raw_spin_*()/etc. version of UP
* builds. (which are NOPs on non-debug, non-preempt
* builds)
*
* (included on UP-non-debug builds:)
*
* linux/spinlock_api_up.h:
* builds the _spin_*() APIs.
*
* linux/spinlock.h: builds the final spin_*() APIs.
*/
All SMP and UP architectures are converted by this patch.
arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via
crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should
be mostly fine.
From: Grant Grundler <grundler@parisc-linux.org>
Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU).
Builds 32-bit SMP kernel (not booted or tested). I did not try to build
non-SMP kernels. That should be trivial to fix up later if necessary.
I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids
some ugly nesting of linux/*.h and asm/*.h files. Those particular locks
are well tested and contained entirely inside arch specific code. I do NOT
expect any new issues to arise with them.
If someone does ever need to use debug/metrics with them, then they will
need to unravel this hairball between spinlocks, atomic ops, and bit ops
that exist only because parisc has exactly one atomic instruction: LDCW
(load and clear word).
From: "Luck, Tony" <tony.luck@intel.com>
ia64 fix
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjanv@infradead.org>
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Cc: Matthew Wilcox <willy@debian.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se>
Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-10 09:25:56 +02:00
|
|
|
raw_spinlock_t *s = ATOMIC_HASH(l); \
|
2005-04-17 00:20:36 +02:00
|
|
|
local_irq_save(f); \
|
[PATCH] spinlock consolidation
This patch (written by me and also containing many suggestions of Arjan van
de Ven) does a major cleanup of the spinlock code. It does the following
things:
- consolidates and enhances the spinlock/rwlock debugging code
- simplifies the asm/spinlock.h files
- encapsulates the raw spinlock type and moves generic spinlock
features (such as ->break_lock) into the generic code.
- cleans up the spinlock code hierarchy to get rid of the spaghetti.
Most notably there's now only a single variant of the debugging code,
located in lib/spinlock_debug.c. (previously we had one SMP debugging
variant per architecture, plus a separate generic one for UP builds)
Also, i've enhanced the rwlock debugging facility, it will now track
write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too.
All locks have lockup detection now, which will work for both soft and hard
spin/rwlock lockups.
The arch-level include files now only contain the minimally necessary
subset of the spinlock code - all the rest that can be generalized now
lives in the generic headers:
include/asm-i386/spinlock_types.h | 16
include/asm-x86_64/spinlock_types.h | 16
I have also split up the various spinlock variants into separate files,
making it easier to see which does what. The new layout is:
SMP | UP
----------------------------|-----------------------------------
asm/spinlock_types_smp.h | linux/spinlock_types_up.h
linux/spinlock_types.h | linux/spinlock_types.h
asm/spinlock_smp.h | linux/spinlock_up.h
linux/spinlock_api_smp.h | linux/spinlock_api_up.h
linux/spinlock.h | linux/spinlock.h
/*
* here's the role of the various spinlock/rwlock related include files:
*
* on SMP builds:
*
* asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the
* initializers
*
* linux/spinlock_types.h:
* defines the generic type and initializers
*
* asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel
* implementations, mostly inline assembly code
*
* (also included on UP-debug builds:)
*
* linux/spinlock_api_smp.h:
* contains the prototypes for the _spin_*() APIs.
*
* linux/spinlock.h: builds the final spin_*() APIs.
*
* on UP builds:
*
* linux/spinlock_type_up.h:
* contains the generic, simplified UP spinlock type.
* (which is an empty structure on non-debug builds)
*
* linux/spinlock_types.h:
* defines the generic type and initializers
*
* linux/spinlock_up.h:
* contains the __raw_spin_*()/etc. version of UP
* builds. (which are NOPs on non-debug, non-preempt
* builds)
*
* (included on UP-non-debug builds:)
*
* linux/spinlock_api_up.h:
* builds the _spin_*() APIs.
*
* linux/spinlock.h: builds the final spin_*() APIs.
*/
All SMP and UP architectures are converted by this patch.
arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via
crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should
be mostly fine.
From: Grant Grundler <grundler@parisc-linux.org>
Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU).
Builds 32-bit SMP kernel (not booted or tested). I did not try to build
non-SMP kernels. That should be trivial to fix up later if necessary.
I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids
some ugly nesting of linux/*.h and asm/*.h files. Those particular locks
are well tested and contained entirely inside arch specific code. I do NOT
expect any new issues to arise with them.
If someone does ever need to use debug/metrics with them, then they will
need to unravel this hairball between spinlocks, atomic ops, and bit ops
that exist only because parisc has exactly one atomic instruction: LDCW
(load and clear word).
From: "Luck, Tony" <tony.luck@intel.com>
ia64 fix
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjanv@infradead.org>
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Cc: Matthew Wilcox <willy@debian.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se>
Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-10 09:25:56 +02:00
|
|
|
__raw_spin_lock(s); \
|
2005-04-17 00:20:36 +02:00
|
|
|
} while(0)
|
|
|
|
|
|
|
|
#define _atomic_spin_unlock_irqrestore(l,f) do { \
|
[PATCH] spinlock consolidation
This patch (written by me and also containing many suggestions of Arjan van
de Ven) does a major cleanup of the spinlock code. It does the following
things:
- consolidates and enhances the spinlock/rwlock debugging code
- simplifies the asm/spinlock.h files
- encapsulates the raw spinlock type and moves generic spinlock
features (such as ->break_lock) into the generic code.
- cleans up the spinlock code hierarchy to get rid of the spaghetti.
Most notably there's now only a single variant of the debugging code,
located in lib/spinlock_debug.c. (previously we had one SMP debugging
variant per architecture, plus a separate generic one for UP builds)
Also, i've enhanced the rwlock debugging facility, it will now track
write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too.
All locks have lockup detection now, which will work for both soft and hard
spin/rwlock lockups.
The arch-level include files now only contain the minimally necessary
subset of the spinlock code - all the rest that can be generalized now
lives in the generic headers:
include/asm-i386/spinlock_types.h | 16
include/asm-x86_64/spinlock_types.h | 16
I have also split up the various spinlock variants into separate files,
making it easier to see which does what. The new layout is:
SMP | UP
----------------------------|-----------------------------------
asm/spinlock_types_smp.h | linux/spinlock_types_up.h
linux/spinlock_types.h | linux/spinlock_types.h
asm/spinlock_smp.h | linux/spinlock_up.h
linux/spinlock_api_smp.h | linux/spinlock_api_up.h
linux/spinlock.h | linux/spinlock.h
/*
* here's the role of the various spinlock/rwlock related include files:
*
* on SMP builds:
*
* asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the
* initializers
*
* linux/spinlock_types.h:
* defines the generic type and initializers
*
* asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel
* implementations, mostly inline assembly code
*
* (also included on UP-debug builds:)
*
* linux/spinlock_api_smp.h:
* contains the prototypes for the _spin_*() APIs.
*
* linux/spinlock.h: builds the final spin_*() APIs.
*
* on UP builds:
*
* linux/spinlock_type_up.h:
* contains the generic, simplified UP spinlock type.
* (which is an empty structure on non-debug builds)
*
* linux/spinlock_types.h:
* defines the generic type and initializers
*
* linux/spinlock_up.h:
* contains the __raw_spin_*()/etc. version of UP
* builds. (which are NOPs on non-debug, non-preempt
* builds)
*
* (included on UP-non-debug builds:)
*
* linux/spinlock_api_up.h:
* builds the _spin_*() APIs.
*
* linux/spinlock.h: builds the final spin_*() APIs.
*/
All SMP and UP architectures are converted by this patch.
arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via
crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should
be mostly fine.
From: Grant Grundler <grundler@parisc-linux.org>
Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU).
Builds 32-bit SMP kernel (not booted or tested). I did not try to build
non-SMP kernels. That should be trivial to fix up later if necessary.
I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids
some ugly nesting of linux/*.h and asm/*.h files. Those particular locks
are well tested and contained entirely inside arch specific code. I do NOT
expect any new issues to arise with them.
If someone does ever need to use debug/metrics with them, then they will
need to unravel this hairball between spinlocks, atomic ops, and bit ops
that exist only because parisc has exactly one atomic instruction: LDCW
(load and clear word).
From: "Luck, Tony" <tony.luck@intel.com>
ia64 fix
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjanv@infradead.org>
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Cc: Matthew Wilcox <willy@debian.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se>
Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-10 09:25:56 +02:00
|
|
|
raw_spinlock_t *s = ATOMIC_HASH(l); \
|
|
|
|
__raw_spin_unlock(s); \
|
2005-04-17 00:20:36 +02:00
|
|
|
local_irq_restore(f); \
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
|
|
|
|
#else
|
|
|
|
# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
|
|
|
|
# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* This should get optimized out since it's never called.
|
|
|
|
** Or get a link error if xchg is used "wrong".
|
|
|
|
*/
|
|
|
|
extern void __xchg_called_with_bad_pointer(void);
|
|
|
|
|
|
|
|
|
|
|
|
/* __xchg32/64 defined in arch/parisc/lib/bitops.c */
|
|
|
|
extern unsigned long __xchg8(char, char *);
|
|
|
|
extern unsigned long __xchg32(int, int *);
|
2007-01-28 15:09:20 +01:00
|
|
|
#ifdef CONFIG_64BIT
|
2005-04-17 00:20:36 +02:00
|
|
|
extern unsigned long __xchg64(unsigned long, unsigned long *);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* optimizer better get rid of switch since size is a constant */
|
2006-01-17 16:33:01 +01:00
|
|
|
static __inline__ unsigned long
|
|
|
|
__xchg(unsigned long x, __volatile__ void * ptr, int size)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
switch(size) {
|
2007-01-28 15:09:20 +01:00
|
|
|
#ifdef CONFIG_64BIT
|
2005-04-17 00:20:36 +02:00
|
|
|
case 8: return __xchg64(x,(unsigned long *) ptr);
|
|
|
|
#endif
|
|
|
|
case 4: return __xchg32((int) x, (int *) ptr);
|
|
|
|
case 1: return __xchg8((char) x, (char *) ptr);
|
|
|
|
}
|
|
|
|
__xchg_called_with_bad_pointer();
|
|
|
|
return x;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
** REVISIT - Abandoned use of LDCW in xchg() for now:
|
|
|
|
** o need to test sizeof(*ptr) to avoid clearing adjacent bytes
|
2007-01-28 15:09:20 +01:00
|
|
|
** o and while we are at it, could CONFIG_64BIT code use LDCD too?
|
2005-04-17 00:20:36 +02:00
|
|
|
**
|
|
|
|
** if (__builtin_constant_p(x) && (x == NULL))
|
|
|
|
** if (((unsigned long)p & 0xf) == 0)
|
|
|
|
** return __ldcw(p);
|
|
|
|
*/
|
|
|
|
#define xchg(ptr,x) \
|
|
|
|
((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
|
|
|
|
|
|
|
|
|
|
|
|
#define __HAVE_ARCH_CMPXCHG 1
|
|
|
|
|
|
|
|
/* bug catcher for when unsupported size is used - won't link */
|
|
|
|
extern void __cmpxchg_called_with_bad_pointer(void);
|
|
|
|
|
|
|
|
/* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */
|
|
|
|
extern unsigned long __cmpxchg_u32(volatile unsigned int *m, unsigned int old, unsigned int new_);
|
|
|
|
extern unsigned long __cmpxchg_u64(volatile unsigned long *ptr, unsigned long old, unsigned long new_);
|
|
|
|
|
|
|
|
/* don't worry...optimizer will get rid of most of this */
|
|
|
|
static __inline__ unsigned long
|
|
|
|
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
|
|
|
|
{
|
|
|
|
switch(size) {
|
2007-01-28 15:09:20 +01:00
|
|
|
#ifdef CONFIG_64BIT
|
2005-04-17 00:20:36 +02:00
|
|
|
case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
|
|
|
|
#endif
|
|
|
|
case 4: return __cmpxchg_u32((unsigned int *)ptr, (unsigned int) old, (unsigned int) new_);
|
|
|
|
}
|
|
|
|
__cmpxchg_called_with_bad_pointer();
|
|
|
|
return old;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define cmpxchg(ptr,o,n) \
|
|
|
|
({ \
|
|
|
|
__typeof__(*(ptr)) _o_ = (o); \
|
|
|
|
__typeof__(*(ptr)) _n_ = (n); \
|
|
|
|
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
|
|
|
|
(unsigned long)_n_, sizeof(*(ptr))); \
|
|
|
|
})
|
|
|
|
|
2008-02-07 09:16:21 +01:00
|
|
|
#include <asm-generic/cmpxchg-local.h>
|
|
|
|
|
|
|
|
static inline unsigned long __cmpxchg_local(volatile void *ptr,
|
|
|
|
unsigned long old,
|
|
|
|
unsigned long new_, int size)
|
|
|
|
{
|
|
|
|
switch (size) {
|
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
|
|
|
|
#endif
|
|
|
|
case 4: return __cmpxchg_u32(ptr, old, new_);
|
|
|
|
default:
|
|
|
|
return __cmpxchg_local_generic(ptr, old, new_, size);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
|
|
|
|
* them available.
|
|
|
|
*/
|
|
|
|
#define cmpxchg_local(ptr, o, n) \
|
|
|
|
((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
|
|
|
|
(unsigned long)(n), sizeof(*(ptr))))
|
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
#define cmpxchg64_local(ptr, o, n) \
|
|
|
|
({ \
|
|
|
|
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
|
|
|
|
cmpxchg_local((ptr), (o), (n)); \
|
|
|
|
})
|
|
|
|
#else
|
|
|
|
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
|
|
|
|
#endif
|
|
|
|
|
2009-01-06 23:40:39 +01:00
|
|
|
/*
|
|
|
|
* Note that we need not lock read accesses - aligned word writes/reads
|
|
|
|
* are atomic, so a reader never sees inconsistent values.
|
2006-01-17 16:33:01 +01:00
|
|
|
*/
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* It's possible to reduce all atomic operations to either
|
|
|
|
* __atomic_add_return, atomic_set and atomic_read (the latter
|
|
|
|
* is there only for consistency).
|
|
|
|
*/
|
|
|
|
|
|
|
|
static __inline__ int __atomic_add_return(int i, atomic_t *v)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
unsigned long flags;
|
|
|
|
_atomic_spin_lock_irqsave(v, flags);
|
|
|
|
|
|
|
|
ret = (v->counter += i);
|
|
|
|
|
|
|
|
_atomic_spin_unlock_irqrestore(v, flags);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __inline__ void atomic_set(atomic_t *v, int i)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
_atomic_spin_lock_irqsave(v, flags);
|
|
|
|
|
|
|
|
v->counter = i;
|
|
|
|
|
|
|
|
_atomic_spin_unlock_irqrestore(v, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static __inline__ int atomic_read(const atomic_t *v)
|
|
|
|
{
|
|
|
|
return v->counter;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* exported interface */
|
2007-05-08 09:34:26 +02:00
|
|
|
#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
|
2006-01-10 00:59:17 +01:00
|
|
|
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-11-14 01:07:25 +01:00
|
|
|
/**
|
|
|
|
* atomic_add_unless - add unless the number is a given value
|
|
|
|
* @v: pointer of type atomic_t
|
|
|
|
* @a: the amount to add to v...
|
|
|
|
* @u: ...unless v is equal to u.
|
|
|
|
*
|
|
|
|
* Atomically adds @a to @v, so long as it was not @u.
|
|
|
|
* Returns non-zero if @v was not @u, and zero otherwise.
|
|
|
|
*/
|
2007-05-08 09:34:38 +02:00
|
|
|
static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
|
|
|
|
{
|
|
|
|
int c, old;
|
|
|
|
c = atomic_read(v);
|
|
|
|
for (;;) {
|
|
|
|
if (unlikely(c == (u)))
|
|
|
|
break;
|
|
|
|
old = atomic_cmpxchg((v), c, c + (a));
|
|
|
|
if (likely(old == c))
|
|
|
|
break;
|
|
|
|
c = old;
|
|
|
|
}
|
|
|
|
return c != (u);
|
|
|
|
}
|
|
|
|
|
2005-11-14 01:07:25 +01:00
|
|
|
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
#define atomic_add(i,v) ((void)(__atomic_add_return( ((int)i),(v))))
|
|
|
|
#define atomic_sub(i,v) ((void)(__atomic_add_return(-((int)i),(v))))
|
|
|
|
#define atomic_inc(v) ((void)(__atomic_add_return( 1,(v))))
|
|
|
|
#define atomic_dec(v) ((void)(__atomic_add_return( -1,(v))))
|
|
|
|
|
|
|
|
#define atomic_add_return(i,v) (__atomic_add_return( ((int)i),(v)))
|
|
|
|
#define atomic_sub_return(i,v) (__atomic_add_return(-((int)i),(v)))
|
|
|
|
#define atomic_inc_return(v) (__atomic_add_return( 1,(v)))
|
|
|
|
#define atomic_dec_return(v) (__atomic_add_return( -1,(v)))
|
|
|
|
|
|
|
|
#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* atomic_inc_and_test - increment and test
|
|
|
|
* @v: pointer of type atomic_t
|
|
|
|
*
|
|
|
|
* Atomically increments @v by 1
|
|
|
|
* and returns true if the result is zero, or false for all
|
|
|
|
* other cases.
|
|
|
|
*/
|
|
|
|
#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
|
|
|
|
|
|
|
|
#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
|
|
|
|
|
2006-03-30 02:47:32 +02:00
|
|
|
#define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0)
|
|
|
|
|
2006-01-17 16:33:01 +01:00
|
|
|
#define ATOMIC_INIT(i) ((atomic_t) { (i) })
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
#define smp_mb__before_atomic_dec() smp_mb()
|
|
|
|
#define smp_mb__after_atomic_dec() smp_mb()
|
|
|
|
#define smp_mb__before_atomic_inc() smp_mb()
|
|
|
|
#define smp_mb__after_atomic_inc() smp_mb()
|
|
|
|
|
2007-01-28 15:09:20 +01:00
|
|
|
#ifdef CONFIG_64BIT
|
2006-01-17 16:33:01 +01:00
|
|
|
|
|
|
|
#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })
|
|
|
|
|
|
|
|
static __inline__ int
|
|
|
|
__atomic64_add_return(s64 i, atomic64_t *v)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
unsigned long flags;
|
|
|
|
_atomic_spin_lock_irqsave(v, flags);
|
|
|
|
|
|
|
|
ret = (v->counter += i);
|
|
|
|
|
|
|
|
_atomic_spin_unlock_irqrestore(v, flags);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __inline__ void
|
|
|
|
atomic64_set(atomic64_t *v, s64 i)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
_atomic_spin_lock_irqsave(v, flags);
|
|
|
|
|
|
|
|
v->counter = i;
|
|
|
|
|
|
|
|
_atomic_spin_unlock_irqrestore(v, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static __inline__ s64
|
|
|
|
atomic64_read(const atomic64_t *v)
|
|
|
|
{
|
|
|
|
return v->counter;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define atomic64_add(i,v) ((void)(__atomic64_add_return( ((s64)i),(v))))
|
|
|
|
#define atomic64_sub(i,v) ((void)(__atomic64_add_return(-((s64)i),(v))))
|
|
|
|
#define atomic64_inc(v) ((void)(__atomic64_add_return( 1,(v))))
|
|
|
|
#define atomic64_dec(v) ((void)(__atomic64_add_return( -1,(v))))
|
|
|
|
|
|
|
|
#define atomic64_add_return(i,v) (__atomic64_add_return( ((s64)i),(v)))
|
|
|
|
#define atomic64_sub_return(i,v) (__atomic64_add_return(-((s64)i),(v)))
|
|
|
|
#define atomic64_inc_return(v) (__atomic64_add_return( 1,(v)))
|
|
|
|
#define atomic64_dec_return(v) (__atomic64_add_return( -1,(v)))
|
|
|
|
|
|
|
|
#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
|
|
|
|
|
|
|
|
#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
|
|
|
|
#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
|
2006-03-30 02:47:32 +02:00
|
|
|
#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i),(v)) == 0)
|
2006-01-17 16:33:01 +01:00
|
|
|
|
2007-05-08 09:34:26 +02:00
|
|
|
/* exported interface */
|
|
|
|
#define atomic64_cmpxchg(v, o, n) \
|
|
|
|
((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
|
|
|
|
#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
|
|
|
|
|
|
|
|
/**
|
|
|
|
* atomic64_add_unless - add unless the number is a given value
|
|
|
|
* @v: pointer of type atomic64_t
|
|
|
|
* @a: the amount to add to v...
|
|
|
|
* @u: ...unless v is equal to u.
|
|
|
|
*
|
|
|
|
* Atomically adds @a to @v, so long as it was not @u.
|
|
|
|
* Returns non-zero if @v was not @u, and zero otherwise.
|
|
|
|
*/
|
2007-05-08 09:34:38 +02:00
|
|
|
static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
|
|
|
|
{
|
|
|
|
long c, old;
|
|
|
|
c = atomic64_read(v);
|
|
|
|
for (;;) {
|
|
|
|
if (unlikely(c == (u)))
|
|
|
|
break;
|
|
|
|
old = atomic64_cmpxchg((v), c, c + (a));
|
|
|
|
if (likely(old == c))
|
|
|
|
break;
|
|
|
|
c = old;
|
|
|
|
}
|
|
|
|
return c != (u);
|
|
|
|
}
|
|
|
|
|
2007-05-08 09:34:26 +02:00
|
|
|
#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
|
|
|
|
|
2007-01-28 15:09:20 +01:00
|
|
|
#endif /* CONFIG_64BIT */
|
2006-01-17 16:33:01 +01:00
|
|
|
|
2006-01-06 09:11:20 +01:00
|
|
|
#include <asm-generic/atomic.h>
|
2006-01-17 16:33:01 +01:00
|
|
|
|
|
|
|
#endif /* _ASM_PARISC_ATOMIC_H_ */
|