2008-07-18 06:55:51 +02:00
|
|
|
#ifndef __SPARC64_PCI_H
|
|
|
|
|
#define __SPARC64_PCI_H
|
|
|
|
|
|
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
|
|
|
|
|
|
#include <linux/dma-mapping.h>
|
|
|
|
|
|
|
|
|
|
/* Can be used to override the logic in pci_scan_bus for skipping
|
|
|
|
|
* already-configured bus numbers - to be used for buggy BIOSes
|
|
|
|
|
* or architectures with incomplete PCI setup by the loader.
|
|
|
|
|
*/
|
|
|
|
|
#define pcibios_assign_all_busses() 0
|
|
|
|
|
|
|
|
|
|
#define PCIBIOS_MIN_IO 0UL
|
|
|
|
|
#define PCIBIOS_MIN_MEM 0UL
|
|
|
|
|
|
|
|
|
|
#define PCI_IRQ_NONE 0xffffffff
|
|
|
|
|
|
|
|
|
|
static inline void pcibios_set_master(struct pci_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
/* No special bus mastering setup handling */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void pcibios_penalize_isa_irq(int irq, int active)
|
|
|
|
|
{
|
|
|
|
|
/* We don't do dynamic PCI IRQ allocation */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The PCI address space does not equal the physical memory
|
|
|
|
|
* address space. The networking and block device layers use
|
|
|
|
|
* this boolean for bounce buffer decisions.
|
|
|
|
|
*/
|
|
|
|
|
#define PCI_DMA_BUS_IS_PHYS (0)
|
|
|
|
|
|
|
|
|
|
/* PCI IOMMU mapping bypass support. */
|
|
|
|
|
|
|
|
|
|
/* PCI 64-bit addressing works for all slots on all controller
|
|
|
|
|
* types on sparc64. However, it requires that the device
|
|
|
|
|
* can drive enough of the 64 bits.
|
|
|
|
|
*/
|
2010-10-28 00:34:47 +02:00
|
|
|
#define PCI64_REQUIRED_MASK (~(u64)0)
|
2008-07-18 06:55:51 +02:00
|
|
|
#define PCI64_ADDR_BASE 0xfffc000000000000UL
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
|
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
|
|
|
|
|
enum pci_dma_burst_strategy *strat,
|
|
|
|
|
unsigned long *strategy_parameter)
|
|
|
|
|
{
|
|
|
|
|
unsigned long cacheline_size;
|
|
|
|
|
u8 byte;
|
|
|
|
|
|
|
|
|
|
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
|
|
|
|
|
if (byte == 0)
|
|
|
|
|
cacheline_size = 1024;
|
|
|
|
|
else
|
|
|
|
|
cacheline_size = (int) byte * 4;
|
|
|
|
|
|
|
|
|
|
*strat = PCI_DMA_BURST_BOUNDARY;
|
|
|
|
|
*strategy_parameter = cacheline_size;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Return the index of the PCI controller for device PDEV. */
|
|
|
|
|
|
|
|
|
|
extern int pci_domain_nr(struct pci_bus *bus);
|
|
|
|
|
static inline int pci_proc_domain(struct pci_bus *bus)
|
|
|
|
|
{
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Platform support for /proc/bus/pci/X/Y mmap()s. */
|
|
|
|
|
|
|
|
|
|
#define HAVE_PCI_MMAP
|
|
|
|
|
#define HAVE_ARCH_PCI_GET_UNMAPPED_AREA
|
|
|
|
|
#define get_pci_unmapped_area get_fb_unmapped_area
|
|
|
|
|
|
|
|
|
|
extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
|
|
|
|
enum pci_mmap_state mmap_state,
|
|
|
|
|
int write_combine);
|
|
|
|
|
|
|
|
|
|
extern void
|
|
|
|
|
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
|
|
|
|
|
struct resource *res);
|
|
|
|
|
|
|
|
|
|
extern void
|
|
|
|
|
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
|
|
|
|
|
struct pci_bus_region *region);
|
|
|
|
|
|
|
|
|
|
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
|
|
|
|
|
{
|
|
|
|
|
return PCI_IRQ_NONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define HAVE_ARCH_PCI_RESOURCE_TO_USER
|
|
|
|
|
extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
|
|
|
|
const struct resource *rsrc,
|
|
|
|
|
resource_size_t *start, resource_size_t *end);
|
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
|
|
|
|
|
|
#endif /* __SPARC64_PCI_H */
|
