2008-09-23 09:05:54 +02:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 David Daney
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*/
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/watch.h>
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/*
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2013-01-22 12:59:30 +01:00
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* Install the watch registers for the current thread. A maximum of
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2008-09-23 09:05:54 +02:00
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* four registers are installed although the machine may have more.
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*/
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2016-03-01 23:19:36 +01:00
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void mips_install_watch_registers(struct task_struct *t)
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2008-09-23 09:05:54 +02:00
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{
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2016-03-01 23:19:36 +01:00
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struct mips3264_watch_reg_state *watches = &t->thread.watch.mips3264;
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2008-09-23 09:05:54 +02:00
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switch (current_cpu_data.watch_reg_use_cnt) {
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default:
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BUG();
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case 4:
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write_c0_watchlo3(watches->watchlo[3]);
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/* Write 1 to the I, R, and W bits to clear them, and
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1 to G so all ASIDs are trapped. */
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2016-03-01 23:19:39 +01:00
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write_c0_watchhi3(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
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watches->watchhi[3]);
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2008-09-23 09:05:54 +02:00
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case 3:
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write_c0_watchlo2(watches->watchlo[2]);
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2016-03-01 23:19:39 +01:00
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write_c0_watchhi2(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
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watches->watchhi[2]);
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2008-09-23 09:05:54 +02:00
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case 2:
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write_c0_watchlo1(watches->watchlo[1]);
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2016-03-01 23:19:39 +01:00
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write_c0_watchhi1(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
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watches->watchhi[1]);
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2008-09-23 09:05:54 +02:00
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case 1:
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write_c0_watchlo0(watches->watchlo[0]);
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2016-03-01 23:19:39 +01:00
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write_c0_watchhi0(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
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watches->watchhi[0]);
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2008-09-23 09:05:54 +02:00
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}
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}
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/*
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* Read back the watchhi registers so the user space debugger has
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* access to the I, R, and W bits. A maximum of four registers are
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* read although the machine may have more.
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*/
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void mips_read_watch_registers(void)
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{
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struct mips3264_watch_reg_state *watches =
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¤t->thread.watch.mips3264;
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switch (current_cpu_data.watch_reg_use_cnt) {
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default:
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BUG();
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case 4:
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2016-03-01 23:19:39 +01:00
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watches->watchhi[3] = (read_c0_watchhi3() &
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(MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
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2008-09-23 09:05:54 +02:00
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case 3:
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2016-03-01 23:19:39 +01:00
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watches->watchhi[2] = (read_c0_watchhi2() &
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(MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
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2008-09-23 09:05:54 +02:00
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case 2:
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2016-03-01 23:19:39 +01:00
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watches->watchhi[1] = (read_c0_watchhi1() &
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(MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
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2008-09-23 09:05:54 +02:00
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case 1:
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2016-03-01 23:19:39 +01:00
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watches->watchhi[0] = (read_c0_watchhi0() &
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(MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
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2008-09-23 09:05:54 +02:00
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}
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if (current_cpu_data.watch_reg_use_cnt == 1 &&
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2016-03-01 23:19:39 +01:00
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(watches->watchhi[0] & MIPS_WATCHHI_IRW) == 0) {
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2008-09-23 09:05:54 +02:00
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/* Pathological case of release 1 architecture that
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* doesn't set the condition bits. We assume that
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* since we got here, the watch condition was met and
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* signal that the conditions requested in watchlo
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* were met. */
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2016-03-01 23:19:39 +01:00
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watches->watchhi[0] |= (watches->watchlo[0] & MIPS_WATCHHI_IRW);
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2008-09-23 09:05:54 +02:00
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}
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}
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/*
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2013-01-22 12:59:30 +01:00
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* Disable all watch registers. Although only four registers are
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2008-09-23 09:05:54 +02:00
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* installed, all are cleared to eliminate the possibility of endless
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* looping in the watch handler.
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*/
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void mips_clear_watch_registers(void)
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{
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switch (current_cpu_data.watch_reg_count) {
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default:
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BUG();
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case 8:
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write_c0_watchlo7(0);
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case 7:
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write_c0_watchlo6(0);
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case 6:
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write_c0_watchlo5(0);
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case 5:
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write_c0_watchlo4(0);
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case 4:
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write_c0_watchlo3(0);
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case 3:
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write_c0_watchlo2(0);
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case 2:
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write_c0_watchlo1(0);
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case 1:
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write_c0_watchlo0(0);
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}
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}
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MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-18 15:38:59 +02:00
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void mips_probe_watch_registers(struct cpuinfo_mips *c)
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2008-09-23 09:05:54 +02:00
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{
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unsigned int t;
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if ((c->options & MIPS_CPU_WATCH) == 0)
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return;
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/*
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* Check which of the I,R and W bits are supported, then
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* disable the register.
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*/
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2016-03-01 23:19:39 +01:00
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write_c0_watchlo0(MIPS_WATCHLO_IRW);
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2013-06-15 17:34:40 +02:00
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back_to_back_c0_hazard();
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2008-09-23 09:05:54 +02:00
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t = read_c0_watchlo0();
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write_c0_watchlo0(0);
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2016-03-01 23:19:39 +01:00
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c->watch_reg_masks[0] = t & MIPS_WATCHLO_IRW;
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2008-09-23 09:05:54 +02:00
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/* Write the mask bits and read them back to determine which
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* can be used. */
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c->watch_reg_count = 1;
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c->watch_reg_use_cnt = 1;
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t = read_c0_watchhi0();
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2016-03-01 23:19:39 +01:00
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write_c0_watchhi0(t | MIPS_WATCHHI_MASK);
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2013-06-15 17:34:40 +02:00
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back_to_back_c0_hazard();
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2008-09-23 09:05:54 +02:00
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t = read_c0_watchhi0();
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2016-03-01 23:19:39 +01:00
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c->watch_reg_masks[0] |= (t & MIPS_WATCHHI_MASK);
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if ((t & MIPS_WATCHHI_M) == 0)
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2008-09-23 09:05:54 +02:00
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return;
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2016-03-01 23:19:39 +01:00
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write_c0_watchlo1(MIPS_WATCHLO_IRW);
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2013-06-15 17:34:40 +02:00
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back_to_back_c0_hazard();
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2008-09-23 09:05:54 +02:00
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t = read_c0_watchlo1();
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write_c0_watchlo1(0);
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2016-03-01 23:19:39 +01:00
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c->watch_reg_masks[1] = t & MIPS_WATCHLO_IRW;
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2008-09-23 09:05:54 +02:00
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c->watch_reg_count = 2;
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c->watch_reg_use_cnt = 2;
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t = read_c0_watchhi1();
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2016-03-01 23:19:39 +01:00
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write_c0_watchhi1(t | MIPS_WATCHHI_MASK);
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2013-06-15 17:34:40 +02:00
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back_to_back_c0_hazard();
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2008-09-23 09:05:54 +02:00
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t = read_c0_watchhi1();
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2016-03-01 23:19:39 +01:00
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c->watch_reg_masks[1] |= (t & MIPS_WATCHHI_MASK);
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if ((t & MIPS_WATCHHI_M) == 0)
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2008-09-23 09:05:54 +02:00
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return;
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2016-03-01 23:19:39 +01:00
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write_c0_watchlo2(MIPS_WATCHLO_IRW);
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2013-06-15 17:34:40 +02:00
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back_to_back_c0_hazard();
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2008-09-23 09:05:54 +02:00
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t = read_c0_watchlo2();
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write_c0_watchlo2(0);
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2016-03-01 23:19:39 +01:00
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c->watch_reg_masks[2] = t & MIPS_WATCHLO_IRW;
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2008-09-23 09:05:54 +02:00
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c->watch_reg_count = 3;
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c->watch_reg_use_cnt = 3;
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t = read_c0_watchhi2();
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2016-03-01 23:19:39 +01:00
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write_c0_watchhi2(t | MIPS_WATCHHI_MASK);
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2013-06-15 17:34:40 +02:00
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back_to_back_c0_hazard();
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2008-09-23 09:05:54 +02:00
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t = read_c0_watchhi2();
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2016-03-01 23:19:39 +01:00
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c->watch_reg_masks[2] |= (t & MIPS_WATCHHI_MASK);
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if ((t & MIPS_WATCHHI_M) == 0)
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2008-09-23 09:05:54 +02:00
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return;
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2016-03-01 23:19:39 +01:00
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write_c0_watchlo3(MIPS_WATCHLO_IRW);
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2013-06-15 17:34:40 +02:00
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back_to_back_c0_hazard();
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2008-09-23 09:05:54 +02:00
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t = read_c0_watchlo3();
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write_c0_watchlo3(0);
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2016-03-01 23:19:39 +01:00
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c->watch_reg_masks[3] = t & MIPS_WATCHLO_IRW;
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2008-09-23 09:05:54 +02:00
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c->watch_reg_count = 4;
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c->watch_reg_use_cnt = 4;
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t = read_c0_watchhi3();
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2016-03-01 23:19:39 +01:00
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write_c0_watchhi3(t | MIPS_WATCHHI_MASK);
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2013-06-15 17:34:40 +02:00
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back_to_back_c0_hazard();
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2008-09-23 09:05:54 +02:00
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t = read_c0_watchhi3();
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2016-03-01 23:19:39 +01:00
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c->watch_reg_masks[3] |= (t & MIPS_WATCHHI_MASK);
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if ((t & MIPS_WATCHHI_M) == 0)
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2008-09-23 09:05:54 +02:00
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return;
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/* We use at most 4, but probe and report up to 8. */
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c->watch_reg_count = 5;
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t = read_c0_watchhi4();
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2016-03-01 23:19:39 +01:00
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if ((t & MIPS_WATCHHI_M) == 0)
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2008-09-23 09:05:54 +02:00
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return;
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c->watch_reg_count = 6;
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t = read_c0_watchhi5();
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2016-03-01 23:19:39 +01:00
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if ((t & MIPS_WATCHHI_M) == 0)
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2008-09-23 09:05:54 +02:00
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return;
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c->watch_reg_count = 7;
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t = read_c0_watchhi6();
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2016-03-01 23:19:39 +01:00
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if ((t & MIPS_WATCHHI_M) == 0)
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2008-09-23 09:05:54 +02:00
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return;
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c->watch_reg_count = 8;
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}
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