170 lines
3.8 KiB
ArmAsm
170 lines
3.8 KiB
ArmAsm
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/* tsb.S: Sparc64 TSB table handling.
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*
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* Copyright (C) 2006 David S. Miller <davem@davemloft.net>
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*/
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#include <asm/tsb.h>
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.text
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.align 32
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/* Invoked from TLB miss handler, we are in the
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* MMU global registers and they are setup like
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* this:
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*
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* %g1: TSB entry pointer
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* %g2: available temporary
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* %g3: FAULT_CODE_{D,I}TLB
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* %g4: available temporary
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* %g5: available temporary
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* %g6: TAG TARGET
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* %g7: physical address base of the linux page
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* tables for the current address space
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*/
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.globl tsb_miss_dtlb
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tsb_miss_dtlb:
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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nop
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.globl tsb_miss_itlb
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tsb_miss_itlb:
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_IMMU, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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nop
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tsb_miss_page_table_walk:
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USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
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tsb_reload:
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TSB_LOCK_TAG(%g1, %g2, %g4)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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brgez,a,pn %g5, tsb_do_fault
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stx %g0, [%g1]
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TSB_WRITE(%g1, %g5, %g6)
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/* Finally, load TLB and return from trap. */
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tsb_tlb_reload:
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cmp %g3, FAULT_CODE_DTLB
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bne,pn %xcc, tsb_itlb_load
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nop
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tsb_dtlb_load:
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stxa %g5, [%g0] ASI_DTLB_DATA_IN
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retry
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tsb_itlb_load:
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stxa %g5, [%g0] ASI_ITLB_DATA_IN
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retry
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/* No valid entry in the page tables, do full fault
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* processing.
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*/
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.globl tsb_do_fault
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tsb_do_fault:
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cmp %g3, FAULT_CODE_DTLB
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rdpr %pstate, %g5
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bne,pn %xcc, tsb_do_itlb_fault
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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tsb_do_dtlb_fault:
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rdpr %tl, %g4
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cmp %g4, 1
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g5
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be,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_DTLB, %g4
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ba,pt %xcc, winfix_trampoline
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nop
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tsb_do_itlb_fault:
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rdpr %tpc, %g5
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ba,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_ITLB, %g4
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.globl sparc64_realfault_common
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sparc64_realfault_common:
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stb %g4, [%g6 + TI_FAULT_CODE] ! Save fault code
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stx %g5, [%g6 + TI_FAULT_ADDR] ! Save fault address
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ba,pt %xcc, etrap ! Save trap state
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1: rd %pc, %g7 ! ...
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call do_sparc64_fault ! Call fault handler
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add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
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ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
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nop ! Delay slot (fill me)
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.globl winfix_trampoline
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winfix_trampoline:
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rdpr %tpc, %g3 ! Prepare winfixup TNPC
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or %g3, 0x7c, %g3 ! Compute branch offset
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wrpr %g3, %tnpc ! Write it into TNPC
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done ! Trap return
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/* Reload MMU related context switch state at
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* schedule() time.
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*
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* %o0: page table physical address
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* %o1: TSB address
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*/
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.globl tsb_context_switch
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tsb_context_switch:
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wrpr %g0, PSTATE_MG | PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV, %pstate
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/* Set page table base alternate global. */
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mov %o0, %g7
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/* XXX can this happen? */
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brz,pn %o1, 9f
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nop
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/* Lock TSB into D-TLB. */
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sethi %hi(PAGE_SIZE), %o3
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and %o3, %o1, %o3
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sethi %hi(TSBMAP_BASE), %o2
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add %o2, %o3, %o2
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/* XXX handle PAGE_SIZE != 8K correctly... */
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mov TSB_REG, %g1
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stxa %o2, [%g1] ASI_DMMU
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membar #Sync
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stxa %o2, [%g1] ASI_IMMU
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membar #Sync
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#define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZBITS)^0xfffff80000000000)
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#define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W | _PAGE_L)
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sethi %uhi(KERN_HIGHBITS), %g2
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or %g2, %ulo(KERN_HIGHBITS), %g2
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sllx %g2, 32, %g2
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or %g2, KERN_LOWBITS, %g2
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#undef KERN_HIGHBITS
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#undef KERN_LOWBITS
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xor %o1, %g2, %o1
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/* We use entry 61 for this locked entry. This is the spitfire
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* TLB entry number, and luckily cheetah masks the value with
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* 15 ending us up with entry 13 which is what we want in that
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* case too.
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*
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* XXX Interactions with prom_world()...
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*/
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mov TLB_TAG_ACCESS, %g1
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stxa %o2, [%g1] ASI_DMMU
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membar #Sync
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mov (61 << 3), %g1
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stxa %o1, [%g1] ASI_DTLB_DATA_ACCESS
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membar #Sync
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9:
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wrpr %g0, PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE, %pstate
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retl
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mov %o2, %o0
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