2005-04-17 00:20:36 +02:00
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/*
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* Standard PCI Hot Plug Driver
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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2005-08-17 00:16:10 +02:00
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* Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
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2005-04-17 00:20:36 +02:00
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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2005-11-14 01:06:40 +01:00
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#include <linux/interrupt.h>
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2005-04-17 00:20:36 +02:00
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#include "shpchp.h"
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/* Slot Available Register I field definition */
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#define SLOT_33MHZ 0x0000001f
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#define SLOT_66MHZ_PCIX 0x00001f00
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#define SLOT_100MHZ_PCIX 0x001f0000
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#define SLOT_133MHZ_PCIX 0x1f000000
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/* Slot Available Register II field definition */
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#define SLOT_66MHZ 0x0000001f
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#define SLOT_66MHZ_PCIX_266 0x00000f00
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#define SLOT_100MHZ_PCIX_266 0x0000f000
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#define SLOT_133MHZ_PCIX_266 0x000f0000
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#define SLOT_66MHZ_PCIX_533 0x00f00000
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#define SLOT_100MHZ_PCIX_533 0x0f000000
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#define SLOT_133MHZ_PCIX_533 0xf0000000
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/* Slot Configuration */
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#define SLOT_NUM 0x0000001F
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#define FIRST_DEV_NUM 0x00001F00
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#define PSN 0x07FF0000
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#define UPDOWN 0x20000000
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#define MRLSENSOR 0x40000000
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#define ATTN_BUTTON 0x80000000
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2006-05-12 04:10:56 +02:00
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/*
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* Interrupt Locator Register definitions
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*/
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#define CMD_INTR_PENDING (1 << 0)
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#define SLOT_INTR_PENDING(i) (1 << (i + 1))
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2006-05-02 04:12:37 +02:00
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/*
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* Controller SERR-INT Register
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*/
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#define GLOBAL_INTR_MASK (1 << 0)
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#define GLOBAL_SERR_MASK (1 << 1)
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#define COMMAND_INTR_MASK (1 << 2)
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#define ARBITER_SERR_MASK (1 << 3)
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#define COMMAND_DETECTED (1 << 16)
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#define ARBITER_DETECTED (1 << 17)
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#define SERR_INTR_RSVDZ_MASK 0xfffc0000
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2006-05-02 04:09:42 +02:00
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/*
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* Logical Slot Register definitions
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*/
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#define SLOT_REG(i) (SLOT1 + (4 * i))
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2006-05-02 04:10:37 +02:00
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#define SLOT_STATE_SHIFT (0)
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#define SLOT_STATE_MASK (3 << 0)
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#define SLOT_STATE_PWRONLY (1)
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#define SLOT_STATE_ENABLED (2)
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#define SLOT_STATE_DISABLED (3)
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#define PWR_LED_STATE_SHIFT (2)
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#define PWR_LED_STATE_MASK (3 << 2)
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#define ATN_LED_STATE_SHIFT (4)
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#define ATN_LED_STATE_MASK (3 << 4)
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#define ATN_LED_STATE_ON (1)
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#define ATN_LED_STATE_BLINK (2)
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#define ATN_LED_STATE_OFF (3)
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#define POWER_FAULT (1 << 6)
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#define ATN_BUTTON (1 << 7)
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#define MRL_SENSOR (1 << 8)
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#define MHZ66_CAP (1 << 9)
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#define PRSNT_SHIFT (10)
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#define PRSNT_MASK (3 << 10)
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#define PCIX_CAP_SHIFT (12)
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#define PCIX_CAP_MASK_PI1 (3 << 12)
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#define PCIX_CAP_MASK_PI2 (7 << 12)
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#define PRSNT_CHANGE_DETECTED (1 << 16)
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#define ISO_PFAULT_DETECTED (1 << 17)
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#define BUTTON_PRESS_DETECTED (1 << 18)
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#define MRL_CHANGE_DETECTED (1 << 19)
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#define CON_PFAULT_DETECTED (1 << 20)
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#define PRSNT_CHANGE_INTR_MASK (1 << 24)
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#define ISO_PFAULT_INTR_MASK (1 << 25)
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#define BUTTON_PRESS_INTR_MASK (1 << 26)
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#define MRL_CHANGE_INTR_MASK (1 << 27)
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#define CON_PFAULT_INTR_MASK (1 << 28)
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#define MRL_CHANGE_SERR_MASK (1 << 29)
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#define CON_PFAULT_SERR_MASK (1 << 30)
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2010-05-26 12:46:39 +02:00
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#define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21))
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2005-04-17 00:20:36 +02:00
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2006-05-12 04:11:48 +02:00
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/*
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* SHPC Command Code definitnions
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*
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* Slot Operation 00h - 3Fh
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* Set Bus Segment Speed/Mode A 40h - 47h
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* Power-Only All Slots 48h
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* Enable All Slots 49h
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* Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
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* Reserved Command Codes 60h - BFh
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* Vendor Specific Commands C0h - FFh
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*/
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#define SET_SLOT_PWR 0x01 /* Slot Operation */
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#define SET_SLOT_ENABLE 0x02
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#define SET_SLOT_DISABLE 0x03
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#define SET_PWR_ON 0x04
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#define SET_PWR_BLINK 0x08
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#define SET_PWR_OFF 0x0c
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#define SET_ATTN_ON 0x10
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#define SET_ATTN_BLINK 0x20
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#define SET_ATTN_OFF 0x30
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#define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
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2005-04-17 00:20:36 +02:00
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#define SETA_PCI_66MHZ 0x41
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#define SETA_PCIX_66MHZ 0x42
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#define SETA_PCIX_100MHZ 0x43
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#define SETA_PCIX_133MHZ 0x44
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2006-05-12 04:11:48 +02:00
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#define SETA_RESERVED1 0x45
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#define SETA_RESERVED2 0x46
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#define SETA_RESERVED3 0x47
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#define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
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#define SET_ENABLE_ALL 0x49 /* Enable All Slots */
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#define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
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2005-04-17 00:20:36 +02:00
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#define SETB_PCI_66MHZ 0x51
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#define SETB_PCIX_66MHZ_PM 0x52
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#define SETB_PCIX_100MHZ_PM 0x53
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#define SETB_PCIX_133MHZ_PM 0x54
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#define SETB_PCIX_66MHZ_EM 0x55
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#define SETB_PCIX_100MHZ_EM 0x56
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#define SETB_PCIX_133MHZ_EM 0x57
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#define SETB_PCIX_66MHZ_266 0x58
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#define SETB_PCIX_100MHZ_266 0x59
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#define SETB_PCIX_133MHZ_266 0x5a
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#define SETB_PCIX_66MHZ_533 0x5b
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#define SETB_PCIX_100MHZ_533 0x5c
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#define SETB_PCIX_133MHZ_533 0x5d
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2006-05-12 04:11:48 +02:00
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#define SETB_RESERVED1 0x5e
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#define SETB_RESERVED2 0x5f
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2005-04-17 00:20:36 +02:00
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2006-05-12 04:11:48 +02:00
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/*
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* SHPC controller command error code
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*/
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2005-04-17 00:20:36 +02:00
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#define SWITCH_OPEN 0x1
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#define INVALID_CMD 0x2
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#define INVALID_SPEED_MODE 0x4
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2006-05-12 04:11:48 +02:00
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/*
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* For accessing SHPC Working Register Set via PCI Configuration Space
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*/
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2005-04-17 00:20:36 +02:00
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#define DWORD_SELECT 0x2
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#define DWORD_DATA 0x4
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/* Field Offset in Logical Slot Register - byte boundary */
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#define SLOT_EVENT_LATCH 0x2
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#define SLOT_SERR_INT_MASK 0x3
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2006-05-03 16:42:04 +02:00
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static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 15:55:46 +02:00
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static irqreturn_t shpc_isr(int irq, void *dev_id);
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2006-12-17 00:25:34 +01:00
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static void start_int_poll_timer(struct controller *ctrl, int sec);
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2006-01-26 01:59:24 +01:00
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static int hpc_check_cmd_status(struct controller *ctrl);
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2005-04-17 00:20:36 +02:00
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2006-05-02 04:08:42 +02:00
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static inline u8 shpc_readb(struct controller *ctrl, int reg)
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{
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2006-12-17 00:25:34 +01:00
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return readb(ctrl->creg + reg);
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2006-05-02 04:08:42 +02:00
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}
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static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
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{
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2006-12-17 00:25:34 +01:00
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writeb(val, ctrl->creg + reg);
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2006-05-02 04:08:42 +02:00
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}
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static inline u16 shpc_readw(struct controller *ctrl, int reg)
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{
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2006-12-17 00:25:34 +01:00
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return readw(ctrl->creg + reg);
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2006-05-02 04:08:42 +02:00
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}
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static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
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{
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2006-12-17 00:25:34 +01:00
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writew(val, ctrl->creg + reg);
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2006-05-02 04:08:42 +02:00
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}
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static inline u32 shpc_readl(struct controller *ctrl, int reg)
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{
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2006-12-17 00:25:34 +01:00
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return readl(ctrl->creg + reg);
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2006-05-02 04:08:42 +02:00
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}
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static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
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{
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2006-12-17 00:25:34 +01:00
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writel(val, ctrl->creg + reg);
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2006-05-02 04:08:42 +02:00
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}
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static inline int shpc_indirect_read(struct controller *ctrl, int index,
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u32 *value)
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{
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int rc;
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u32 cap_offset = ctrl->cap_offset;
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struct pci_dev *pdev = ctrl->pci_dev;
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rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
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if (rc)
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return rc;
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return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
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}
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2006-05-12 04:13:02 +02:00
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/*
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* This is the interrupt polling timeout function.
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*/
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2006-12-17 00:25:34 +01:00
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static void int_poll_timeout(unsigned long data)
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2005-04-17 00:20:36 +02:00
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{
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2006-12-17 00:25:34 +01:00
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struct controller *ctrl = (struct controller *)data;
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2005-04-17 00:20:36 +02:00
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2006-05-12 04:13:02 +02:00
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/* Poll for interrupt events. regs == NULL => polling */
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2006-12-17 00:25:34 +01:00
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shpc_isr(0, ctrl);
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2005-04-17 00:20:36 +02:00
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2006-12-17 00:25:34 +01:00
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init_timer(&ctrl->poll_timer);
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2005-04-17 00:20:36 +02:00
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if (!shpchp_poll_time)
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2006-05-12 04:13:02 +02:00
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shpchp_poll_time = 2; /* default polling interval is 2 sec */
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2006-12-17 00:25:34 +01:00
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start_int_poll_timer(ctrl, shpchp_poll_time);
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2005-04-17 00:20:36 +02:00
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}
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2006-05-12 04:13:02 +02:00
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/*
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* This function starts the interrupt polling timer.
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*/
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2006-12-17 00:25:34 +01:00
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static void start_int_poll_timer(struct controller *ctrl, int sec)
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2005-04-17 00:20:36 +02:00
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{
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2006-05-12 04:13:02 +02:00
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/* Clamp to sane value */
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if ((sec <= 0) || (sec > 60))
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sec = 2;
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2006-12-17 00:25:34 +01:00
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ctrl->poll_timer.function = &int_poll_timeout;
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ctrl->poll_timer.data = (unsigned long)ctrl;
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ctrl->poll_timer.expires = jiffies + sec * HZ;
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add_timer(&ctrl->poll_timer);
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2005-04-17 00:20:36 +02:00
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}
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2006-09-29 00:51:21 +02:00
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static inline int is_ctrl_busy(struct controller *ctrl)
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{
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u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
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return cmd_status & 0x1;
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}
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2006-09-22 21:52:37 +02:00
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/*
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* Returns 1 if SHPC finishes executing a command within 1 sec,
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* otherwise returns 0.
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*/
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static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
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{
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int i;
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|
|
2006-09-29 00:51:21 +02:00
|
|
|
if (!is_ctrl_busy(ctrl))
|
2006-09-22 21:52:37 +02:00
|
|
|
return 1;
|
|
|
|
|
|
|
|
/* Check every 0.1 sec for a total of 1 sec */
|
|
|
|
for (i = 0; i < 10; i++) {
|
|
|
|
msleep(100);
|
2006-09-29 00:51:21 +02:00
|
|
|
if (!is_ctrl_busy(ctrl))
|
2006-09-22 21:52:37 +02:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-11-25 04:28:53 +01:00
|
|
|
static inline int shpc_wait_cmd(struct controller *ctrl)
|
|
|
|
{
|
|
|
|
int retval = 0;
|
2006-09-22 21:52:37 +02:00
|
|
|
unsigned long timeout = msecs_to_jiffies(1000);
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (shpchp_poll_mode)
|
|
|
|
rc = shpc_poll_ctrl_busy(ctrl);
|
|
|
|
else
|
|
|
|
rc = wait_event_interruptible_timeout(ctrl->queue,
|
2006-09-29 00:51:36 +02:00
|
|
|
!is_ctrl_busy(ctrl), timeout);
|
2006-09-29 00:51:21 +02:00
|
|
|
if (!rc && is_ctrl_busy(ctrl)) {
|
2005-11-25 04:28:53 +01:00
|
|
|
retval = -EIO;
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_err(ctrl, "Command not completed in 1000 msec\n");
|
2005-11-25 04:28:53 +01:00
|
|
|
} else if (rc < 0) {
|
|
|
|
retval = -EINTR;
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_info(ctrl, "Command was interrupted by a signal\n");
|
2005-11-25 04:28:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
|
|
|
|
{
|
2006-05-02 04:08:42 +02:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2005-04-17 00:20:36 +02:00
|
|
|
u16 cmd_status;
|
|
|
|
int retval = 0;
|
|
|
|
u16 temp_word;
|
|
|
|
|
2006-01-26 01:59:24 +01:00
|
|
|
mutex_lock(&slot->ctrl->cmd_lock);
|
|
|
|
|
2006-09-22 21:52:37 +02:00
|
|
|
if (!shpc_poll_ctrl_busy(ctrl)) {
|
2005-04-17 00:20:36 +02:00
|
|
|
/* After 1 sec and and the controller is still busy */
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
|
2006-01-26 01:59:24 +01:00
|
|
|
retval = -EBUSY;
|
|
|
|
goto out;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
++t_slot;
|
|
|
|
temp_word = (t_slot << 8) | (cmd & 0xFF);
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
|
2007-01-09 22:03:10 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/* To make sure the Controller Busy bit is 0 before we send out the
|
2007-01-09 22:03:10 +01:00
|
|
|
* command.
|
2005-04-17 00:20:36 +02:00
|
|
|
*/
|
2006-05-02 04:08:42 +02:00
|
|
|
shpc_writew(ctrl, CMD, temp_word);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-11-25 04:28:53 +01:00
|
|
|
/*
|
|
|
|
* Wait for command completion.
|
|
|
|
*/
|
|
|
|
retval = shpc_wait_cmd(slot->ctrl);
|
2006-01-26 01:59:24 +01:00
|
|
|
if (retval)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
cmd_status = hpc_check_cmd_status(slot->ctrl);
|
|
|
|
if (cmd_status) {
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl,
|
|
|
|
"Failed to issued command 0x%x (error code = %d)\n",
|
|
|
|
cmd, cmd_status);
|
2006-01-26 01:59:24 +01:00
|
|
|
retval = -EIO;
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
mutex_unlock(&slot->ctrl->cmd_lock);
|
2005-04-17 00:20:36 +02:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_check_cmd_status(struct controller *ctrl)
|
|
|
|
{
|
|
|
|
int retval = 0;
|
2007-01-09 22:03:01 +01:00
|
|
|
u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
|
2007-01-09 22:03:10 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
switch (cmd_status >> 1) {
|
|
|
|
case 0:
|
|
|
|
retval = 0;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
retval = SWITCH_OPEN;
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl, "Switch opened!\n");
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
retval = INVALID_CMD;
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl, "Invalid HPC command!\n");
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
retval = INVALID_SPEED_MODE;
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl, "Invalid bus speed/mode!\n");
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
retval = cmd_status;
|
|
|
|
}
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int hpc_get_attention_status(struct slot *slot, u8 *status)
|
|
|
|
{
|
2006-05-02 04:08:42 +02:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2007-01-09 22:03:01 +01:00
|
|
|
u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
|
|
|
|
u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-02 04:10:37 +02:00
|
|
|
switch (state) {
|
|
|
|
case ATN_LED_STATE_ON:
|
2005-04-17 00:20:36 +02:00
|
|
|
*status = 1; /* On */
|
|
|
|
break;
|
2006-05-02 04:10:37 +02:00
|
|
|
case ATN_LED_STATE_BLINK:
|
2005-04-17 00:20:36 +02:00
|
|
|
*status = 2; /* Blink */
|
|
|
|
break;
|
2006-05-02 04:10:37 +02:00
|
|
|
case ATN_LED_STATE_OFF:
|
2005-04-17 00:20:36 +02:00
|
|
|
*status = 0; /* Off */
|
|
|
|
break;
|
|
|
|
default:
|
2006-05-02 04:10:37 +02:00
|
|
|
*status = 0xFF; /* Reserved */
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_get_power_status(struct slot * slot, u8 *status)
|
|
|
|
{
|
2006-05-02 04:08:42 +02:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2007-01-09 22:03:01 +01:00
|
|
|
u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
|
|
|
|
u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-02 04:10:37 +02:00
|
|
|
switch (state) {
|
|
|
|
case SLOT_STATE_PWRONLY:
|
2005-04-17 00:20:36 +02:00
|
|
|
*status = 2; /* Powered only */
|
|
|
|
break;
|
2006-05-02 04:10:37 +02:00
|
|
|
case SLOT_STATE_ENABLED:
|
2005-04-17 00:20:36 +02:00
|
|
|
*status = 1; /* Enabled */
|
|
|
|
break;
|
2006-05-02 04:10:37 +02:00
|
|
|
case SLOT_STATE_DISABLED:
|
2005-04-17 00:20:36 +02:00
|
|
|
*status = 0; /* Disabled */
|
|
|
|
break;
|
|
|
|
default:
|
2006-05-02 04:10:37 +02:00
|
|
|
*status = 0xFF; /* Reserved */
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2006-05-02 04:10:37 +02:00
|
|
|
return 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int hpc_get_latch_status(struct slot *slot, u8 *status)
|
|
|
|
{
|
2006-05-02 04:08:42 +02:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2007-01-09 22:03:01 +01:00
|
|
|
u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-02 04:10:37 +02:00
|
|
|
*status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_get_adapter_status(struct slot *slot, u8 *status)
|
|
|
|
{
|
2006-05-02 04:08:42 +02:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2007-01-09 22:03:01 +01:00
|
|
|
u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
|
|
|
|
u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-02 04:10:37 +02:00
|
|
|
*status = (state != 0x3) ? 1 : 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
|
|
|
|
{
|
2006-05-02 04:08:42 +02:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-02 04:08:42 +02:00
|
|
|
*prog_int = shpc_readb(ctrl, PROG_INTERFACE);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
|
|
|
|
{
|
|
|
|
int retval = 0;
|
2006-05-02 04:08:42 +02:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2006-05-02 04:09:42 +02:00
|
|
|
u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
|
2006-05-02 04:10:37 +02:00
|
|
|
u8 m66_cap = !!(slot_reg & MHZ66_CAP);
|
2006-05-02 04:11:54 +02:00
|
|
|
u8 pi, pcix_cap;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-02 04:11:54 +02:00
|
|
|
if ((retval = hpc_get_prog_int(slot, &pi)))
|
|
|
|
return retval;
|
|
|
|
|
|
|
|
switch (pi) {
|
|
|
|
case 1:
|
|
|
|
pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
|
|
|
|
__func__, slot_reg, pcix_cap, m66_cap);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-03-01 06:55:11 +01:00
|
|
|
switch (pcix_cap) {
|
|
|
|
case 0x0:
|
|
|
|
*value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
|
|
|
|
break;
|
|
|
|
case 0x1:
|
|
|
|
*value = PCI_SPEED_66MHz_PCIX;
|
|
|
|
break;
|
|
|
|
case 0x3:
|
|
|
|
*value = PCI_SPEED_133MHz_PCIX;
|
|
|
|
break;
|
|
|
|
case 0x4:
|
|
|
|
*value = PCI_SPEED_133MHz_PCIX_266;
|
|
|
|
break;
|
|
|
|
case 0x5:
|
|
|
|
*value = PCI_SPEED_133MHz_PCIX_533;
|
|
|
|
break;
|
|
|
|
case 0x2:
|
|
|
|
default:
|
|
|
|
*value = PCI_SPEED_UNKNOWN;
|
|
|
|
retval = -ENODEV;
|
|
|
|
break;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
|
2005-04-17 00:20:36 +02:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
|
|
|
|
{
|
|
|
|
int retval = 0;
|
2007-01-09 22:03:01 +01:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
|
|
|
u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
|
|
|
|
u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
if (pi == 2) {
|
2005-11-24 03:35:05 +01:00
|
|
|
*mode = (sec_bus_status & 0x0100) >> 8;
|
2005-04-17 00:20:36 +02:00
|
|
|
} else {
|
|
|
|
retval = -1;
|
|
|
|
}
|
|
|
|
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
|
2005-04-17 00:20:36 +02:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_query_power_fault(struct slot * slot)
|
|
|
|
{
|
2006-05-02 04:08:42 +02:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2007-01-09 22:03:01 +01:00
|
|
|
u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* Note: Logic 0 => fault */
|
2006-05-02 04:10:37 +02:00
|
|
|
return !(slot_reg & POWER_FAULT);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_set_attention_status(struct slot *slot, u8 value)
|
|
|
|
{
|
|
|
|
u8 slot_cmd = 0;
|
|
|
|
|
|
|
|
switch (value) {
|
2007-01-09 22:03:10 +01:00
|
|
|
case 0 :
|
2006-05-12 04:11:48 +02:00
|
|
|
slot_cmd = SET_ATTN_OFF; /* OFF */
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
case 1:
|
2006-05-12 04:11:48 +02:00
|
|
|
slot_cmd = SET_ATTN_ON; /* ON */
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2006-05-12 04:11:48 +02:00
|
|
|
slot_cmd = SET_ATTN_BLINK; /* BLINK */
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2006-05-12 04:05:59 +02:00
|
|
|
return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void hpc_set_green_led_on(struct slot *slot)
|
|
|
|
{
|
2006-05-12 04:11:48 +02:00
|
|
|
shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void hpc_set_green_led_off(struct slot *slot)
|
|
|
|
{
|
2006-05-12 04:11:48 +02:00
|
|
|
shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void hpc_set_green_led_blink(struct slot *slot)
|
|
|
|
{
|
2006-05-12 04:11:48 +02:00
|
|
|
shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void hpc_release_ctlr(struct controller *ctrl)
|
|
|
|
{
|
2006-02-22 00:45:45 +01:00
|
|
|
int i;
|
2006-05-03 16:34:17 +02:00
|
|
|
u32 slot_reg, serr_int;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-02-22 00:45:45 +01:00
|
|
|
/*
|
2006-05-02 04:11:54 +02:00
|
|
|
* Mask event interrupts and SERRs of all slots
|
2006-02-22 00:45:45 +01:00
|
|
|
*/
|
2006-05-02 04:11:54 +02:00
|
|
|
for (i = 0; i < ctrl->num_slots; i++) {
|
|
|
|
slot_reg = shpc_readl(ctrl, SLOT_REG(i));
|
|
|
|
slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
|
|
|
|
BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
|
|
|
|
CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
|
|
|
|
CON_PFAULT_SERR_MASK);
|
|
|
|
slot_reg &= ~SLOT_REG_RSVDZ_MASK;
|
|
|
|
shpc_writel(ctrl, SLOT_REG(i), slot_reg);
|
|
|
|
}
|
2006-02-22 00:45:45 +01:00
|
|
|
|
|
|
|
cleanup_slots(ctrl);
|
|
|
|
|
2006-05-03 16:34:17 +02:00
|
|
|
/*
|
2007-12-17 20:40:11 +01:00
|
|
|
* Mask SERR and System Interrupt generation
|
2006-05-03 16:34:17 +02:00
|
|
|
*/
|
|
|
|
serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
|
|
|
serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
|
|
|
|
COMMAND_INTR_MASK | ARBITER_SERR_MASK);
|
|
|
|
serr_int &= ~SERR_INTR_RSVDZ_MASK;
|
|
|
|
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
|
|
|
|
|
2006-12-17 00:25:34 +01:00
|
|
|
if (shpchp_poll_mode)
|
|
|
|
del_timer(&ctrl->poll_timer);
|
|
|
|
else {
|
|
|
|
free_irq(ctrl->pci_dev->irq, ctrl);
|
|
|
|
pci_disable_msi(ctrl->pci_dev);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2006-12-17 00:25:34 +01:00
|
|
|
iounmap(ctrl->creg);
|
|
|
|
release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-03 16:42:04 +02:00
|
|
|
/*
|
|
|
|
* If this is the last controller to be released, destroy the
|
|
|
|
* shpchpd work queue
|
|
|
|
*/
|
|
|
|
if (atomic_dec_and_test(&shpchp_num_controllers))
|
|
|
|
destroy_workqueue(shpchp_wq);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_power_on_slot(struct slot * slot)
|
|
|
|
{
|
2006-05-12 04:05:59 +02:00
|
|
|
int retval;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-12 04:11:48 +02:00
|
|
|
retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
|
2007-01-09 22:03:01 +01:00
|
|
|
if (retval)
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-01-09 22:03:01 +01:00
|
|
|
return retval;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_slot_enable(struct slot * slot)
|
|
|
|
{
|
2006-05-12 04:05:59 +02:00
|
|
|
int retval;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-12 04:11:48 +02:00
|
|
|
/* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
|
|
|
|
retval = shpc_write_cmd(slot, slot->hp_slot,
|
|
|
|
SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
|
2007-01-09 22:03:01 +01:00
|
|
|
if (retval)
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-01-09 22:03:01 +01:00
|
|
|
return retval;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int hpc_slot_disable(struct slot * slot)
|
|
|
|
{
|
2006-05-12 04:05:59 +02:00
|
|
|
int retval;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-12 04:11:48 +02:00
|
|
|
/* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
|
|
|
|
retval = shpc_write_cmd(slot, slot->hp_slot,
|
|
|
|
SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
|
2007-01-09 22:03:01 +01:00
|
|
|
if (retval)
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-01-09 22:03:01 +01:00
|
|
|
return retval;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2009-12-13 14:11:32 +01:00
|
|
|
static int shpc_get_cur_bus_speed(struct controller *ctrl)
|
|
|
|
{
|
|
|
|
int retval = 0;
|
|
|
|
struct pci_bus *bus = ctrl->pci_dev->subordinate;
|
|
|
|
enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
|
|
|
|
u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
|
|
|
|
u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
|
|
|
|
u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
|
|
|
|
|
|
|
|
if ((pi == 1) && (speed_mode > 4)) {
|
|
|
|
retval = -ENODEV;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (speed_mode) {
|
|
|
|
case 0x0:
|
|
|
|
bus_speed = PCI_SPEED_33MHz;
|
|
|
|
break;
|
|
|
|
case 0x1:
|
|
|
|
bus_speed = PCI_SPEED_66MHz;
|
|
|
|
break;
|
|
|
|
case 0x2:
|
|
|
|
bus_speed = PCI_SPEED_66MHz_PCIX;
|
|
|
|
break;
|
|
|
|
case 0x3:
|
|
|
|
bus_speed = PCI_SPEED_100MHz_PCIX;
|
|
|
|
break;
|
|
|
|
case 0x4:
|
|
|
|
bus_speed = PCI_SPEED_133MHz_PCIX;
|
|
|
|
break;
|
|
|
|
case 0x5:
|
|
|
|
bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
|
|
|
|
break;
|
|
|
|
case 0x6:
|
|
|
|
bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
|
|
|
|
break;
|
|
|
|
case 0x7:
|
|
|
|
bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
|
|
|
|
break;
|
|
|
|
case 0x8:
|
|
|
|
bus_speed = PCI_SPEED_66MHz_PCIX_266;
|
|
|
|
break;
|
|
|
|
case 0x9:
|
|
|
|
bus_speed = PCI_SPEED_100MHz_PCIX_266;
|
|
|
|
break;
|
|
|
|
case 0xa:
|
|
|
|
bus_speed = PCI_SPEED_133MHz_PCIX_266;
|
|
|
|
break;
|
|
|
|
case 0xb:
|
|
|
|
bus_speed = PCI_SPEED_66MHz_PCIX_533;
|
|
|
|
break;
|
|
|
|
case 0xc:
|
|
|
|
bus_speed = PCI_SPEED_100MHz_PCIX_533;
|
|
|
|
break;
|
|
|
|
case 0xd:
|
|
|
|
bus_speed = PCI_SPEED_133MHz_PCIX_533;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
retval = -ENODEV;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
bus->cur_bus_speed = bus_speed;
|
|
|
|
dbg("Current bus speed = %d\n", bus_speed);
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
|
|
|
|
{
|
2006-03-01 06:55:11 +01:00
|
|
|
int retval;
|
2006-05-02 04:08:42 +02:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2006-03-01 06:55:11 +01:00
|
|
|
u8 pi, cmd;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-02 04:08:42 +02:00
|
|
|
pi = shpc_readb(ctrl, PROG_INTERFACE);
|
2006-03-01 06:55:11 +01:00
|
|
|
if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
|
|
|
|
return -EINVAL;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-03-01 06:55:11 +01:00
|
|
|
switch (value) {
|
|
|
|
case PCI_SPEED_33MHz:
|
|
|
|
cmd = SETA_PCI_33MHZ;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_66MHz:
|
|
|
|
cmd = SETA_PCI_66MHZ;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_66MHz_PCIX:
|
|
|
|
cmd = SETA_PCIX_66MHZ;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_100MHz_PCIX:
|
|
|
|
cmd = SETA_PCIX_100MHZ;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_133MHz_PCIX:
|
|
|
|
cmd = SETA_PCIX_133MHZ;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_66MHz_PCIX_ECC:
|
|
|
|
cmd = SETB_PCIX_66MHZ_EM;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_100MHz_PCIX_ECC:
|
|
|
|
cmd = SETB_PCIX_100MHZ_EM;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_133MHz_PCIX_ECC:
|
|
|
|
cmd = SETB_PCIX_133MHZ_EM;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_66MHz_PCIX_266:
|
|
|
|
cmd = SETB_PCIX_66MHZ_266;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_100MHz_PCIX_266:
|
|
|
|
cmd = SETB_PCIX_100MHZ_266;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_133MHz_PCIX_266:
|
|
|
|
cmd = SETB_PCIX_133MHZ_266;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_66MHz_PCIX_533:
|
|
|
|
cmd = SETB_PCIX_66MHZ_533;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_100MHz_PCIX_533:
|
|
|
|
cmd = SETB_PCIX_100MHZ_533;
|
|
|
|
break;
|
|
|
|
case PCI_SPEED_133MHz_PCIX_533:
|
|
|
|
cmd = SETB_PCIX_133MHZ_533;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2006-03-01 06:55:11 +01:00
|
|
|
|
|
|
|
retval = shpc_write_cmd(slot, 0, cmd);
|
|
|
|
if (retval)
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
|
2009-12-13 14:11:32 +01:00
|
|
|
else
|
|
|
|
shpc_get_cur_bus_speed(ctrl);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 15:55:46 +02:00
|
|
|
static irqreturn_t shpc_isr(int irq, void *dev_id)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2006-05-12 04:10:56 +02:00
|
|
|
struct controller *ctrl = (struct controller *)dev_id;
|
|
|
|
u32 serr_int, slot_reg, intr_loc, intr_loc2;
|
2005-04-17 00:20:36 +02:00
|
|
|
int hp_slot;
|
|
|
|
|
|
|
|
/* Check to see if it was our interrupt */
|
2006-05-02 04:08:42 +02:00
|
|
|
intr_loc = shpc_readl(ctrl, INTR_LOC);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (!intr_loc)
|
|
|
|
return IRQ_NONE;
|
2006-05-12 04:10:56 +02:00
|
|
|
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
if(!shpchp_poll_mode) {
|
2006-05-12 04:10:56 +02:00
|
|
|
/*
|
|
|
|
* Mask Global Interrupt Mask - see implementation
|
|
|
|
* note on p. 139 of SHPC spec rev 1.0
|
|
|
|
*/
|
|
|
|
serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
|
|
|
serr_int |= GLOBAL_INTR_MASK;
|
|
|
|
serr_int &= ~SERR_INTR_RSVDZ_MASK;
|
|
|
|
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-05-02 04:08:42 +02:00
|
|
|
intr_loc2 = shpc_readl(ctrl, INTR_LOC);
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2006-05-12 04:10:56 +02:00
|
|
|
if (intr_loc & CMD_INTR_PENDING) {
|
2007-01-09 22:03:10 +01:00
|
|
|
/*
|
|
|
|
* Command Complete Interrupt Pending
|
2005-11-24 03:39:29 +01:00
|
|
|
* RO only - clear by writing 1 to the Command Completion
|
2005-04-17 00:20:36 +02:00
|
|
|
* Detect bit in Controller SERR-INT register
|
|
|
|
*/
|
2006-05-12 04:10:56 +02:00
|
|
|
serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
|
|
|
serr_int &= ~SERR_INTR_RSVDZ_MASK;
|
|
|
|
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
wake_up_interruptible(&ctrl->queue);
|
|
|
|
}
|
|
|
|
|
2006-05-12 04:10:56 +02:00
|
|
|
if (!(intr_loc & ~CMD_INTR_PENDING))
|
2006-01-26 02:05:57 +01:00
|
|
|
goto out;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-01-09 22:03:10 +01:00
|
|
|
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
|
2006-05-12 04:10:56 +02:00
|
|
|
/* To find out which slot has interrupt pending */
|
|
|
|
if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
|
|
|
|
hp_slot, slot_reg);
|
2006-05-12 04:10:56 +02:00
|
|
|
|
|
|
|
if (slot_reg & MRL_CHANGE_DETECTED)
|
2006-12-17 00:25:34 +01:00
|
|
|
shpchp_handle_switch_change(hp_slot, ctrl);
|
2006-05-12 04:10:56 +02:00
|
|
|
|
|
|
|
if (slot_reg & BUTTON_PRESS_DETECTED)
|
2006-12-17 00:25:34 +01:00
|
|
|
shpchp_handle_attention_button(hp_slot, ctrl);
|
2006-05-12 04:10:56 +02:00
|
|
|
|
|
|
|
if (slot_reg & PRSNT_CHANGE_DETECTED)
|
2006-12-17 00:25:34 +01:00
|
|
|
shpchp_handle_presence_change(hp_slot, ctrl);
|
2006-05-12 04:10:56 +02:00
|
|
|
|
|
|
|
if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
|
2006-12-17 00:25:34 +01:00
|
|
|
shpchp_handle_power_fault(hp_slot, ctrl);
|
2006-05-12 04:10:56 +02:00
|
|
|
|
|
|
|
/* Clear all slot events */
|
|
|
|
slot_reg &= ~SLOT_REG_RSVDZ_MASK;
|
|
|
|
shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2006-01-26 02:05:57 +01:00
|
|
|
out:
|
2005-04-17 00:20:36 +02:00
|
|
|
if (!shpchp_poll_mode) {
|
|
|
|
/* Unmask Global Interrupt Mask */
|
2006-05-12 04:10:56 +02:00
|
|
|
serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
|
|
|
serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
|
|
|
|
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2007-01-09 22:03:10 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2009-12-13 14:11:32 +01:00
|
|
|
static int shpc_get_max_bus_speed(struct controller *ctrl)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2006-03-01 06:55:11 +01:00
|
|
|
int retval = 0;
|
2009-12-13 14:11:32 +01:00
|
|
|
struct pci_bus *bus = ctrl->pci_dev->subordinate;
|
2005-04-17 00:20:36 +02:00
|
|
|
enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
|
2006-05-02 04:08:42 +02:00
|
|
|
u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
|
|
|
|
u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
|
|
|
|
u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
if (pi == 2) {
|
2005-11-24 05:44:01 +01:00
|
|
|
if (slot_avail2 & SLOT_133MHZ_PCIX_533)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_133MHz_PCIX_533;
|
2005-11-24 05:44:01 +01:00
|
|
|
else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_100MHz_PCIX_533;
|
2005-11-24 05:44:01 +01:00
|
|
|
else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_66MHz_PCIX_533;
|
2005-11-24 05:44:01 +01:00
|
|
|
else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_133MHz_PCIX_266;
|
2005-11-24 05:44:01 +01:00
|
|
|
else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_100MHz_PCIX_266;
|
2005-11-24 05:44:01 +01:00
|
|
|
else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_66MHz_PCIX_266;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (bus_speed == PCI_SPEED_UNKNOWN) {
|
2005-11-24 05:44:01 +01:00
|
|
|
if (slot_avail1 & SLOT_133MHZ_PCIX)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_133MHz_PCIX;
|
2005-11-24 05:44:01 +01:00
|
|
|
else if (slot_avail1 & SLOT_100MHZ_PCIX)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_100MHz_PCIX;
|
2005-11-24 05:44:01 +01:00
|
|
|
else if (slot_avail1 & SLOT_66MHZ_PCIX)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_66MHz_PCIX;
|
2005-11-24 05:44:01 +01:00
|
|
|
else if (slot_avail2 & SLOT_66MHZ)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_66MHz;
|
2005-11-24 05:44:01 +01:00
|
|
|
else if (slot_avail1 & SLOT_33MHZ)
|
2006-03-01 06:55:11 +01:00
|
|
|
bus_speed = PCI_SPEED_33MHz;
|
|
|
|
else
|
|
|
|
retval = -ENODEV;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2009-12-13 14:11:32 +01:00
|
|
|
bus->max_bus_speed = bus_speed;
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
|
2007-01-09 22:03:01 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct hpc_ops shpchp_hpc_ops = {
|
|
|
|
.power_on_slot = hpc_power_on_slot,
|
|
|
|
.slot_enable = hpc_slot_enable,
|
|
|
|
.slot_disable = hpc_slot_disable,
|
2007-01-09 22:03:10 +01:00
|
|
|
.set_bus_speed_mode = hpc_set_bus_speed_mode,
|
2005-04-17 00:20:36 +02:00
|
|
|
.set_attention_status = hpc_set_attention_status,
|
|
|
|
.get_power_status = hpc_get_power_status,
|
|
|
|
.get_attention_status = hpc_get_attention_status,
|
|
|
|
.get_latch_status = hpc_get_latch_status,
|
|
|
|
.get_adapter_status = hpc_get_adapter_status,
|
|
|
|
|
|
|
|
.get_adapter_speed = hpc_get_adapter_speed,
|
|
|
|
.get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
|
|
|
|
.get_prog_int = hpc_get_prog_int,
|
|
|
|
|
|
|
|
.query_power_fault = hpc_query_power_fault,
|
|
|
|
.green_led_on = hpc_set_green_led_on,
|
|
|
|
.green_led_off = hpc_set_green_led_off,
|
|
|
|
.green_led_blink = hpc_set_green_led_blink,
|
2007-01-09 22:03:10 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
.release_ctlr = hpc_release_ctlr,
|
|
|
|
};
|
|
|
|
|
2006-12-17 00:25:34 +01:00
|
|
|
int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2006-10-05 08:37:32 +02:00
|
|
|
int rc = -1, num_slots = 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
u8 hp_slot;
|
2005-11-24 03:36:59 +01:00
|
|
|
u32 shpc_base_offset;
|
2006-05-02 04:08:42 +02:00
|
|
|
u32 tempdword, slot_reg, slot_config;
|
2005-04-17 00:20:36 +02:00
|
|
|
u8 i;
|
|
|
|
|
2005-11-24 03:36:59 +01:00
|
|
|
ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, "Hotplug Controller:\n");
|
2005-11-24 03:36:59 +01:00
|
|
|
|
2005-10-13 21:05:42 +02:00
|
|
|
if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
|
|
|
|
PCI_DEVICE_ID_AMD_GOLAM_7450)) {
|
2005-11-24 03:36:59 +01:00
|
|
|
/* amd shpc driver doesn't use Base Offset; assume 0 */
|
|
|
|
ctrl->mmio_base = pci_resource_start(pdev, 0);
|
|
|
|
ctrl->mmio_size = pci_resource_len(pdev, 0);
|
2005-04-17 00:20:36 +02:00
|
|
|
} else {
|
2005-11-24 03:36:59 +01:00
|
|
|
ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
|
|
|
|
if (!ctrl->cap_offset) {
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl, "Cannot find PCI capability\n");
|
2006-12-17 00:25:34 +01:00
|
|
|
goto abort;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
|
2005-11-24 03:36:59 +01:00
|
|
|
|
2006-05-02 04:08:42 +02:00
|
|
|
rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (rc) {
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl, "Cannot read base_offset\n");
|
2006-12-17 00:25:34 +01:00
|
|
|
goto abort;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2005-11-24 03:36:59 +01:00
|
|
|
|
2006-05-02 04:08:42 +02:00
|
|
|
rc = shpc_indirect_read(ctrl, 3, &tempdword);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (rc) {
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl, "Cannot read slot config\n");
|
2006-12-17 00:25:34 +01:00
|
|
|
goto abort;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2005-11-24 03:36:59 +01:00
|
|
|
num_slots = tempdword & SLOT_NUM;
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-11-24 03:36:59 +01:00
|
|
|
for (i = 0; i < 9 + num_slots; i++) {
|
2006-05-02 04:08:42 +02:00
|
|
|
rc = shpc_indirect_read(ctrl, i, &tempdword);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (rc) {
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl,
|
|
|
|
"Cannot read creg (index = %d)\n", i);
|
2006-12-17 00:25:34 +01:00
|
|
|
goto abort;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2005-11-24 03:36:59 +01:00
|
|
|
|
|
|
|
ctrl->mmio_base =
|
|
|
|
pci_resource_start(pdev, 0) + shpc_base_offset;
|
|
|
|
ctrl->mmio_size = 0x24 + 0x4 * num_slots;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
|
|
|
|
pdev->vendor, pdev->device, pdev->subsystem_vendor,
|
|
|
|
pdev->subsystem_device);
|
2007-01-09 22:03:10 +01:00
|
|
|
|
2006-10-05 08:37:32 +02:00
|
|
|
rc = pci_enable_device(pdev);
|
|
|
|
if (rc) {
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl, "pci_enable_device failed\n");
|
2006-12-17 00:25:34 +01:00
|
|
|
goto abort;
|
2006-10-05 08:37:32 +02:00
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-11-24 03:36:59 +01:00
|
|
|
if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl, "Cannot reserve MMIO region\n");
|
2006-10-05 08:37:32 +02:00
|
|
|
rc = -1;
|
2006-12-17 00:25:34 +01:00
|
|
|
goto abort;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2006-12-17 00:25:34 +01:00
|
|
|
ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
|
|
|
|
if (!ctrl->creg) {
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
|
|
|
|
ctrl->mmio_size, ctrl->mmio_base);
|
2005-11-24 03:36:59 +01:00
|
|
|
release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
|
2006-10-05 08:37:32 +02:00
|
|
|
rc = -1;
|
2006-12-17 00:25:34 +01:00
|
|
|
goto abort;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-01-13 16:02:15 +01:00
|
|
|
mutex_init(&ctrl->crit_sect);
|
2006-01-26 01:59:24 +01:00
|
|
|
mutex_init(&ctrl->cmd_lock);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/* Setup wait queue */
|
|
|
|
init_waitqueue_head(&ctrl->queue);
|
|
|
|
|
2006-05-02 04:08:42 +02:00
|
|
|
ctrl->hpc_ops = &shpchp_hpc_ops;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/* Return PCI Controller Info */
|
2006-05-02 04:08:42 +02:00
|
|
|
slot_config = shpc_readl(ctrl, SLOT_CONFIG);
|
2006-12-17 00:25:34 +01:00
|
|
|
ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
|
|
|
|
ctrl->num_slots = slot_config & SLOT_NUM;
|
|
|
|
ctrl->first_slot = (slot_config & PSN) >> 16;
|
|
|
|
ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
|
2006-05-02 04:08:42 +02:00
|
|
|
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
|
2006-05-02 04:12:37 +02:00
|
|
|
tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
|
|
|
|
COMMAND_INTR_MASK | ARBITER_SERR_MASK);
|
|
|
|
tempdword &= ~SERR_INTR_RSVDZ_MASK;
|
2006-05-02 04:08:42 +02:00
|
|
|
shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
|
|
|
|
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* Mask the MRL sensor SERR Mask of individual slot in
|
|
|
|
* Slot SERR-INT Mask & clear all the existing event if any
|
|
|
|
*/
|
2006-12-17 00:25:34 +01:00
|
|
|
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
|
2006-05-02 04:09:42 +02:00
|
|
|
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
|
|
|
|
hp_slot, slot_reg);
|
2006-05-02 04:11:54 +02:00
|
|
|
slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
|
|
|
|
BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
|
|
|
|
CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
|
|
|
|
CON_PFAULT_SERR_MASK);
|
|
|
|
slot_reg &= ~SLOT_REG_RSVDZ_MASK;
|
|
|
|
shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2007-01-09 22:03:10 +01:00
|
|
|
|
2006-12-17 00:25:34 +01:00
|
|
|
if (shpchp_poll_mode) {
|
|
|
|
/* Install interrupt polling timer. Start with 10 sec delay */
|
|
|
|
init_timer(&ctrl->poll_timer);
|
|
|
|
start_int_poll_timer(ctrl, 10);
|
2005-04-17 00:20:36 +02:00
|
|
|
} else {
|
|
|
|
/* Installs the interrupt handler */
|
|
|
|
rc = pci_enable_msi(pdev);
|
|
|
|
if (rc) {
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_info(ctrl,
|
|
|
|
"Can't get msi for the hotplug controller\n");
|
|
|
|
ctrl_info(ctrl,
|
|
|
|
"Use INTx for the hotplug controller\n");
|
2006-12-17 00:25:34 +01:00
|
|
|
}
|
2007-01-09 22:03:10 +01:00
|
|
|
|
2006-12-17 00:25:34 +01:00
|
|
|
rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
|
|
|
|
MY_NAME, (void *)ctrl);
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, "request_irq %d for hpc%d (returns %d)\n",
|
|
|
|
ctrl->pci_dev->irq,
|
2006-12-17 00:25:34 +01:00
|
|
|
atomic_read(&shpchp_num_controllers), rc);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (rc) {
|
2008-10-23 04:52:12 +02:00
|
|
|
ctrl_err(ctrl, "Can't get irq %d for the hotplug "
|
|
|
|
"controller\n", ctrl->pci_dev->irq);
|
2006-12-17 00:25:34 +01:00
|
|
|
goto abort_iounmap;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
}
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-12-13 14:11:32 +01:00
|
|
|
shpc_get_max_bus_speed(ctrl);
|
|
|
|
shpc_get_cur_bus_speed(ctrl);
|
|
|
|
|
2006-05-03 16:42:04 +02:00
|
|
|
/*
|
|
|
|
* If this is the first controller to be initialized,
|
|
|
|
* initialize the shpchpd work queue
|
|
|
|
*/
|
|
|
|
if (atomic_add_return(1, &shpchp_num_controllers) == 1) {
|
|
|
|
shpchp_wq = create_singlethread_workqueue("shpchpd");
|
2006-10-05 08:37:32 +02:00
|
|
|
if (!shpchp_wq) {
|
|
|
|
rc = -ENOMEM;
|
2006-12-17 00:25:34 +01:00
|
|
|
goto abort_iounmap;
|
2006-10-05 08:37:32 +02:00
|
|
|
}
|
2006-05-03 16:42:04 +02:00
|
|
|
}
|
|
|
|
|
2006-05-02 04:11:54 +02:00
|
|
|
/*
|
|
|
|
* Unmask all event interrupts of all slots
|
|
|
|
*/
|
2006-12-17 00:25:34 +01:00
|
|
|
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
|
2006-05-02 04:09:42 +02:00
|
|
|
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
|
|
|
|
hp_slot, slot_reg);
|
2006-05-02 04:11:54 +02:00
|
|
|
slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
|
|
|
|
BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
|
|
|
|
CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
|
|
|
|
shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
if (!shpchp_poll_mode) {
|
|
|
|
/* Unmask all general input interrupts and SERR */
|
2006-05-02 04:08:42 +02:00
|
|
|
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
2006-05-02 04:12:37 +02:00
|
|
|
tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
|
|
|
|
SERR_INTR_RSVDZ_MASK);
|
2006-05-02 04:08:42 +02:00
|
|
|
shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
|
|
|
|
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
2008-10-23 04:54:39 +02:00
|
|
|
ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* We end up here for the many possible ways to fail this API. */
|
2006-12-17 00:25:34 +01:00
|
|
|
abort_iounmap:
|
|
|
|
iounmap(ctrl->creg);
|
2005-04-17 00:20:36 +02:00
|
|
|
abort:
|
2006-10-05 08:37:32 +02:00
|
|
|
return rc;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|