[PATCH] avr32 architecture
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.
AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density. The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.
The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit. It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.
Full data sheet is available from
http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
Information about the AT32STK1000 development board can be found at
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918
including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.
Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.
This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.
[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-26 08:32:13 +02:00
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/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* Based on MIPS implementation arch/mips/kernel/time.c
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* Copyright 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/time.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/profile.h>
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#include <linux/sysdev.h>
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#include <asm/div64.h>
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#include <asm/sysreg.h>
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#include <asm/io.h>
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#include <asm/sections.h>
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static cycle_t read_cycle_count(void)
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{
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return (cycle_t)sysreg_read(COUNT);
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}
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static struct clocksource clocksource_avr32 = {
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.name = "avr32",
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.rating = 350,
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.read = read_cycle_count,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 16,
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.is_continuous = 1,
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};
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/*
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* By default we provide the null RTC ops
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*/
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static unsigned long null_rtc_get_time(void)
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{
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return mktime(2004, 1, 1, 0, 0, 0);
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}
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static int null_rtc_set_time(unsigned long sec)
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{
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return 0;
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}
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static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
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static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
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/* how many counter cycles in a jiffy? */
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static unsigned long cycles_per_jiffy;
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/* cycle counter value at the previous timer interrupt */
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static unsigned int timerhi, timerlo;
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/* the count value for the next timer interrupt */
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static unsigned int expirelo;
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static void avr32_timer_ack(void)
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{
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unsigned int count;
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/* Ack this timer interrupt and set the next one */
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expirelo += cycles_per_jiffy;
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if (expirelo == 0) {
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printk(KERN_DEBUG "expirelo == 0\n");
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sysreg_write(COMPARE, expirelo + 1);
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} else {
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sysreg_write(COMPARE, expirelo);
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}
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/* Check to see if we have missed any timer interrupts */
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count = sysreg_read(COUNT);
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if ((count - expirelo) < 0x7fffffff) {
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expirelo = count + cycles_per_jiffy;
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sysreg_write(COMPARE, expirelo);
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}
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}
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static unsigned int avr32_hpt_read(void)
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{
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return sysreg_read(COUNT);
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}
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/*
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* Taken from MIPS c0_hpt_timer_init().
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*
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* Why is it so complicated, and what is "count"? My assumption is
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* that `count' specifies the "reference cycle", i.e. the cycle since
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* reset that should mean "zero". The reason COUNT is written twice is
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* probably to make sure we don't get any timer interrupts while we
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* are messing with the counter.
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*/
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static void avr32_hpt_init(unsigned int count)
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{
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count = sysreg_read(COUNT) - count;
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expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
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sysreg_write(COUNT, expirelo - cycles_per_jiffy);
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sysreg_write(COMPARE, expirelo);
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sysreg_write(COUNT, count);
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}
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/*
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* Scheduler clock - returns current time in nanosec units.
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*/
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unsigned long long sched_clock(void)
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{
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/* There must be better ways...? */
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return (unsigned long long)jiffies * (1000000000 / HZ);
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}
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/*
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* local_timer_interrupt() does profiling and process accounting on a
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* per-CPU basis.
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*
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* In UP mode, it is invoked from the (global) timer_interrupt.
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*/
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static void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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if (current->pid)
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profile_tick(CPU_PROFILING, regs);
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update_process_times(user_mode(regs));
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}
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static irqreturn_t
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timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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unsigned int count;
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/* ack timer interrupt and try to set next interrupt */
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count = avr32_hpt_read();
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avr32_timer_ack();
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/* Update timerhi/timerlo for intra-jiffy calibration */
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timerhi += count < timerlo; /* Wrap around */
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timerlo = count;
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/*
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* Call the generic timer interrupt handler
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*/
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write_seqlock(&xtime_lock);
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2006-09-29 11:00:32 +02:00
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do_timer(1);
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[PATCH] avr32 architecture
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.
AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density. The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.
The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit. It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.
Full data sheet is available from
http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
Information about the AT32STK1000 development board can be found at
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918
including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.
Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.
This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.
[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-26 08:32:13 +02:00
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write_sequnlock(&xtime_lock);
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/*
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* In UP mode, we call local_timer_interrupt() to do profiling
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* and process accounting.
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*
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* SMP is not supported yet.
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*/
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local_timer_interrupt(irq, dev_id, regs);
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return IRQ_HANDLED;
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}
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static struct irqaction timer_irqaction = {
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED,
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.name = "timer",
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};
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void __init time_init(void)
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{
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unsigned long mult, shift, count_hz;
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int ret;
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xtime.tv_sec = rtc_get_time();
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xtime.tv_nsec = 0;
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set_normalized_timespec(&wall_to_monotonic,
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-xtime.tv_sec, -xtime.tv_nsec);
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printk("Before time_init: count=%08lx, compare=%08lx\n",
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(unsigned long)sysreg_read(COUNT),
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(unsigned long)sysreg_read(COMPARE));
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count_hz = clk_get_rate(boot_cpu_data.clk);
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shift = clocksource_avr32.shift;
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mult = clocksource_hz2mult(count_hz, shift);
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clocksource_avr32.mult = mult;
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printk("Cycle counter: mult=%lu, shift=%lu\n", mult, shift);
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{
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u64 tmp;
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tmp = TICK_NSEC;
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tmp <<= shift;
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tmp += mult / 2;
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do_div(tmp, mult);
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cycles_per_jiffy = tmp;
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}
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/* This sets up the high precision timer for the first interrupt. */
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avr32_hpt_init(avr32_hpt_read());
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printk("After time_init: count=%08lx, compare=%08lx\n",
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(unsigned long)sysreg_read(COUNT),
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(unsigned long)sysreg_read(COMPARE));
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ret = clocksource_register(&clocksource_avr32);
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if (ret)
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printk(KERN_ERR
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"timer: could not register clocksource: %d\n", ret);
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ret = setup_irq(0, &timer_irqaction);
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if (ret)
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printk("timer: could not request IRQ 0: %d\n", ret);
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}
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static struct sysdev_class timer_class = {
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set_kset_name("timer"),
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};
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static struct sys_device timer_device = {
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.id = 0,
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.cls = &timer_class,
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};
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static int __init init_timer_sysfs(void)
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{
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int err = sysdev_class_register(&timer_class);
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if (!err)
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err = sysdev_register(&timer_device);
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return err;
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}
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device_initcall(init_timer_sysfs);
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