License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 15:07:57 +01:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-17 00:20:36 +02:00
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/*
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* linux/arch/arm/kernel/bios32.c
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*
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* PCI bios-type initialisation for PCI machines
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*
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* Bits taken from various places.
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*/
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2011-07-22 16:58:34 +02:00
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#include <linux/export.h>
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2005-04-17 00:20:36 +02:00
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/init.h>
|
2008-09-06 13:10:45 +02:00
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#include <linux/io.h>
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2005-04-17 00:20:36 +02:00
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#include <asm/mach-types.h>
|
2012-03-01 01:10:58 +01:00
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#include <asm/mach/map.h>
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2005-04-17 00:20:36 +02:00
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#include <asm/mach/pci.h>
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static int debug_pci;
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/*
|
2014-02-13 12:57:43 +01:00
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* We can't use pci_get_device() here since we are
|
2005-04-17 00:20:36 +02:00
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* called from interrupt context.
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*/
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static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 status;
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/*
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* ignore host bridge - we handle
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* that separately
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*/
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if (dev->bus->number == 0 && dev->devfn == 0)
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continue;
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pci_read_config_word(dev, PCI_STATUS, &status);
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if (status == 0xffff)
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continue;
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if ((status & status_mask) == 0)
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continue;
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/* clear the status errors */
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pci_write_config_word(dev, PCI_STATUS, status & status_mask);
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if (warn)
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printk("(%s: %04X) ", pci_name(dev), status);
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}
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list_for_each_entry(dev, &bus->devices, bus_list)
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if (dev->subordinate)
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pcibios_bus_report_status(dev->subordinate, status_mask, warn);
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}
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void pcibios_report_status(u_int status_mask, int warn)
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{
|
2014-02-13 14:13:59 +01:00
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struct pci_bus *bus;
|
2005-04-17 00:20:36 +02:00
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2014-02-13 14:13:59 +01:00
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list_for_each_entry(bus, &pci_root_buses, node)
|
2005-04-17 00:20:36 +02:00
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pcibios_bus_report_status(bus, status_mask, warn);
|
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}
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/*
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|
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* We don't use this to fix the device, but initialisation of it.
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* It's not the correct use for this, but it works.
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|
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* Note that the arbiter/ISA bridge appears to be buggy, specifically in
|
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* the following area:
|
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* 1. park on CPU
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* 2. ISA bridge ping-pong
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* 3. ISA bridge master handling of target RETRY
|
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*
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* Bug 3 is responsible for the sound DMA grinding to a halt. We now
|
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* live with bug 2.
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|
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*/
|
2012-12-21 23:02:24 +01:00
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static void pci_fixup_83c553(struct pci_dev *dev)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
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/*
|
|
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* Set memory region to start at address 0, and enable IO
|
|
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|
*/
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
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pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
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dev->resource[0].end -= dev->resource[0].start;
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dev->resource[0].start = 0;
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/*
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* All memory requests from ISA to be channelled to PCI
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*/
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pci_write_config_byte(dev, 0x48, 0xff);
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/*
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* Enable ping-pong on bus master to ISA bridge transactions.
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* This improves the sound DMA substantially. The fixed
|
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* priority arbiter also helps (see below).
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*/
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pci_write_config_byte(dev, 0x42, 0x01);
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/*
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* Enable PCI retry
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*/
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pci_write_config_byte(dev, 0x40, 0x22);
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/*
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* We used to set the arbiter to "park on last master" (bit
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* 1 set), but unfortunately the CyberPro does not park the
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* bus. We must therefore park on CPU. Unfortunately, this
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* may trigger yet another bug in the 553.
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*/
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pci_write_config_byte(dev, 0x83, 0x02);
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/*
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* Make the ISA DMA request lowest priority, and disable
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* rotating priorities completely.
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*/
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pci_write_config_byte(dev, 0x80, 0x11);
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pci_write_config_byte(dev, 0x81, 0x00);
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/*
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* Route INTA input to IRQ 11, and set IRQ11 to be level
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* sensitive.
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*/
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pci_write_config_word(dev, 0x44, 0xb000);
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outb(0x08, 0x4d1);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
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|
2012-12-21 23:02:24 +01:00
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static void pci_fixup_unassign(struct pci_dev *dev)
|
2005-04-17 00:20:36 +02:00
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{
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dev->resource[0].end -= dev->resource[0].start;
|
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dev->resource[0].start = 0;
|
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
|
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/*
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|
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* Prevent the PCI layer from seeing the resources allocated to this device
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* if it is the host bridge by marking it as such. These resources are of
|
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* no consequence to the PCI layer (they are handled elsewhere).
|
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*/
|
2012-12-21 23:02:24 +01:00
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static void pci_fixup_dec21285(struct pci_dev *dev)
|
2005-04-17 00:20:36 +02:00
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{
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int i;
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if (dev->devfn == 0) {
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dev->class &= 0xff;
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dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
|
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/*
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* PCI IDE controllers use non-standard I/O port decoding, respect it.
|
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*/
|
2012-12-21 23:02:24 +01:00
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static void pci_fixup_ide_bases(struct pci_dev *dev)
|
2005-04-17 00:20:36 +02:00
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{
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struct resource *r;
|
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int i;
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if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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r = dev->resource + i;
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if ((r->start & ~0x80) == 0x374) {
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r->start |= 2;
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r->end = r->start;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
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/*
|
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* Put the DEC21142 to sleep
|
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*/
|
2012-12-21 23:02:24 +01:00
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static void pci_fixup_dec21142(struct pci_dev *dev)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
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|
pci_write_config_dword(dev, 0x40, 0x80000000);
|
|
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|
}
|
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
|
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/*
|
|
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|
* The CY82C693 needs some rather major fixups to ensure that it does
|
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* the right thing. Idea from the Alpha people, with a few additions.
|
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*
|
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* We ensure that the IDE base registers are set to 1f0/3f4 for the
|
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* primary bus, and 170/374 for the secondary bus. Also, hide them
|
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* from the PCI subsystem view as well so we won't try to perform
|
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* our own auto-configuration on them.
|
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*
|
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* In addition, we ensure that the PCI IDE interrupts are routed to
|
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* IRQ 14 and IRQ 15 respectively.
|
|
|
|
*
|
|
|
|
* The above gets us to a point where the IDE on this device is
|
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|
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* functional. However, The CY82C693U _does not work_ in bus
|
|
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* master mode without locking the PCI bus solid.
|
|
|
|
*/
|
2012-12-21 23:02:24 +01:00
|
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static void pci_fixup_cy82c693(struct pci_dev *dev)
|
2005-04-17 00:20:36 +02:00
|
|
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{
|
|
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if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
|
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u32 base0, base1;
|
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|
|
|
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if (dev->class & 0x80) { /* primary */
|
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base0 = 0x1f0;
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base1 = 0x3f4;
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} else { /* secondary */
|
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base0 = 0x170;
|
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base1 = 0x374;
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}
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
|
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base0 | PCI_BASE_ADDRESS_SPACE_IO);
|
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
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base1 | PCI_BASE_ADDRESS_SPACE_IO);
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dev->resource[0].start = 0;
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dev->resource[0].end = 0;
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dev->resource[0].flags = 0;
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dev->resource[1].start = 0;
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dev->resource[1].end = 0;
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dev->resource[1].flags = 0;
|
|
|
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} else if (PCI_FUNC(dev->devfn) == 0) {
|
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/*
|
|
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* Setup IDE IRQ routing.
|
|
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|
*/
|
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pci_write_config_byte(dev, 0x4b, 14);
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pci_write_config_byte(dev, 0x4c, 15);
|
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|
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|
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/*
|
|
|
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* Disable FREQACK handshake, enable USB.
|
|
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|
*/
|
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pci_write_config_byte(dev, 0x4d, 0x41);
|
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/*
|
|
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|
* Enable PCI retry, and PCI post-write buffer.
|
|
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|
*/
|
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pci_write_config_byte(dev, 0x44, 0x17);
|
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|
/*
|
|
|
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* Enable ISA master and DMA post write buffering.
|
|
|
|
*/
|
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|
|
pci_write_config_byte(dev, 0x45, 0x03);
|
|
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}
|
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}
|
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
|
|
|
|
|
2012-12-21 23:02:24 +01:00
|
|
|
static void pci_fixup_it8152(struct pci_dev *dev)
|
2007-09-23 16:59:52 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
/* fixup for ITE 8152 devices */
|
|
|
|
/* FIXME: add defines for class 0x68000 and 0x80103 */
|
|
|
|
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
|
|
|
|
dev->class == 0x68000 ||
|
|
|
|
dev->class == 0x80103) {
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
|
|
|
dev->resource[i].start = 0;
|
|
|
|
dev->resource[i].end = 0;
|
|
|
|
dev->resource[i].flags = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/*
|
|
|
|
* If the bus contains any of these devices, then we must not turn on
|
|
|
|
* parity checking of any kind. Currently this is CyberPro 20x0 only.
|
|
|
|
*/
|
|
|
|
static inline int pdev_bad_for_parity(struct pci_dev *dev)
|
|
|
|
{
|
2007-09-23 16:59:52 +02:00
|
|
|
return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
|
|
|
|
(dev->device == PCI_DEVICE_ID_INTERG_2000 ||
|
|
|
|
dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
|
|
|
|
(dev->vendor == PCI_VENDOR_ID_ITE &&
|
|
|
|
dev->device == PCI_DEVICE_ID_ITE_8152));
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* pcibios_fixup_bus - Called after each bus is probed,
|
|
|
|
* but before its children are examined.
|
|
|
|
*/
|
2007-09-30 18:36:22 +02:00
|
|
|
void pcibios_fixup_bus(struct pci_bus *bus)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
struct pci_dev *dev;
|
|
|
|
u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Walk the devices on this bus, working out what we can
|
|
|
|
* and can't support.
|
|
|
|
*/
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
|
|
u16 status;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_STATUS, &status);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If any device on this bus does not support fast back
|
|
|
|
* to back transfers, then the bus as a whole is not able
|
|
|
|
* to support them. Having fast back to back transfers
|
|
|
|
* on saves us one PCI cycle per transaction.
|
|
|
|
*/
|
|
|
|
if (!(status & PCI_STATUS_FAST_BACK))
|
|
|
|
features &= ~PCI_COMMAND_FAST_BACK;
|
|
|
|
|
|
|
|
if (pdev_bad_for_parity(dev))
|
|
|
|
features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
|
|
|
|
|
|
|
|
switch (dev->class >> 8) {
|
|
|
|
case PCI_CLASS_BRIDGE_PCI:
|
|
|
|
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
|
|
|
|
status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
|
|
|
|
status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
|
|
|
|
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_CLASS_BRIDGE_CARDBUS:
|
|
|
|
pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
|
|
|
|
status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
|
|
|
|
pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now walk the devices again, this time setting them up.
|
|
|
|
*/
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
|
|
u16 cmd;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
|
|
cmd |= features;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
|
|
|
|
|
|
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
|
|
|
|
L1_CACHE_BYTES >> 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Propagate the flags to the PCI bridge.
|
|
|
|
*/
|
|
|
|
if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
|
|
|
|
if (features & PCI_COMMAND_FAST_BACK)
|
|
|
|
bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
|
|
|
|
if (features & PCI_COMMAND_PARITY)
|
|
|
|
bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Report what we did for this bus
|
|
|
|
*/
|
2014-10-28 12:26:42 +01:00
|
|
|
pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
|
2005-04-17 00:20:36 +02:00
|
|
|
bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
|
|
|
|
}
|
2011-09-04 22:30:06 +02:00
|
|
|
EXPORT_SYMBOL(pcibios_fixup_bus);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/*
|
2012-03-10 12:39:33 +01:00
|
|
|
* Swizzle the device pin each time we cross a bridge. If a platform does
|
|
|
|
* not provide a swizzle function, we perform the standard PCI swizzling.
|
|
|
|
*
|
|
|
|
* The default swizzling walks up the bus tree one level at a time, applying
|
|
|
|
* the standard swizzle function at each step, stopping when it finds the PCI
|
|
|
|
* root bus. This will return the slot number of the bridge device on the
|
|
|
|
* root bus and the interrupt pin on that device which should correspond
|
|
|
|
* with the downstream device interrupt.
|
|
|
|
*
|
|
|
|
* Platforms may override this, in which case the slot and pin returned
|
|
|
|
* depend entirely on the platform code. However, please note that the
|
|
|
|
* PCI standard swizzle is implemented on plug-in cards and Cardbus based
|
|
|
|
* PCI extenders, so it can not be ignored.
|
2005-04-17 00:20:36 +02:00
|
|
|
*/
|
2012-12-21 23:02:24 +01:00
|
|
|
static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
struct pci_sys_data *sys = dev->sysdata;
|
2012-03-10 12:39:33 +01:00
|
|
|
int slot, oldpin = *pin;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
if (sys->swizzle)
|
|
|
|
slot = sys->swizzle(dev, pin);
|
2012-03-10 12:39:33 +01:00
|
|
|
else
|
|
|
|
slot = pci_common_swizzle(dev, pin);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
if (debug_pci)
|
|
|
|
printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
|
|
|
|
pci_name(dev), oldpin, *pin, slot);
|
|
|
|
|
|
|
|
return slot;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Map a slot/pin to an IRQ.
|
|
|
|
*/
|
2011-06-10 16:30:21 +02:00
|
|
|
static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
struct pci_sys_data *sys = dev->sysdata;
|
|
|
|
int irq = -1;
|
|
|
|
|
|
|
|
if (sys->map_irq)
|
|
|
|
irq = sys->map_irq(dev, slot, pin);
|
|
|
|
|
|
|
|
if (debug_pci)
|
|
|
|
printk("PCI: %s mapping slot %d pin %d => irq %d\n",
|
|
|
|
pci_name(dev), slot, pin, irq);
|
|
|
|
|
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
|
2016-06-21 17:54:29 +02:00
|
|
|
static int pcibios_init_resource(int busnr, struct pci_sys_data *sys,
|
|
|
|
int io_optional)
|
2012-07-10 04:59:03 +02:00
|
|
|
{
|
|
|
|
int ret;
|
2015-02-05 06:44:44 +01:00
|
|
|
struct resource_entry *window;
|
2012-07-10 04:59:03 +02:00
|
|
|
|
|
|
|
if (list_empty(&sys->resources)) {
|
|
|
|
pci_add_resource_offset(&sys->resources,
|
|
|
|
&iomem_resource, sys->mem_offset);
|
|
|
|
}
|
|
|
|
|
2016-06-21 17:54:29 +02:00
|
|
|
/*
|
|
|
|
* If a platform says I/O port support is optional, we don't add
|
|
|
|
* the default I/O space. The platform is responsible for adding
|
|
|
|
* any I/O space it needs.
|
|
|
|
*/
|
|
|
|
if (io_optional)
|
|
|
|
return 0;
|
|
|
|
|
2015-02-05 06:44:44 +01:00
|
|
|
resource_list_for_each_entry(window, &sys->resources)
|
2012-07-10 04:59:03 +02:00
|
|
|
if (resource_type(window->res) == IORESOURCE_IO)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
|
|
|
|
sys->io_res.end = (busnr + 1) * SZ_64K - 1;
|
|
|
|
sys->io_res.flags = IORESOURCE_IO;
|
|
|
|
sys->io_res.name = sys->io_res_name;
|
|
|
|
sprintf(sys->io_res_name, "PCI%d I/O", busnr);
|
|
|
|
|
|
|
|
ret = request_resource(&ioport_resource, &sys->io_res);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
pci_add_resource_offset(&sys->resources, &sys->io_res,
|
|
|
|
sys->io_offset);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-04-11 23:32:28 +02:00
|
|
|
static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
|
|
|
|
struct list_head *head)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
struct pci_sys_data *sys = NULL;
|
|
|
|
int ret;
|
|
|
|
int nr, busnr;
|
|
|
|
|
|
|
|
for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
|
2017-06-28 22:13:55 +02:00
|
|
|
struct pci_host_bridge *bridge;
|
|
|
|
|
|
|
|
bridge = pci_alloc_host_bridge(sizeof(struct pci_sys_data));
|
|
|
|
if (WARN(!bridge, "PCI: unable to allocate bridge!"))
|
2015-07-29 13:33:17 +02:00
|
|
|
break;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2017-06-28 22:13:55 +02:00
|
|
|
sys = pci_host_bridge_priv(bridge);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
sys->busnr = busnr;
|
|
|
|
sys->swizzle = hw->swizzle;
|
|
|
|
sys->map_irq = hw->map_irq;
|
2011-10-29 00:26:16 +02:00
|
|
|
INIT_LIST_HEAD(&sys->resources);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2013-02-11 08:46:10 +01:00
|
|
|
if (hw->private_data)
|
|
|
|
sys->private_data = hw->private_data[nr];
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
ret = hw->setup(nr, sys);
|
|
|
|
|
|
|
|
if (ret > 0) {
|
2015-11-11 02:12:25 +01:00
|
|
|
|
2016-06-21 17:54:29 +02:00
|
|
|
ret = pcibios_init_resource(nr, sys, hw->io_optional);
|
2012-07-10 04:59:03 +02:00
|
|
|
if (ret) {
|
2017-07-10 14:34:08 +02:00
|
|
|
pci_free_host_bridge(bridge);
|
2012-07-10 04:59:03 +02:00
|
|
|
break;
|
2011-10-29 00:26:16 +02:00
|
|
|
}
|
|
|
|
|
2017-06-28 22:14:04 +02:00
|
|
|
bridge->map_irq = pcibios_map_irq;
|
|
|
|
bridge->swizzle_irq = pcibios_swizzle;
|
|
|
|
|
2012-03-10 13:49:16 +01:00
|
|
|
if (hw->scan)
|
2017-06-28 22:13:55 +02:00
|
|
|
ret = hw->scan(nr, bridge);
|
|
|
|
else {
|
|
|
|
list_splice_init(&sys->resources,
|
|
|
|
&bridge->windows);
|
|
|
|
bridge->dev.parent = parent;
|
|
|
|
bridge->sysdata = sys;
|
|
|
|
bridge->busnr = sys->busnr;
|
|
|
|
bridge->ops = hw->ops;
|
|
|
|
bridge->msi = hw->msi_ctrl;
|
|
|
|
bridge->align_resource =
|
|
|
|
hw->align_resource;
|
|
|
|
|
|
|
|
ret = pci_scan_root_bus_bridge(bridge);
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2017-06-28 22:13:55 +02:00
|
|
|
if (WARN(ret < 0, "PCI: unable to scan bus!")) {
|
|
|
|
pci_free_host_bridge(bridge);
|
2015-07-29 13:33:17 +02:00
|
|
|
break;
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2017-06-28 22:13:55 +02:00
|
|
|
sys->bus = bridge->bus;
|
|
|
|
|
2012-05-18 03:51:11 +02:00
|
|
|
busnr = sys->bus->busn_res.end + 1;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2012-03-10 15:21:06 +01:00
|
|
|
list_add(&sys->node, head);
|
2005-04-17 00:20:36 +02:00
|
|
|
} else {
|
2017-06-28 22:13:55 +02:00
|
|
|
pci_free_host_bridge(bridge);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (ret < 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-11 23:32:28 +02:00
|
|
|
void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
struct pci_sys_data *sys;
|
2012-03-10 15:21:06 +01:00
|
|
|
LIST_HEAD(head);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
PCI: Remove PCI_REASSIGN_ALL_RSRC use on arm and arm64
On arm, PCI_REASSIGN_ALL_RSRC is used only in pcibios_assign_all_busses(),
which helps decide whether to reconfigure bridge bus numbers. It has
nothing to do with BAR assignments. On arm64 and powerpc,
pcibios_assign_all_busses() tests PCI_REASSIGN_ALL_BUS, which makes more
sense.
Align arm with arm64 and powerpc, so they all use PCI_REASSIGN_ALL_BUS for
pcibios_assign_all_busses().
Remove PCI_REASSIGN_ALL_RSRC from the generic, Tegra, Versatile, and
R-Car drivers. These drivers are used only on arm or arm64, where
PCI_REASSIGN_ALL_RSRC is not used after this change, so removing it
should have no effect.
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2017-11-30 18:21:57 +01:00
|
|
|
pci_add_flags(PCI_REASSIGN_ALL_BUS);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (hw->preinit)
|
|
|
|
hw->preinit();
|
2013-04-11 23:32:28 +02:00
|
|
|
pcibios_init_hw(parent, hw, &head);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (hw->postinit)
|
|
|
|
hw->postinit();
|
|
|
|
|
2012-03-10 15:21:06 +01:00
|
|
|
list_for_each_entry(sys, &head, node) {
|
2005-04-17 00:20:36 +02:00
|
|
|
struct pci_bus *bus = sys->bus;
|
|
|
|
|
ARM/PCI: Claim bus resources on PCI_PROBE_ONLY set-ups
We claim PCI BAR and bridge window resources in pci_bus_assign_resources(),
but when PCI_PROBE_ONLY is set, we treat those resources as immutable and
don't call pci_bus_assign_resources(), so the resources aren't put in the
resource tree.
When the resources aren't in the tree, they don't show up in /proc/iomem,
we can't detect conflicts, and we need special cases elsewhere for
PCI_PROBE_ONLY or resources without a parent pointer.
Claim all PCI BAR and window resources in the PCI_PROBE_ONLY case.
If a PCI_PROBE_ONLY platform assigns conflicting resources, Linux can't fix
the conflicts. Previously we didn't notice the conflicts, but now we will,
which may expose new failures.
[bhelgaas: changelog, add resource comment, remove size/assign comments]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Russell King <linux@armlinux.org.uk>
2016-06-23 12:36:22 +02:00
|
|
|
/*
|
|
|
|
* We insert PCI resources into the iomem_resource and
|
|
|
|
* ioport_resource trees in either pci_bus_claim_resources()
|
|
|
|
* or pci_bus_assign_resources().
|
|
|
|
*/
|
|
|
|
if (pci_has_flag(PCI_PROBE_ONLY)) {
|
|
|
|
pci_bus_claim_resources(bus);
|
|
|
|
} else {
|
2015-07-21 23:35:19 +02:00
|
|
|
struct pci_bus *child;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
pci_bus_size_bridges(bus);
|
|
|
|
pci_bus_assign_resources(bus);
|
|
|
|
|
2015-07-21 23:35:19 +02:00
|
|
|
list_for_each_entry(child, &bus->children, node)
|
|
|
|
pcie_bus_configure_settings(child);
|
|
|
|
}
|
ARM/PCI: Claim bus resources on PCI_PROBE_ONLY set-ups
We claim PCI BAR and bridge window resources in pci_bus_assign_resources(),
but when PCI_PROBE_ONLY is set, we treat those resources as immutable and
don't call pci_bus_assign_resources(), so the resources aren't put in the
resource tree.
When the resources aren't in the tree, they don't show up in /proc/iomem,
we can't detect conflicts, and we need special cases elsewhere for
PCI_PROBE_ONLY or resources without a parent pointer.
Claim all PCI BAR and window resources in the PCI_PROBE_ONLY case.
If a PCI_PROBE_ONLY platform assigns conflicting resources, Linux can't fix
the conflicts. Previously we didn't notice the conflicts, but now we will,
which may expose new failures.
[bhelgaas: changelog, add resource comment, remove size/assign comments]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Russell King <linux@armlinux.org.uk>
2016-06-23 12:36:22 +02:00
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2005-04-17 00:20:36 +02:00
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pci_bus_add_devices(bus);
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}
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}
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2011-10-28 23:47:42 +02:00
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#ifndef CONFIG_PCI_HOST_ITE8152
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void pcibios_set_master(struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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#endif
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2005-04-17 00:20:36 +02:00
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char * __init pcibios_setup(char *str)
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{
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if (!strcmp(str, "debug")) {
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debug_pci = 1;
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return NULL;
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}
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return str;
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}
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/*
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* From arch/i386/kernel/pci-i386.c:
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*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might be mirrored at 0x0100-0x03ff..
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*/
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2010-01-01 17:40:50 +01:00
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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2010-01-01 17:40:49 +01:00
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resource_size_t size, resource_size_t align)
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2005-04-17 00:20:36 +02:00
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{
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2013-03-26 18:14:24 +01:00
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struct pci_dev *dev = data;
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2006-06-13 02:06:02 +02:00
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resource_size_t start = res->start;
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2015-11-11 02:12:25 +01:00
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struct pci_host_bridge *host_bridge;
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2005-04-17 00:20:36 +02:00
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if (res->flags & IORESOURCE_IO && start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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2010-01-01 17:40:49 +01:00
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start = (start + align - 1) & ~(align - 1);
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2015-11-11 02:12:25 +01:00
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host_bridge = pci_find_host_bridge(dev->bus);
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if (host_bridge->align_resource)
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return host_bridge->align_resource(dev, res,
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start, size, align);
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2013-03-26 18:14:24 +01:00
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2010-01-01 17:40:49 +01:00
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return start;
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2005-04-17 00:20:36 +02:00
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}
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2012-03-01 01:10:58 +01:00
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void __init pci_map_io_early(unsigned long pfn)
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{
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struct map_desc pci_io_desc = {
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.virtual = PCI_IO_VIRT_BASE,
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.type = MT_DEVICE,
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.length = SZ_64K,
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};
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pci_io_desc.pfn = pfn;
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iotable_init(&pci_io_desc, 1);
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}
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