2005-04-17 00:20:36 +02:00
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/* $Id: trampoline.S,v 1.26 2002/02/09 19:49:30 davem Exp $
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* trampoline.S: Jump start slave processors on sparc64.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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2008-02-21 07:22:16 +01:00
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#include <linux/init.h>
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2005-04-17 00:20:36 +02:00
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#include <asm/head.h>
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#include <asm/asi.h>
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#include <asm/lsu.h>
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#include <asm/dcr.h>
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#include <asm/dcu.h>
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#include <asm/pstate.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/spitfire.h>
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#include <asm/processor.h>
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#include <asm/thread_info.h>
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#include <asm/mmu.h>
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2006-02-09 11:52:44 +01:00
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#include <asm/hypervisor.h>
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2006-02-14 09:55:49 +01:00
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#include <asm/cpudata.h>
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2005-04-17 00:20:36 +02:00
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.data
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.align 8
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call_method:
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.asciz "call-method"
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.align 8
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itlb_load:
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.asciz "SUNW,itlb-load"
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.align 8
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dtlb_load:
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.asciz "SUNW,dtlb-load"
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[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 10:29:17 +01:00
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/* XXX __cpuinit this thing XXX */
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#define TRAMP_STACK_SIZE 1024
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.align 16
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tramp_stack:
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.skip TRAMP_STACK_SIZE
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2008-02-21 07:22:16 +01:00
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__CPUINIT
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2005-04-17 00:20:36 +02:00
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.align 8
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.globl sparc64_cpu_startup, sparc64_cpu_startup_end
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sparc64_cpu_startup:
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2006-02-09 11:52:44 +01:00
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BRANCH_IF_SUN4V(g1, niagara_startup)
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BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
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2005-04-17 00:20:36 +02:00
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ba,pt %xcc, spitfire_startup
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nop
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cheetah_plus_startup:
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/* Preserve OBP chosen DCU and DCR register settings. */
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ba,pt %xcc, cheetah_generic_startup
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nop
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cheetah_startup:
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mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
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wr %g1, %asr18
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sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
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or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
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sllx %g5, 32, %g5
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or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
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stxa %g5, [%g0] ASI_DCU_CONTROL_REG
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membar #Sync
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[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 10:29:17 +01:00
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/* fallthru */
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2005-04-17 00:20:36 +02:00
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cheetah_generic_startup:
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mov TSB_EXTENSION_P, %g3
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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mov TSB_EXTENSION_S, %g3
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stxa %g0, [%g3] ASI_DMMU
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membar #Sync
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mov TSB_EXTENSION_N, %g3
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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2006-02-09 11:52:44 +01:00
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/* fallthru */
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2005-04-17 00:20:36 +02:00
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2006-02-09 11:52:44 +01:00
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niagara_startup:
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2005-04-17 00:20:36 +02:00
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/* Disable STICK_INT interrupts. */
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sethi %hi(0x80000000), %g5
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sllx %g5, 32, %g5
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wr %g5, %asr25
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ba,pt %xcc, startup_continue
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nop
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spitfire_startup:
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mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
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stxa %g1, [%g0] ASI_LSU_CONTROL
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membar #Sync
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startup_continue:
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2007-08-16 10:56:00 +02:00
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mov %o0, %l0
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BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
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2005-04-17 00:20:36 +02:00
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sethi %hi(0x80000000), %g2
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sllx %g2, 32, %g2
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wr %g2, 0, %tick_cmpr
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/* Call OBP by hand to lock KERNBASE into i/d tlbs.
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* We lock 2 consequetive entries if we are 'bigkernel'.
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*/
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sethi %hi(prom_entry_lock), %g2
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1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 00:42:04 +02:00
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membar #StoreLoad | #StoreStore
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2005-04-17 00:20:36 +02:00
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brnz,pn %g1, 1b
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 00:42:04 +02:00
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nop
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2005-04-17 00:20:36 +02:00
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x10], %l2
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add %l2, -(192 + 128), %sp
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flushw
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(itlb_load), %g2
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or %g2, %lo(itlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 05:11:33 +02:00
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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2005-04-17 00:20:36 +02:00
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stx %g2, [%sp + 2047 + 128 + 0x20]
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sethi %hi(KERNBASE), %g2
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stx %g2, [%sp + 2047 + 128 + 0x28]
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sethi %hi(kern_locked_tte_data), %g2
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ldx [%g2 + %lo(kern_locked_tte_data)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x30]
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mov 15, %g2
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BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
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mov 63, %g2
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1:
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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sethi %hi(bigkernel), %g2
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lduw [%g2 + %lo(bigkernel)], %g2
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2006-02-09 11:52:44 +01:00
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brz,pt %g2, do_dtlb
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2005-04-17 00:20:36 +02:00
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nop
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(itlb_load), %g2
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or %g2, %lo(itlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 05:11:33 +02:00
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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2005-04-17 00:20:36 +02:00
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stx %g2, [%sp + 2047 + 128 + 0x20]
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sethi %hi(KERNBASE + 0x400000), %g2
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stx %g2, [%sp + 2047 + 128 + 0x28]
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sethi %hi(kern_locked_tte_data), %g2
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ldx [%g2 + %lo(kern_locked_tte_data)], %g2
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sethi %hi(0x400000), %g1
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add %g2, %g1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x30]
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mov 14, %g2
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BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
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mov 62, %g2
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1:
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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do_dtlb:
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(dtlb_load), %g2
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or %g2, %lo(dtlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 05:11:33 +02:00
|
|
|
sethi %hi(prom_mmu_ihandle_cache), %g2
|
|
|
|
lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
|
2005-04-17 00:20:36 +02:00
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x20]
|
|
|
|
sethi %hi(KERNBASE), %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x28]
|
|
|
|
sethi %hi(kern_locked_tte_data), %g2
|
|
|
|
ldx [%g2 + %lo(kern_locked_tte_data)], %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x30]
|
|
|
|
|
|
|
|
mov 15, %g2
|
|
|
|
BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
|
|
|
|
|
|
|
|
mov 63, %g2
|
|
|
|
1:
|
|
|
|
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x38]
|
|
|
|
sethi %hi(p1275buf), %g2
|
|
|
|
or %g2, %lo(p1275buf), %g2
|
|
|
|
ldx [%g2 + 0x08], %o1
|
|
|
|
call %o1
|
|
|
|
add %sp, (2047 + 128), %o0
|
|
|
|
|
|
|
|
sethi %hi(bigkernel), %g2
|
|
|
|
lduw [%g2 + %lo(bigkernel)], %g2
|
2006-02-09 11:52:44 +01:00
|
|
|
brz,pt %g2, do_unlock
|
2005-04-17 00:20:36 +02:00
|
|
|
nop
|
|
|
|
|
|
|
|
sethi %hi(call_method), %g2
|
|
|
|
or %g2, %lo(call_method), %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x00]
|
|
|
|
mov 5, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x08]
|
|
|
|
mov 1, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x10]
|
|
|
|
sethi %hi(dtlb_load), %g2
|
|
|
|
or %g2, %lo(dtlb_load), %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x18]
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 05:11:33 +02:00
|
|
|
sethi %hi(prom_mmu_ihandle_cache), %g2
|
|
|
|
lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
|
2005-04-17 00:20:36 +02:00
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x20]
|
|
|
|
sethi %hi(KERNBASE + 0x400000), %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x28]
|
|
|
|
sethi %hi(kern_locked_tte_data), %g2
|
|
|
|
ldx [%g2 + %lo(kern_locked_tte_data)], %g2
|
|
|
|
sethi %hi(0x400000), %g1
|
|
|
|
add %g2, %g1, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x30]
|
|
|
|
|
|
|
|
mov 14, %g2
|
|
|
|
BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
|
|
|
|
|
|
|
|
mov 62, %g2
|
|
|
|
1:
|
|
|
|
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x38]
|
|
|
|
sethi %hi(p1275buf), %g2
|
|
|
|
or %g2, %lo(p1275buf), %g2
|
|
|
|
ldx [%g2 + 0x08], %o1
|
|
|
|
call %o1
|
|
|
|
add %sp, (2047 + 128), %o0
|
|
|
|
|
|
|
|
do_unlock:
|
|
|
|
sethi %hi(prom_entry_lock), %g2
|
|
|
|
stb %g0, [%g2 + %lo(prom_entry_lock)]
|
|
|
|
membar #StoreStore | #StoreLoad
|
|
|
|
|
2006-02-09 11:52:44 +01:00
|
|
|
ba,pt %xcc, after_lock_tlb
|
|
|
|
nop
|
|
|
|
|
|
|
|
niagara_lock_tlb:
|
2006-02-10 07:57:21 +01:00
|
|
|
mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
|
|
|
|
sethi %hi(KERNBASE), %o0
|
|
|
|
clr %o1
|
|
|
|
sethi %hi(kern_locked_tte_data), %o2
|
|
|
|
ldx [%o2 + %lo(kern_locked_tte_data)], %o2
|
|
|
|
mov HV_MMU_IMMU, %o3
|
2006-02-09 11:52:44 +01:00
|
|
|
ta HV_FAST_TRAP
|
|
|
|
|
2006-02-10 07:57:21 +01:00
|
|
|
mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
|
|
|
|
sethi %hi(KERNBASE), %o0
|
|
|
|
clr %o1
|
|
|
|
sethi %hi(kern_locked_tte_data), %o2
|
|
|
|
ldx [%o2 + %lo(kern_locked_tte_data)], %o2
|
|
|
|
mov HV_MMU_DMMU, %o3
|
2006-02-09 11:52:44 +01:00
|
|
|
ta HV_FAST_TRAP
|
|
|
|
|
|
|
|
sethi %hi(bigkernel), %g2
|
|
|
|
lduw [%g2 + %lo(bigkernel)], %g2
|
|
|
|
brz,pt %g2, after_lock_tlb
|
|
|
|
nop
|
|
|
|
|
2006-02-10 07:57:21 +01:00
|
|
|
mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
|
|
|
|
sethi %hi(KERNBASE + 0x400000), %o0
|
|
|
|
clr %o1
|
|
|
|
sethi %hi(kern_locked_tte_data), %o2
|
|
|
|
ldx [%o2 + %lo(kern_locked_tte_data)], %o2
|
|
|
|
sethi %hi(0x400000), %o3
|
|
|
|
add %o2, %o3, %o2
|
|
|
|
mov HV_MMU_IMMU, %o3
|
2006-02-09 11:52:44 +01:00
|
|
|
ta HV_FAST_TRAP
|
|
|
|
|
2006-02-10 07:57:21 +01:00
|
|
|
mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
|
|
|
|
sethi %hi(KERNBASE + 0x400000), %o0
|
|
|
|
clr %o1
|
|
|
|
sethi %hi(kern_locked_tte_data), %o2
|
|
|
|
ldx [%o2 + %lo(kern_locked_tte_data)], %o2
|
|
|
|
sethi %hi(0x400000), %o3
|
|
|
|
add %o2, %o3, %o2
|
|
|
|
mov HV_MMU_DMMU, %o3
|
2006-02-09 11:52:44 +01:00
|
|
|
ta HV_FAST_TRAP
|
|
|
|
|
|
|
|
after_lock_tlb:
|
2005-04-17 00:20:36 +02:00
|
|
|
wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
|
|
|
|
wr %g0, 0, %fprs
|
|
|
|
|
|
|
|
wr %g0, ASI_P, %asi
|
|
|
|
|
|
|
|
mov PRIMARY_CONTEXT, %g7
|
2006-02-08 07:13:05 +01:00
|
|
|
|
|
|
|
661: stxa %g0, [%g7] ASI_DMMU
|
|
|
|
.section .sun4v_1insn_patch, "ax"
|
|
|
|
.word 661b
|
|
|
|
stxa %g0, [%g7] ASI_MMU
|
|
|
|
.previous
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
membar #Sync
|
|
|
|
mov SECONDARY_CONTEXT, %g7
|
2006-02-08 07:13:05 +01:00
|
|
|
|
|
|
|
661: stxa %g0, [%g7] ASI_DMMU
|
|
|
|
.section .sun4v_1insn_patch, "ax"
|
|
|
|
.word 661b
|
|
|
|
stxa %g0, [%g7] ASI_MMU
|
|
|
|
.previous
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
membar #Sync
|
|
|
|
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 10:29:17 +01:00
|
|
|
/* Everything we do here, until we properly take over the
|
|
|
|
* trap table, must be done with extreme care. We cannot
|
|
|
|
* make any references to %g6 (current thread pointer),
|
|
|
|
* %g4 (current task pointer), or %g5 (base of current cpu's
|
|
|
|
* per-cpu area) until we properly take over the trap table
|
|
|
|
* from the firmware and hypervisor.
|
|
|
|
*
|
|
|
|
* Get onto temporary stack which is in the locked kernel image.
|
|
|
|
*/
|
|
|
|
sethi %hi(tramp_stack), %g1
|
|
|
|
or %g1, %lo(tramp_stack), %g1
|
|
|
|
add %g1, TRAMP_STACK_SIZE, %g1
|
2007-09-16 20:51:15 +02:00
|
|
|
sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp
|
2005-04-17 00:20:36 +02:00
|
|
|
mov 0, %fp
|
|
|
|
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 10:29:17 +01:00
|
|
|
/* Put garbage in these registers to trap any access to them. */
|
|
|
|
set 0xdeadbeef, %g4
|
|
|
|
set 0xdeadbeef, %g5
|
|
|
|
set 0xdeadbeef, %g6
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
call init_irqwork_curcpu
|
|
|
|
nop
|
2006-02-08 09:08:23 +01:00
|
|
|
|
|
|
|
sethi %hi(tlb_type), %g3
|
|
|
|
lduw [%g3 + %lo(tlb_type)], %g2
|
|
|
|
cmp %g2, 3
|
|
|
|
bne,pt %icc, 1f
|
|
|
|
nop
|
|
|
|
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 10:29:17 +01:00
|
|
|
call hard_smp_processor_id
|
|
|
|
nop
|
|
|
|
|
2007-08-09 02:32:33 +02:00
|
|
|
call sun4v_register_mondo_queues
|
|
|
|
nop
|
2006-02-08 09:08:23 +01:00
|
|
|
|
|
|
|
1: call init_cur_cpu_trap
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 10:29:17 +01:00
|
|
|
ldx [%l0], %o0
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-10-05 00:23:20 +02:00
|
|
|
/* Start using proper page size encodings in ctx register. */
|
2006-02-08 07:13:05 +01:00
|
|
|
sethi %hi(sparc64_kern_pri_context), %g3
|
|
|
|
ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
|
|
|
|
mov PRIMARY_CONTEXT, %g1
|
|
|
|
|
|
|
|
661: stxa %g2, [%g1] ASI_DMMU
|
|
|
|
.section .sun4v_1insn_patch, "ax"
|
|
|
|
.word 661b
|
|
|
|
stxa %g2, [%g1] ASI_MMU
|
|
|
|
.previous
|
|
|
|
|
|
|
|
membar #Sync
|
2005-04-17 00:20:36 +02:00
|
|
|
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 10:29:17 +01:00
|
|
|
wrpr %g0, 0, %wstate
|
|
|
|
|
|
|
|
/* As a hack, put &init_thread_union into %g6.
|
|
|
|
* prom_world() loads from here to restore the %asi
|
|
|
|
* register.
|
|
|
|
*/
|
|
|
|
sethi %hi(init_thread_union), %g6
|
|
|
|
or %g6, %lo(init_thread_union), %g6
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-02-11 00:39:51 +01:00
|
|
|
sethi %hi(is_sun4v), %o0
|
|
|
|
lduw [%o0 + %lo(is_sun4v)], %o0
|
|
|
|
brz,pt %o0, 1f
|
|
|
|
nop
|
|
|
|
|
|
|
|
TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
|
|
|
|
add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
|
|
|
|
stxa %g2, [%g0] ASI_SCRATCHPAD
|
|
|
|
|
|
|
|
/* Compute physical address:
|
|
|
|
*
|
|
|
|
* paddr = kern_base + (mmfsa_vaddr - KERNBASE)
|
|
|
|
*/
|
|
|
|
sethi %hi(KERNBASE), %g3
|
|
|
|
sub %g2, %g3, %g2
|
|
|
|
sethi %hi(kern_base), %g3
|
|
|
|
ldx [%g3 + %lo(kern_base)], %g3
|
|
|
|
add %g2, %g3, %o1
|
2007-09-16 20:51:15 +02:00
|
|
|
sethi %hi(sparc64_ttable_tl0), %o0
|
2006-02-11 00:39:51 +01:00
|
|
|
|
2007-09-16 20:51:15 +02:00
|
|
|
set prom_set_trap_table_name, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x00]
|
|
|
|
mov 2, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x08]
|
|
|
|
mov 0, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x10]
|
|
|
|
stx %o0, [%sp + 2047 + 128 + 0x18]
|
|
|
|
stx %o1, [%sp + 2047 + 128 + 0x20]
|
|
|
|
sethi %hi(p1275buf), %g2
|
|
|
|
or %g2, %lo(p1275buf), %g2
|
|
|
|
ldx [%g2 + 0x08], %o1
|
|
|
|
call %o1
|
|
|
|
add %sp, (2047 + 128), %o0
|
2006-02-11 00:39:51 +01:00
|
|
|
|
|
|
|
ba,pt %xcc, 2f
|
|
|
|
nop
|
|
|
|
|
2007-09-16 20:51:15 +02:00
|
|
|
1: sethi %hi(sparc64_ttable_tl0), %o0
|
|
|
|
set prom_set_trap_table_name, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x00]
|
|
|
|
mov 1, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x08]
|
|
|
|
mov 0, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x10]
|
|
|
|
stx %o0, [%sp + 2047 + 128 + 0x18]
|
|
|
|
sethi %hi(p1275buf), %g2
|
|
|
|
or %g2, %lo(p1275buf), %g2
|
|
|
|
ldx [%g2 + 0x08], %o1
|
|
|
|
call %o1
|
|
|
|
add %sp, (2047 + 128), %o0
|
2005-04-17 00:20:36 +02:00
|
|
|
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 10:29:17 +01:00
|
|
|
2: ldx [%l0], %g6
|
|
|
|
ldx [%g6 + TI_TASK], %g4
|
|
|
|
|
|
|
|
mov 1, %g5
|
|
|
|
sllx %g5, THREAD_SHIFT, %g5
|
|
|
|
sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
|
|
|
|
add %g6, %g5, %sp
|
|
|
|
mov 0, %fp
|
|
|
|
|
|
|
|
rdpr %pstate, %o1
|
|
|
|
or %o1, PSTATE_IE, %o1
|
|
|
|
wrpr %o1, 0, %pstate
|
|
|
|
|
|
|
|
call smp_callin
|
2005-04-17 00:20:36 +02:00
|
|
|
nop
|
|
|
|
call cpu_idle
|
|
|
|
mov 0, %o0
|
|
|
|
call cpu_panic
|
|
|
|
nop
|
|
|
|
1: b,a,pt %xcc, 1b
|
|
|
|
|
|
|
|
.align 8
|
|
|
|
sparc64_cpu_startup_end:
|