2005-04-17 00:20:36 +02:00
|
|
|
#ifndef __ASM_CPU_SH3_DMA_H
|
|
|
|
#define __ASM_CPU_SH3_DMA_H
|
|
|
|
|
2007-12-26 03:45:06 +01:00
|
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
2009-03-10 09:26:49 +01:00
|
|
|
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
|
|
|
defined(CONFIG_CPU_SUBTYPE_SH7710) || \
|
|
|
|
defined(CONFIG_CPU_SUBTYPE_SH7712)
|
|
|
|
#define SH_DMAC_BASE0 0xa4010020
|
|
|
|
#else /* SH7705/06/07/09 */
|
|
|
|
#define SH_DMAC_BASE0 0xa4000020
|
2008-05-06 12:36:27 +02:00
|
|
|
#endif
|
2007-08-20 01:59:33 +02:00
|
|
|
|
|
|
|
#define DMTE0_IRQ 48
|
|
|
|
#define DMTE4_IRQ 76
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-01-17 07:14:09 +01:00
|
|
|
/* Definitions for the SuperH DMAC */
|
|
|
|
#define TM_BURST 0x00000020
|
|
|
|
#define TS_8 0x00000000
|
|
|
|
#define TS_16 0x00000008
|
|
|
|
#define TS_32 0x00000010
|
|
|
|
#define TS_128 0x00000018
|
|
|
|
|
|
|
|
#define CHCR_TS_MASK 0x18
|
|
|
|
#define CHCR_TS_SHIFT 3
|
|
|
|
|
|
|
|
#define DMAOR_INIT DMAOR_DME
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-01-17 07:14:09 +01:00
|
|
|
/*
|
|
|
|
* The SuperH DMAC supports a number of transmit sizes, we list them here,
|
|
|
|
* with their respective values as they appear in the CHCR registers.
|
|
|
|
*/
|
|
|
|
enum {
|
|
|
|
XMIT_SZ_8BIT,
|
|
|
|
XMIT_SZ_16BIT,
|
|
|
|
XMIT_SZ_32BIT,
|
|
|
|
XMIT_SZ_128BIT,
|
|
|
|
};
|
|
|
|
|
2007-05-09 11:35:28 +02:00
|
|
|
static unsigned int ts_shift[] __maybe_unused = {
|
2006-01-17 07:14:09 +01:00
|
|
|
[XMIT_SZ_8BIT] = 0,
|
|
|
|
[XMIT_SZ_16BIT] = 1,
|
|
|
|
[XMIT_SZ_32BIT] = 2,
|
|
|
|
[XMIT_SZ_128BIT] = 4,
|
|
|
|
};
|
|
|
|
|
|
|
|
#endif /* __ASM_CPU_SH3_DMA_H */
|