2005-04-17 00:20:36 +02:00
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/*
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* PCI Bus Services, see include/linux/pci.h for further explanation.
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*
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* Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
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* David Mosberger-Tang
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*
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* Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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2007-04-26 09:12:06 +02:00
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#include <linux/pm.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 09:04:11 +01:00
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#include <linux/slab.h>
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2005-04-17 00:20:36 +02:00
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#include <linux/module.h>
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#include <linux/spinlock.h>
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2005-10-31 00:03:48 +01:00
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#include <linux/string.h>
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2007-08-13 14:53:14 +02:00
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#include <linux/log2.h>
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PCI: add PCI Express ASPM support
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.
This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
-default, BIOS default setting
-powersave, highest power saving mode, enable all available ASPM
state and clock power management
-performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.
In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.
Note: some devices might not work well with aspm, either because chipset
issue or device issue. The patch provide API (pci_disable_link_state),
driver can disable ASPM for specific device.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2008-02-25 02:46:41 +01:00
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#include <linux/pci-aspm.h>
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2008-07-10 02:16:44 +02:00
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#include <linux/pm_wakeup.h>
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2008-10-21 11:38:25 +02:00
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#include <linux/interrupt.h>
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2009-03-16 09:13:39 +01:00
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#include <linux/device.h>
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2010-02-17 23:44:09 +01:00
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#include <linux/pm_runtime.h>
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2012-04-30 23:21:02 +02:00
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#include <asm-generic/pci-bridge.h>
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2009-03-16 09:13:39 +01:00
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#include <asm/setup.h>
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2005-04-08 07:53:31 +02:00
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#include "pci.h"
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2005-04-17 00:20:36 +02:00
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2009-04-27 19:33:16 +02:00
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const char *pci_power_names[] = {
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"error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
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};
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EXPORT_SYMBOL_GPL(pci_power_names);
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2010-01-02 22:57:24 +01:00
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int isa_dma_bridge_buggy;
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EXPORT_SYMBOL(isa_dma_bridge_buggy);
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int pci_pci_problems;
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EXPORT_SYMBOL(pci_pci_problems);
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2009-12-31 12:15:54 +01:00
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unsigned int pci_pm_d3_delay;
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2010-10-04 20:22:29 +02:00
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static void pci_pme_list_scan(struct work_struct *work);
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static LIST_HEAD(pci_pme_list);
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static DEFINE_MUTEX(pci_pme_list_mutex);
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static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
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struct pci_pme_device {
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struct list_head list;
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struct pci_dev *dev;
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};
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#define PME_TIMEOUT 1000 /* How long between PME checks */
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2009-12-31 12:15:54 +01:00
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static void pci_dev_d3_sleep(struct pci_dev *dev)
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{
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unsigned int delay = dev->d3_delay;
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if (delay < pci_pm_d3_delay)
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delay = pci_pm_d3_delay;
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msleep(delay);
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}
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2005-04-17 00:20:36 +02:00
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2007-10-11 22:57:27 +02:00
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#ifdef CONFIG_PCI_DOMAINS
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int pci_domains_supported = 1;
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#endif
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2007-02-06 01:36:06 +01:00
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#define DEFAULT_CARDBUS_IO_SIZE (256)
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#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
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/* pci=cbmemsize=nnM,cbiosize=nn can override this */
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unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
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unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
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2009-09-09 23:09:24 +02:00
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#define DEFAULT_HOTPLUG_IO_SIZE (256)
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#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
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/* pci=hpmemsize=nnM,hpiosize=nn can override this */
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unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
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unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
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2011-10-03 16:50:20 +02:00
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
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PCI: Set PCI-E Max Payload Size on fabric
On a given PCI-E fabric, each device, bridge, and root port can have a
different PCI-E maximum payload size. There is a sizable performance
boost for having the largest possible maximum payload size on each PCI-E
device. However, if improperly configured, fatal bus errors can occur.
Thus, it is important to ensure that PCI-E payloads sends by a device
are never larger than the MPS setting of all devices on the way to the
destination.
This can be achieved two ways:
- A conservative approach is to use the smallest common denominator of
the entire tree below a root complex for every device on that fabric.
This means for example that having a 128 bytes MPS USB controller on one
leg of a switch will dramatically reduce performances of a video card or
10GE adapter on another leg of that same switch.
It also means that any hierarchy supporting hotplug slots (including
expresscard or thunderbolt I suppose, dbl check that) will have to be
entirely clamped to 128 bytes since we cannot predict what will be
plugged into those slots, and we cannot change the MPS on a "live"
system.
- A more optimal way is possible, if it falls within a couple of
constraints:
* The top-level host bridge will never generate packets larger than the
smallest TLP (or if it can be controlled independently from its MPS at
least)
* The device will never generate packets larger than MPS (which can be
configured via MRRS)
* No support of direct PCI-E <-> PCI-E transfers between devices without
some additional code to specifically deal with that case
Then we can use an approach that basically ignores downstream requests
and focuses exclusively on upstream requests. In that case, all we need
to care about is that a device MPS is no larger than its parent MPS,
which allows us to keep all switches/bridges to the max MPS supported by
their parent and eventually the PHB.
In this case, your USB controller would no longer "starve" your 10GE
Ethernet and your hotplug slots won't affect your global MPS.
Additionally, the hotplugged devices themselves can be configured to a
larger MPS up to the value configured in the hotplug bridge.
To choose between the two available options, two PCI kernel boot args
have been added to the PCI calls. "pcie_bus_safe" will provide the
former behavior, while "pcie_bus_perf" will perform the latter behavior.
By default, the latter behavior is used.
NOTE: due to the location of the enablement, each arch will need to add
calls to this function. This patch only enables x86.
This patch includes a number of changes recommended by Benjamin
Herrenschmidt.
Tested-by: Jordan_Hargrave@dell.com
Signed-off-by: Jon Mason <mason@myri.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-20 22:20:54 +02:00
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2009-10-26 21:20:44 +01:00
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/*
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* The default CLS is used if arch didn't set CLS explicitly and not
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* all pci devices agree on the same value. Arch can override either
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* the dfl or actual value as it sees fit. Don't forget this is
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* measured in 32-bit words, not bytes.
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*/
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2009-10-08 11:59:53 +02:00
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u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
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2009-10-26 21:20:44 +01:00
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u8 pci_cache_line_size;
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2011-10-28 23:48:38 +02:00
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/*
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* If we set up a device for bus mastering, we need to check the latency
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* timer as certain BIOSes forget to set it properly.
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*/
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unsigned int pcibios_max_latency = 255;
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2012-03-01 00:06:33 +01:00
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/* If set, the PCIe ARI capability will not be used. */
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static bool pcie_ari_disabled;
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2005-04-17 00:20:36 +02:00
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/**
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* pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
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* @bus: pointer to PCI bus structure to search
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*
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* Given a PCI bus, returns the highest PCI bus number present in the set
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* including the given PCI bus and its list of child PCI buses.
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*/
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2007-03-27 07:53:30 +02:00
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unsigned char pci_bus_max_busnr(struct pci_bus* bus)
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2005-04-17 00:20:36 +02:00
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{
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struct list_head *tmp;
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unsigned char max, n;
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2012-05-18 03:51:11 +02:00
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max = bus->busn_res.end;
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2005-04-17 00:20:36 +02:00
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list_for_each(tmp, &bus->children) {
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n = pci_bus_max_busnr(pci_bus_b(tmp));
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if(n > max)
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max = n;
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}
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return max;
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}
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2006-01-18 01:56:56 +01:00
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EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
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2005-04-17 00:20:36 +02:00
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2008-12-01 23:30:30 +01:00
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#ifdef CONFIG_HAS_IOMEM
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void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
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{
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/*
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* Make sure the BAR is actually a memory resource, not an IO resource
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*/
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if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
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WARN_ON(1);
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return NULL;
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}
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return ioremap_nocache(pci_resource_start(pdev, bar),
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pci_resource_len(pdev, bar));
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}
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EXPORT_SYMBOL_GPL(pci_ioremap_bar);
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#endif
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2006-11-22 08:26:18 +01:00
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#define PCI_FIND_CAP_TTL 48
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static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
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u8 pos, int cap, int *ttl)
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[PATCH] PCI: add pci_find_next_capability()
Some devices have more than one capability of the same type. For
example, the PCI header for the PathScale InfiniPath looks like:
04:01.0 InfiniBand: Unknown device 1fc1:000d (rev 02)
Subsystem: Unknown device 1fc1:000d
Flags: bus master, fast devsel, latency 0, IRQ 193
Memory at fea00000 (64-bit, non-prefetchable) [size=2M]
Capabilities: [c0] HyperTransport: Slave or Primary Interface
Capabilities: [f8] HyperTransport: Interrupt Discovery and Configuration
There are _two_ HyperTransport capabilities, and the PathScale driver
wants to look at both of them.
The current pci_find_capability() API doesn't work for this, since it
only allows us to get to the first capability of a given type. The
patch below introduces a new pci_find_next_capability(), which can be
used in a loop like
for (pos = pci_find_capability(pdev, <ID>);
pos;
pos = pci_find_next_capability(pdev, pos, <ID>)) {
/* ... */
}
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Matthew Wilcox <matthew@wil.cx>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2005-10-29 02:35:34 +02:00
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{
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u8 id;
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2006-11-22 08:26:18 +01:00
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while ((*ttl)--) {
|
[PATCH] PCI: add pci_find_next_capability()
Some devices have more than one capability of the same type. For
example, the PCI header for the PathScale InfiniPath looks like:
04:01.0 InfiniBand: Unknown device 1fc1:000d (rev 02)
Subsystem: Unknown device 1fc1:000d
Flags: bus master, fast devsel, latency 0, IRQ 193
Memory at fea00000 (64-bit, non-prefetchable) [size=2M]
Capabilities: [c0] HyperTransport: Slave or Primary Interface
Capabilities: [f8] HyperTransport: Interrupt Discovery and Configuration
There are _two_ HyperTransport capabilities, and the PathScale driver
wants to look at both of them.
The current pci_find_capability() API doesn't work for this, since it
only allows us to get to the first capability of a given type. The
patch below introduces a new pci_find_next_capability(), which can be
used in a loop like
for (pos = pci_find_capability(pdev, <ID>);
pos;
pos = pci_find_next_capability(pdev, pos, <ID>)) {
/* ... */
}
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Matthew Wilcox <matthew@wil.cx>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2005-10-29 02:35:34 +02:00
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pci_bus_read_config_byte(bus, devfn, pos, &pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
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&id);
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if (id == 0xff)
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break;
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if (id == cap)
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|
|
return pos;
|
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|
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pos += PCI_CAP_LIST_NEXT;
|
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|
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}
|
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|
return 0;
|
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|
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}
|
|
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|
|
2006-11-22 08:26:18 +01:00
|
|
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static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
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|
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u8 pos, int cap)
|
|
|
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{
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int ttl = PCI_FIND_CAP_TTL;
|
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|
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|
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return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
|
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}
|
|
|
|
|
[PATCH] PCI: add pci_find_next_capability()
Some devices have more than one capability of the same type. For
example, the PCI header for the PathScale InfiniPath looks like:
04:01.0 InfiniBand: Unknown device 1fc1:000d (rev 02)
Subsystem: Unknown device 1fc1:000d
Flags: bus master, fast devsel, latency 0, IRQ 193
Memory at fea00000 (64-bit, non-prefetchable) [size=2M]
Capabilities: [c0] HyperTransport: Slave or Primary Interface
Capabilities: [f8] HyperTransport: Interrupt Discovery and Configuration
There are _two_ HyperTransport capabilities, and the PathScale driver
wants to look at both of them.
The current pci_find_capability() API doesn't work for this, since it
only allows us to get to the first capability of a given type. The
patch below introduces a new pci_find_next_capability(), which can be
used in a loop like
for (pos = pci_find_capability(pdev, <ID>);
pos;
pos = pci_find_next_capability(pdev, pos, <ID>)) {
/* ... */
}
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Matthew Wilcox <matthew@wil.cx>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2005-10-29 02:35:34 +02:00
|
|
|
int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
|
|
|
|
{
|
|
|
|
return __pci_find_next_cap(dev->bus, dev->devfn,
|
|
|
|
pos + PCI_CAP_LIST_NEXT, cap);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_find_next_capability);
|
|
|
|
|
2006-11-22 08:26:16 +01:00
|
|
|
static int __pci_bus_find_cap_start(struct pci_bus *bus,
|
|
|
|
unsigned int devfn, u8 hdr_type)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
u16 status;
|
|
|
|
|
|
|
|
pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
|
|
|
|
if (!(status & PCI_STATUS_CAP_LIST))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
switch (hdr_type) {
|
|
|
|
case PCI_HEADER_TYPE_NORMAL:
|
|
|
|
case PCI_HEADER_TYPE_BRIDGE:
|
2006-11-22 08:26:16 +01:00
|
|
|
return PCI_CAPABILITY_LIST;
|
2005-04-17 00:20:36 +02:00
|
|
|
case PCI_HEADER_TYPE_CARDBUS:
|
2006-11-22 08:26:16 +01:00
|
|
|
return PCI_CB_CAPABILITY_LIST;
|
2005-04-17 00:20:36 +02:00
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
2006-11-22 08:26:16 +01:00
|
|
|
|
|
|
|
return 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_find_capability - query for devices' capabilities
|
|
|
|
* @dev: PCI device to query
|
|
|
|
* @cap: capability code
|
|
|
|
*
|
|
|
|
* Tell if a device supports a given PCI capability.
|
|
|
|
* Returns the address of the requested capability structure within the
|
|
|
|
* device's PCI configuration space or 0 in case the device does not
|
|
|
|
* support it. Possible values for @cap:
|
|
|
|
*
|
|
|
|
* %PCI_CAP_ID_PM Power Management
|
|
|
|
* %PCI_CAP_ID_AGP Accelerated Graphics Port
|
|
|
|
* %PCI_CAP_ID_VPD Vital Product Data
|
|
|
|
* %PCI_CAP_ID_SLOTID Slot Identification
|
|
|
|
* %PCI_CAP_ID_MSI Message Signalled Interrupts
|
|
|
|
* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
|
|
|
|
* %PCI_CAP_ID_PCIX PCI-X
|
|
|
|
* %PCI_CAP_ID_EXP PCI Express
|
|
|
|
*/
|
|
|
|
int pci_find_capability(struct pci_dev *dev, int cap)
|
|
|
|
{
|
2006-11-22 08:26:16 +01:00
|
|
|
int pos;
|
|
|
|
|
|
|
|
pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
|
|
|
|
if (pos)
|
|
|
|
pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
|
|
|
|
|
|
|
|
return pos;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_bus_find_capability - query for devices' capabilities
|
|
|
|
* @bus: the PCI bus to query
|
|
|
|
* @devfn: PCI device to query
|
|
|
|
* @cap: capability code
|
|
|
|
*
|
|
|
|
* Like pci_find_capability() but works for pci devices that do not have a
|
|
|
|
* pci_dev structure set up yet.
|
|
|
|
*
|
|
|
|
* Returns the address of the requested capability structure within the
|
|
|
|
* device's PCI configuration space or 0 in case the device does not
|
|
|
|
* support it.
|
|
|
|
*/
|
|
|
|
int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
|
|
|
|
{
|
2006-11-22 08:26:16 +01:00
|
|
|
int pos;
|
2005-04-17 00:20:36 +02:00
|
|
|
u8 hdr_type;
|
|
|
|
|
|
|
|
pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
|
|
|
|
|
2006-11-22 08:26:16 +01:00
|
|
|
pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
|
|
|
|
if (pos)
|
|
|
|
pos = __pci_find_next_cap(bus, devfn, pos, cap);
|
|
|
|
|
|
|
|
return pos;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2012-06-01 23:16:37 +02:00
|
|
|
/**
|
|
|
|
* pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure
|
|
|
|
* @dev: PCI device to check
|
|
|
|
*
|
|
|
|
* Like pci_pcie_cap() but also checks that the PCIe capability version is
|
|
|
|
* >= 2. Note that v1 capability structures could be sparse in that not
|
|
|
|
* all register fields were required. v2 requires the entire structure to
|
|
|
|
* be present size wise, while still allowing for non-implemented registers
|
|
|
|
* to exist but they must be hardwired to 0.
|
|
|
|
*
|
|
|
|
* Due to the differences in the versions of capability structures, one
|
|
|
|
* must be careful not to try and access non-existant registers that may
|
|
|
|
* exist in early versions - v1 - of Express devices.
|
|
|
|
*
|
|
|
|
* Returns the offset of the PCIe capability structure as long as the
|
|
|
|
* capability version is >= 2; otherwise 0 is returned.
|
|
|
|
*/
|
|
|
|
static int pci_pcie_cap2(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
u16 flags;
|
|
|
|
int pos;
|
|
|
|
|
|
|
|
pos = pci_pcie_cap(dev);
|
|
|
|
if (pos) {
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
|
|
|
|
if ((flags & PCI_EXP_FLAGS_VERS) < 2)
|
|
|
|
pos = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return pos;
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pci_find_ext_capability - Find an extended capability
|
|
|
|
* @dev: PCI device to query
|
|
|
|
* @cap: capability code
|
|
|
|
*
|
|
|
|
* Returns the address of the requested extended capability structure
|
|
|
|
* within the device's PCI configuration space or 0 if the device does
|
|
|
|
* not support it. Possible values for @cap:
|
|
|
|
*
|
|
|
|
* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
|
|
|
|
* %PCI_EXT_CAP_ID_VC Virtual Channel
|
|
|
|
* %PCI_EXT_CAP_ID_DSN Device Serial Number
|
|
|
|
* %PCI_EXT_CAP_ID_PWR Power Budgeting
|
|
|
|
*/
|
|
|
|
int pci_find_ext_capability(struct pci_dev *dev, int cap)
|
|
|
|
{
|
|
|
|
u32 header;
|
2008-10-13 13:18:07 +02:00
|
|
|
int ttl;
|
|
|
|
int pos = PCI_CFG_SPACE_SIZE;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-10-13 13:18:07 +02:00
|
|
|
/* minimum 8 bytes per capability */
|
|
|
|
ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
|
|
|
|
|
|
|
|
if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
|
2005-04-17 00:20:36 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we have no capabilities, this is indicated by cap ID,
|
|
|
|
* cap version and next pointer all being 0.
|
|
|
|
*/
|
|
|
|
if (header == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
while (ttl-- > 0) {
|
|
|
|
if (PCI_EXT_CAP_ID(header) == cap)
|
|
|
|
return pos;
|
|
|
|
|
|
|
|
pos = PCI_EXT_CAP_NEXT(header);
|
2008-10-13 13:18:07 +02:00
|
|
|
if (pos < PCI_CFG_SPACE_SIZE)
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2006-05-23 12:10:01 +02:00
|
|
|
EXPORT_SYMBOL_GPL(pci_find_ext_capability);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2006-11-22 08:26:18 +01:00
|
|
|
static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
|
|
|
|
{
|
|
|
|
int rc, ttl = PCI_FIND_CAP_TTL;
|
|
|
|
u8 cap, mask;
|
|
|
|
|
|
|
|
if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
|
|
|
|
mask = HT_3BIT_CAP_MASK;
|
|
|
|
else
|
|
|
|
mask = HT_5BIT_CAP_MASK;
|
|
|
|
|
|
|
|
pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
|
|
|
|
PCI_CAP_ID_HT, &ttl);
|
|
|
|
while (pos) {
|
|
|
|
rc = pci_read_config_byte(dev, pos + 3, &cap);
|
|
|
|
if (rc != PCIBIOS_SUCCESSFUL)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if ((cap & mask) == ht_cap)
|
|
|
|
return pos;
|
|
|
|
|
2007-01-11 08:15:29 +01:00
|
|
|
pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
|
|
|
|
pos + PCI_CAP_LIST_NEXT,
|
2006-11-22 08:26:18 +01:00
|
|
|
PCI_CAP_ID_HT, &ttl);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
/**
|
|
|
|
* pci_find_next_ht_capability - query a device's Hypertransport capabilities
|
|
|
|
* @dev: PCI device to query
|
|
|
|
* @pos: Position from which to continue searching
|
|
|
|
* @ht_cap: Hypertransport capability code
|
|
|
|
*
|
|
|
|
* To be used in conjunction with pci_find_ht_capability() to search for
|
|
|
|
* all capabilities matching @ht_cap. @pos should always be a value returned
|
|
|
|
* from pci_find_ht_capability().
|
|
|
|
*
|
|
|
|
* NB. To be 100% safe against broken PCI devices, the caller should take
|
|
|
|
* steps to avoid an infinite loop.
|
|
|
|
*/
|
|
|
|
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
|
|
|
|
{
|
|
|
|
return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_find_ht_capability - query a device's Hypertransport capabilities
|
|
|
|
* @dev: PCI device to query
|
|
|
|
* @ht_cap: Hypertransport capability code
|
|
|
|
*
|
|
|
|
* Tell if a device supports a given Hypertransport capability.
|
|
|
|
* Returns an address within the device's PCI configuration space
|
|
|
|
* or 0 in case the device does not support the request capability.
|
|
|
|
* The address points to the PCI capability, of type PCI_CAP_ID_HT,
|
|
|
|
* which has a Hypertransport capability matching @ht_cap.
|
|
|
|
*/
|
|
|
|
int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
|
|
|
|
pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
|
|
|
|
if (pos)
|
|
|
|
pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
|
|
|
|
|
|
|
|
return pos;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_find_ht_capability);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pci_find_parent_resource - return resource region of parent bus of given region
|
|
|
|
* @dev: PCI device structure contains resources to be searched
|
|
|
|
* @res: child resource record for which parent is sought
|
|
|
|
*
|
|
|
|
* For given resource region of given device, return the resource
|
|
|
|
* region of parent bus the given region is contained in or where
|
|
|
|
* it should be allocated from.
|
|
|
|
*/
|
|
|
|
struct resource *
|
|
|
|
pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
|
|
|
|
{
|
|
|
|
const struct pci_bus *bus = dev->bus;
|
|
|
|
int i;
|
2010-02-23 18:24:31 +01:00
|
|
|
struct resource *best = NULL, *r;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2010-02-23 18:24:31 +01:00
|
|
|
pci_bus_for_each_resource(bus, r, i) {
|
2005-04-17 00:20:36 +02:00
|
|
|
if (!r)
|
|
|
|
continue;
|
|
|
|
if (res->start && !(res->start >= r->start && res->end <= r->end))
|
|
|
|
continue; /* Not contained */
|
|
|
|
if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
|
|
|
|
continue; /* Wrong type */
|
|
|
|
if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
|
|
|
|
return r; /* Exact match */
|
PCI: allow matching of prefetchable resources to non-prefetchable windows
I'm not entirely sure it needs to go into 32, but it's probably the right
thing to do. Another way of explaining the patch is:
- we currently pick the _first_ exactly matching bus resource entry, but
the _last_ inexactly matching one. Normally first/last shouldn't
matter, but bus resource entries aren't actually all created equal: in
a transparent bus, the last resources will be the parent resources,
which we should generally try to avoid unless we have no choice. So
"first matching" is the thing we should always aim for.
- the patch is a bit bigger than it needs to be, because I simplified the
logic at the same time. It used to be a fairly incomprehensible
if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
best = r; /* Approximating prefetchable by non-prefetchable */
and technically, all the patch did was to make that complex choice be
even more complex (it basically added a "&& !best" to say that if we
already gound a non-prefetchable window for the prefetchable resource,
then we won't override an earlier one with that later one: remember
"first matching").
- So instead of that complex one with three separate conditionals in one,
I split it up a bit, and am taking advantage of the fact that we
already handled the exact case, so if 'res->flags' has the PREFETCH
bit, then we already know that 'r->flags' will _not_ have it. So the
simplified code drops the redundant test, and does the new '!best' test
separately. It also uses 'continue' as a way to ignore the bus
resource we know doesn't work (ie a prefetchable bus resource is _not_
acceptable for anything but an exact match), so it turns into:
/* We can't insert a non-prefetch resource inside a prefetchable parent .. */
if (r->flags & IORESOURCE_PREFETCH)
continue;
/* .. but we can put a prefetchable resource inside a non-prefetchable one */
if (!best)
best = r;
instead. With the comments, it's now six lines instead of two, but it's
conceptually simpler, and I _could_ have written it as two lines:
if ((res->flags & IORESOURCE_PREFETCH) && !best)
best = r; /* Approximating prefetchable by non-prefetchable */
but I thought that was too damn subtle.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-11-09 21:04:32 +01:00
|
|
|
/* We can't insert a non-prefetch resource inside a prefetchable parent .. */
|
|
|
|
if (r->flags & IORESOURCE_PREFETCH)
|
|
|
|
continue;
|
|
|
|
/* .. but we can put a prefetchable resource inside a non-prefetchable one */
|
|
|
|
if (!best)
|
|
|
|
best = r;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
return best;
|
|
|
|
}
|
|
|
|
|
2005-07-27 16:19:44 +02:00
|
|
|
/**
|
|
|
|
* pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
|
|
|
|
* @dev: PCI device to have its BARs restored
|
|
|
|
*
|
|
|
|
* Restore the BAR values for a given device, so as to make it
|
|
|
|
* accessible by its driver.
|
|
|
|
*/
|
2007-10-27 03:06:22 +02:00
|
|
|
static void
|
2005-07-27 16:19:44 +02:00
|
|
|
pci_restore_bars(struct pci_dev *dev)
|
|
|
|
{
|
2008-11-21 19:40:00 +01:00
|
|
|
int i;
|
2005-07-27 16:19:44 +02:00
|
|
|
|
2008-11-21 19:40:00 +01:00
|
|
|
for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
|
2008-11-21 19:38:52 +01:00
|
|
|
pci_update_resource(dev, i);
|
2005-07-27 16:19:44 +02:00
|
|
|
}
|
|
|
|
|
2008-07-07 03:32:02 +02:00
|
|
|
static struct pci_platform_pm_ops *pci_platform_pm;
|
|
|
|
|
|
|
|
int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
|
|
|
|
{
|
2008-07-07 03:34:48 +02:00
|
|
|
if (!ops->is_manageable || !ops->set_state || !ops->choose_state
|
|
|
|
|| !ops->sleep_wake || !ops->can_wakeup)
|
2008-07-07 03:32:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
pci_platform_pm = ops;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool platform_pci_power_manageable(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int platform_pci_set_power_state(struct pci_dev *dev,
|
|
|
|
pci_power_t t)
|
|
|
|
{
|
|
|
|
return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return pci_platform_pm ?
|
|
|
|
pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
|
|
|
|
}
|
2005-10-23 20:57:38 +02:00
|
|
|
|
2008-07-07 03:34:48 +02:00
|
|
|
static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
|
|
|
|
{
|
|
|
|
return pci_platform_pm ?
|
|
|
|
pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
|
|
|
|
}
|
|
|
|
|
2010-02-17 23:44:09 +01:00
|
|
|
static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
|
|
|
|
{
|
|
|
|
return pci_platform_pm ?
|
|
|
|
pci_platform_pm->run_wake(dev, enable) : -ENODEV;
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
2008-07-07 03:32:52 +02:00
|
|
|
* pci_raw_set_power_state - Use PCI PM registers to set the power state of
|
|
|
|
* given PCI device
|
|
|
|
* @dev: PCI device to handle.
|
|
|
|
* @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
|
2005-04-17 00:20:36 +02:00
|
|
|
*
|
2008-07-07 03:32:52 +02:00
|
|
|
* RETURN VALUE:
|
|
|
|
* -EINVAL if the requested state is invalid.
|
|
|
|
* -EIO if device does not support PCI PM or its PM capabilities register has a
|
|
|
|
* wrong version, or device doesn't support the requested state.
|
|
|
|
* 0 if device already is in the requested state.
|
|
|
|
* 0 if device's power state has been successfully changed.
|
2005-04-17 00:20:36 +02:00
|
|
|
*/
|
2009-03-16 22:40:08 +01:00
|
|
|
static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2008-07-07 03:36:24 +02:00
|
|
|
u16 pmcsr;
|
2008-07-07 03:32:52 +02:00
|
|
|
bool need_restore = false;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-03-16 22:40:36 +01:00
|
|
|
/* Check if we're already there */
|
|
|
|
if (dev->current_state == state)
|
|
|
|
return 0;
|
|
|
|
|
2008-07-07 03:36:24 +02:00
|
|
|
if (!dev->pm_cap)
|
2007-07-09 20:55:58 +02:00
|
|
|
return -EIO;
|
|
|
|
|
2008-07-07 03:32:52 +02:00
|
|
|
if (state < PCI_D0 || state > PCI_D3hot)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/* Validate current state:
|
|
|
|
* Can enter D0 from any state, but if we can only go deeper
|
|
|
|
* to sleep if we're already in a low power state
|
|
|
|
*/
|
2009-03-16 22:40:36 +01:00
|
|
|
if (state != PCI_D0 && dev->current_state <= PCI_D3cold
|
2008-07-07 03:32:52 +02:00
|
|
|
&& dev->current_state > state) {
|
2008-06-13 18:52:11 +02:00
|
|
|
dev_err(&dev->dev, "invalid power transition "
|
|
|
|
"(from state %d to %d)\n", dev->current_state, state);
|
2005-04-17 00:20:36 +02:00
|
|
|
return -EINVAL;
|
2008-07-07 03:32:52 +02:00
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* check if this device supports the desired state */
|
2008-07-07 03:36:24 +02:00
|
|
|
if ((state == PCI_D1 && !dev->d1_support)
|
|
|
|
|| (state == PCI_D2 && !dev->d2_support))
|
2005-08-18 00:32:19 +02:00
|
|
|
return -EIO;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-07-07 03:36:24 +02:00
|
|
|
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
|
2005-07-27 16:19:44 +02:00
|
|
|
|
2005-09-14 15:52:42 +02:00
|
|
|
/* If we're (effectively) in D3, force entire word to 0.
|
2005-04-17 00:20:36 +02:00
|
|
|
* This doesn't affect PME_Status, disables PME_En, and
|
|
|
|
* sets PowerState to 0.
|
|
|
|
*/
|
2005-09-14 15:52:42 +02:00
|
|
|
switch (dev->current_state) {
|
2005-09-28 23:50:51 +02:00
|
|
|
case PCI_D0:
|
|
|
|
case PCI_D1:
|
|
|
|
case PCI_D2:
|
|
|
|
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
|
|
|
|
pmcsr |= state;
|
|
|
|
break;
|
2009-05-18 22:51:12 +02:00
|
|
|
case PCI_D3hot:
|
|
|
|
case PCI_D3cold:
|
2005-09-14 15:52:42 +02:00
|
|
|
case PCI_UNKNOWN: /* Boot-up */
|
|
|
|
if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
|
2009-03-16 22:40:08 +01:00
|
|
|
&& !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
|
2008-07-07 03:32:52 +02:00
|
|
|
need_restore = true;
|
2005-09-14 15:52:42 +02:00
|
|
|
/* Fall-through: force to D0 */
|
|
|
|
default:
|
2005-09-28 23:50:51 +02:00
|
|
|
pmcsr = 0;
|
2005-09-14 15:52:42 +02:00
|
|
|
break;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* enter specified state */
|
2008-07-07 03:36:24 +02:00
|
|
|
pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* Mandatory power management transition delays */
|
|
|
|
/* see PCI PM 1.1 5.6.1 table 18 */
|
|
|
|
if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
|
2009-12-31 12:15:54 +01:00
|
|
|
pci_dev_d3_sleep(dev);
|
2005-04-17 00:20:36 +02:00
|
|
|
else if (state == PCI_D2 || dev->current_state == PCI_D2)
|
2009-01-16 21:54:43 +01:00
|
|
|
udelay(PCI_PM_D2_DELAY);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-10-05 00:48:40 +02:00
|
|
|
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
|
|
|
|
dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
|
|
|
|
if (dev->current_state != state && printk_ratelimit())
|
|
|
|
dev_info(&dev->dev, "Refused to change power state, "
|
|
|
|
"currently in D%d\n", dev->current_state);
|
2005-07-27 16:19:44 +02:00
|
|
|
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
/*
|
|
|
|
* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
|
2005-07-27 16:19:44 +02:00
|
|
|
* INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
|
|
|
|
* from D3hot to D0 _may_ perform an internal reset, thereby
|
|
|
|
* going to "D0 Uninitialized" rather than "D0 Initialized".
|
|
|
|
* For example, at least some versions of the 3c905B and the
|
|
|
|
* 3c556B exhibit this behaviour.
|
|
|
|
*
|
|
|
|
* At least some laptop BIOSen (e.g. the Thinkpad T21) leave
|
|
|
|
* devices in a D3hot state at boot. Consequently, we need to
|
|
|
|
* restore at least the BARs so that the device will be
|
|
|
|
* accessible to its driver.
|
|
|
|
*/
|
|
|
|
if (need_restore)
|
|
|
|
pci_restore_bars(dev);
|
|
|
|
|
2009-03-16 22:40:08 +01:00
|
|
|
if (dev->bus->self)
|
PCI: add PCI Express ASPM support
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.
This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
-default, BIOS default setting
-powersave, highest power saving mode, enable all available ASPM
state and clock power management
-performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.
In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.
Note: some devices might not work well with aspm, either because chipset
issue or device issue. The patch provide API (pci_disable_link_state),
driver can disable ASPM for specific device.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2008-02-25 02:46:41 +01:00
|
|
|
pcie_aspm_pm_state_change(dev->bus->self);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-07-07 03:32:52 +02:00
|
|
|
/**
|
|
|
|
* pci_update_current_state - Read PCI power state of given device from its
|
|
|
|
* PCI PM registers and cache it
|
|
|
|
* @dev: PCI device to handle.
|
2008-12-27 16:30:52 +01:00
|
|
|
* @state: State to cache in case the device doesn't have the PM capability
|
2008-07-07 03:32:52 +02:00
|
|
|
*/
|
PCI PM: Avoid touching devices behind bridges in unknown state
It generally is better to avoid accessing devices behind bridges that
may not be in the D0 power state, because in that case the bridges'
secondary buses may not be accessible. For this reason, during the
early phase of resume (ie. with interrupts disabled), before
restoring the standard config registers of a device, check the power
state of the bridge the device is behind and postpone the restoration
of the device's config space, as well as any other operations that
would involve accessing the device, if that state is not D0.
In such cases the restoration of the device's config space will be
retried during the "normal" phase of resume (ie. with interrupts
enabled), so that the bridge can be put into D0 before that happens.
Also, save standard configuration registers of PCI devices during the
"normal" phase of suspend (ie. with interrupts enabled), so that the
bridges the devices are behind can be put into low power states (we
don't put bridges into low power states at the moment, but we may
want to do it in the future and it seems reasonable to design for
that).
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-01-07 13:07:15 +01:00
|
|
|
void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
|
2008-07-07 03:32:52 +02:00
|
|
|
{
|
2008-07-07 03:36:24 +02:00
|
|
|
if (dev->pm_cap) {
|
2008-07-07 03:32:52 +02:00
|
|
|
u16 pmcsr;
|
|
|
|
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
/*
|
|
|
|
* Configuration space is not accessible for device in
|
|
|
|
* D3cold, so just keep or set D3cold for safety
|
|
|
|
*/
|
|
|
|
if (dev->current_state == PCI_D3cold)
|
|
|
|
return;
|
|
|
|
if (state == PCI_D3cold) {
|
|
|
|
dev->current_state = PCI_D3cold;
|
|
|
|
return;
|
|
|
|
}
|
2008-07-07 03:36:24 +02:00
|
|
|
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
|
2008-07-07 03:32:52 +02:00
|
|
|
dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
|
2008-12-27 16:30:52 +01:00
|
|
|
} else {
|
|
|
|
dev->current_state = state;
|
2008-07-07 03:32:52 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
PCI / PM: restore the original behavior of pci_set_power_state()
Commit cc2893b6 (PCI: Ensure we re-enable devices on resume)
addressed the problem with USB not being powered after resume on
recent Lenovo machines, but it did that in a suboptimal way.
Namely, it should have changed the relevant code paths only,
which are pci_pm_resume_noirq() and pci_pm_restore_noirq() supposed
to restore the device's power and standard configuration registers
after system resume from suspend or hibernation. Instead, however,
it modified pci_set_power_state() which is executed in several
other situations too. That resulted in some undesirable effects,
like attempting to change a device's power state in the same way
multiple times in a row (up to as many as 4 times in a row in the
snd_hda_intel driver).
Fix the bug addressed by commit cc2893b6 in an alternative way,
by forcibly powering up all devices in pci_pm_default_resume_early(),
which is called by pci_pm_resume_noirq() and pci_pm_restore_noirq()
to restore the device's power and standard configuration registers,
and modifying pci_pm_runtime_resume() to avoid the forcible power-up
if not necessary. Then, revert the changes made by commit cc2893b6
to make the confusion introduced by it go away.
Acked-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-05 23:20:00 +02:00
|
|
|
/**
|
|
|
|
* pci_power_up - Put the given device into D0 forcibly
|
|
|
|
* @dev: PCI device to power up
|
|
|
|
*/
|
|
|
|
void pci_power_up(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
if (platform_pci_power_manageable(dev))
|
|
|
|
platform_pci_set_power_state(dev, PCI_D0);
|
|
|
|
|
|
|
|
pci_raw_set_power_state(dev, PCI_D0);
|
|
|
|
pci_update_current_state(dev, PCI_D0);
|
|
|
|
}
|
|
|
|
|
2009-03-26 22:51:40 +01:00
|
|
|
/**
|
|
|
|
* pci_platform_power_transition - Use platform to change device power state
|
|
|
|
* @dev: PCI device to handle.
|
|
|
|
* @state: State to put the device into.
|
|
|
|
*/
|
|
|
|
static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
|
|
|
|
{
|
|
|
|
int error;
|
|
|
|
|
|
|
|
if (platform_pci_power_manageable(dev)) {
|
|
|
|
error = platform_pci_set_power_state(dev, state);
|
|
|
|
if (!error)
|
|
|
|
pci_update_current_state(dev, state);
|
PCI: Set device power state to PCI_D0 for device without native PM support
During test of one IB card with guest VM, found that, msi is not
initialized properly.
It turns out __write_msi_msg will do nothing if device current_state is
not PCI_D0. And, that pci device does not have pm_cap in guest VM.
There is an error in setting of power state to PCI_D0 in
pci_enable_device(), but error is not returned for this. Following is
code flow:
pci_enable_device() --> __pci_enable_device_flags() -->
do_pci_enable_device() --> pci_set_power_state() -->
__pci_start_power_transition()
We have following condition inside __pci_start_power_transition():
if (platform_pci_power_manageable(dev)) {
error = platform_pci_set_power_state(dev, state);
if (!error)
pci_update_current_state(dev, state);
} else {
error = -ENODEV;
/* Fall back to PCI_D0 if native PM is not supported */
if (!dev->pm_cap)
dev->current_state = PCI_D0;
}
Here, from platform_pci_set_power_state(), acpi_pci_set_power_state() is
getting called and that is failing with ENODEV because of following
condition:
if (!handle || ACPI_SUCCESS(acpi_get_handle(handle, "_EJ0",&tmp)))
return -ENODEV;
Because of that, pci_update_current_state() is not getting called.
With this patch, if device power state can not be set via
platform_pci_set_power_state and that device does not have native pm
support, then PCI device power state will be set to PCI_D0.
-v2: This also reverts 47e9037ac16637cd7f12b8790ea7ce6680e42168, as it's
not needed after this change.
Acked-by: "Rafael J. Wysocki" <rjw@sisk.pl>
Signed-off-by: Ajaykumar Hotchandani<ajaykumar.hotchandani@oracle.com>
Signed-off-by: Yinghai Lu<yinghai.lu@oracle.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-12-12 09:27:36 +01:00
|
|
|
/* Fall back to PCI_D0 if native PM is not supported */
|
|
|
|
if (!dev->pm_cap)
|
|
|
|
dev->current_state = PCI_D0;
|
2009-03-26 22:51:40 +01:00
|
|
|
} else {
|
|
|
|
error = -ENODEV;
|
|
|
|
/* Fall back to PCI_D0 if native PM is not supported */
|
PCI PM: Fix initialization and kexec breakage for some devices
Recent PCI PM changes introduced a bug that causes some devices to be
mishandled after kexec and during early initialization. The failure
scenario in the kexec case is the following:
* Assume a PCI device is not power-manageable by the platform and has
PCI_PM_CTRL_NO_SOFT_RESET set in PMCSR.
* The device is put into D3 before kexec (using the native PCI PM).
* After kexec, pci_setup_device() sets the device's power state to
PCI_UNKNOWN.
* pci_set_power_state(dev, PCI_D0) is called by the device's driver.
* __pci_start_power_transition(dev, PCI_D0) is called and since the
device is not power-manageable by the platform, it causes
pci_update_current_state(dev, PCI_D0) to be called. As a result
the device's current_state field is updated to PCI_D3, in
accordance with the contents of its PCI PM registers.
* pci_raw_set_power_state() is called and it changes the device power
state to D0. *However*, it should also call pci_restore_bars() to
reinitialize the device, but it doesn't, because the device's
current_state field has been modified earlier.
To prevent this from happening, modify pci_platform_power_transition()
so that it doesn't use pci_update_current_state() to update the
current_state field for devices that aren't power-manageable by the
platform. Instead, this field should be updated directly for devices
that don't support the native PCI PM.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-05-17 20:17:06 +02:00
|
|
|
if (!dev->pm_cap)
|
|
|
|
dev->current_state = PCI_D0;
|
2009-03-26 22:51:40 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* __pci_start_power_transition - Start power transition of a PCI device
|
|
|
|
* @dev: PCI device to handle.
|
|
|
|
* @state: State to put the device into.
|
|
|
|
*/
|
|
|
|
static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
|
|
|
|
{
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
if (state == PCI_D0) {
|
2009-03-26 22:51:40 +01:00
|
|
|
pci_platform_power_transition(dev, PCI_D0);
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
/*
|
|
|
|
* Mandatory power management transition delays, see
|
|
|
|
* PCI Express Base Specification Revision 2.0 Section
|
|
|
|
* 6.6.1: Conventional Reset. Do not delay for
|
|
|
|
* devices powered on/off by corresponding bridge,
|
|
|
|
* because have already delayed for the bridge.
|
|
|
|
*/
|
|
|
|
if (dev->runtime_d3cold) {
|
|
|
|
msleep(dev->d3cold_delay);
|
|
|
|
/*
|
|
|
|
* When powering on a bridge from D3cold, the
|
|
|
|
* whole hierarchy may be powered on into
|
|
|
|
* D0uninitialized state, resume them to give
|
|
|
|
* them a chance to suspend again
|
|
|
|
*/
|
|
|
|
pci_wakeup_bus(dev->subordinate);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* __pci_dev_set_current_state - Set current state of a PCI device
|
|
|
|
* @dev: Device to handle
|
|
|
|
* @data: pointer to state to be set
|
|
|
|
*/
|
|
|
|
static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
|
|
|
|
{
|
|
|
|
pci_power_t state = *(pci_power_t *)data;
|
|
|
|
|
|
|
|
dev->current_state = state;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* __pci_bus_set_current_state - Walk given bus and set current state of devices
|
|
|
|
* @bus: Top bus of the subtree to walk.
|
|
|
|
* @state: state to be set
|
|
|
|
*/
|
|
|
|
static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
|
|
|
|
{
|
|
|
|
if (bus)
|
|
|
|
pci_walk_bus(bus, __pci_dev_set_current_state, &state);
|
2009-03-26 22:51:40 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* __pci_complete_power_transition - Complete power transition of a PCI device
|
|
|
|
* @dev: PCI device to handle.
|
|
|
|
* @state: State to put the device into.
|
|
|
|
*
|
|
|
|
* This function should not be called directly by device drivers.
|
|
|
|
*/
|
|
|
|
int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
|
|
|
|
{
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
int ret;
|
|
|
|
|
PCI / PM: restore the original behavior of pci_set_power_state()
Commit cc2893b6 (PCI: Ensure we re-enable devices on resume)
addressed the problem with USB not being powered after resume on
recent Lenovo machines, but it did that in a suboptimal way.
Namely, it should have changed the relevant code paths only,
which are pci_pm_resume_noirq() and pci_pm_restore_noirq() supposed
to restore the device's power and standard configuration registers
after system resume from suspend or hibernation. Instead, however,
it modified pci_set_power_state() which is executed in several
other situations too. That resulted in some undesirable effects,
like attempting to change a device's power state in the same way
multiple times in a row (up to as many as 4 times in a row in the
snd_hda_intel driver).
Fix the bug addressed by commit cc2893b6 in an alternative way,
by forcibly powering up all devices in pci_pm_default_resume_early(),
which is called by pci_pm_resume_noirq() and pci_pm_restore_noirq()
to restore the device's power and standard configuration registers,
and modifying pci_pm_runtime_resume() to avoid the forcible power-up
if not necessary. Then, revert the changes made by commit cc2893b6
to make the confusion introduced by it go away.
Acked-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-05 23:20:00 +02:00
|
|
|
if (state <= PCI_D0)
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
return -EINVAL;
|
|
|
|
ret = pci_platform_power_transition(dev, state);
|
|
|
|
/* Power off the bridge may power off the whole hierarchy */
|
|
|
|
if (!ret && state == PCI_D3cold)
|
|
|
|
__pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
|
|
|
|
return ret;
|
2009-03-26 22:51:40 +01:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
|
|
|
|
|
2008-07-07 03:32:52 +02:00
|
|
|
/**
|
|
|
|
* pci_set_power_state - Set the power state of a PCI device
|
|
|
|
* @dev: PCI device to handle.
|
|
|
|
* @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
|
|
|
|
*
|
2009-01-26 11:06:57 +01:00
|
|
|
* Transition a device to a new power state, using the platform firmware and/or
|
2008-07-07 03:32:52 +02:00
|
|
|
* the device's PCI PM registers.
|
|
|
|
*
|
|
|
|
* RETURN VALUE:
|
|
|
|
* -EINVAL if the requested state is invalid.
|
|
|
|
* -EIO if device does not support PCI PM or its PM capabilities register has a
|
|
|
|
* wrong version, or device doesn't support the requested state.
|
|
|
|
* 0 if device already is in the requested state.
|
|
|
|
* 0 if device's power state has been successfully changed.
|
|
|
|
*/
|
|
|
|
int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
|
|
|
|
{
|
2008-07-07 03:36:24 +02:00
|
|
|
int error;
|
2008-07-07 03:32:52 +02:00
|
|
|
|
|
|
|
/* bound the state we're entering */
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
if (state > PCI_D3cold)
|
|
|
|
state = PCI_D3cold;
|
2008-07-07 03:32:52 +02:00
|
|
|
else if (state < PCI_D0)
|
|
|
|
state = PCI_D0;
|
|
|
|
else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
|
|
|
|
/*
|
|
|
|
* If the device or the parent bridge do not support PCI PM,
|
|
|
|
* ignore the request if we're doing anything other than putting
|
|
|
|
* it into D0 (which would only happen on boot).
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
|
PCI / PM: restore the original behavior of pci_set_power_state()
Commit cc2893b6 (PCI: Ensure we re-enable devices on resume)
addressed the problem with USB not being powered after resume on
recent Lenovo machines, but it did that in a suboptimal way.
Namely, it should have changed the relevant code paths only,
which are pci_pm_resume_noirq() and pci_pm_restore_noirq() supposed
to restore the device's power and standard configuration registers
after system resume from suspend or hibernation. Instead, however,
it modified pci_set_power_state() which is executed in several
other situations too. That resulted in some undesirable effects,
like attempting to change a device's power state in the same way
multiple times in a row (up to as many as 4 times in a row in the
snd_hda_intel driver).
Fix the bug addressed by commit cc2893b6 in an alternative way,
by forcibly powering up all devices in pci_pm_default_resume_early(),
which is called by pci_pm_resume_noirq() and pci_pm_restore_noirq()
to restore the device's power and standard configuration registers,
and modifying pci_pm_runtime_resume() to avoid the forcible power-up
if not necessary. Then, revert the changes made by commit cc2893b6
to make the confusion introduced by it go away.
Acked-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-05 23:20:00 +02:00
|
|
|
/* Check if we're already there */
|
|
|
|
if (dev->current_state == state)
|
|
|
|
return 0;
|
|
|
|
|
2009-03-26 22:51:40 +01:00
|
|
|
__pci_start_power_transition(dev, state);
|
|
|
|
|
2008-07-24 18:18:38 +02:00
|
|
|
/* This device is quirked not to be put into D3, so
|
|
|
|
don't put it in D3 */
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
|
2008-07-24 18:18:38 +02:00
|
|
|
return 0;
|
2008-07-07 03:32:52 +02:00
|
|
|
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
/*
|
|
|
|
* To put device in D3cold, we put device into D3hot in native
|
|
|
|
* way, then put device into D3cold with platform ops
|
|
|
|
*/
|
|
|
|
error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
|
|
|
|
PCI_D3hot : state);
|
2008-07-07 03:32:52 +02:00
|
|
|
|
2009-03-26 22:51:40 +01:00
|
|
|
if (!__pci_complete_power_transition(dev, state))
|
|
|
|
error = 0;
|
2011-03-21 04:29:08 +01:00
|
|
|
/*
|
|
|
|
* When aspm_policy is "powersave" this call ensures
|
|
|
|
* that ASPM is configured.
|
|
|
|
*/
|
|
|
|
if (!error && dev->bus->self)
|
|
|
|
pcie_aspm_powersave_config_link(dev->bus->self);
|
2008-07-07 03:32:52 +02:00
|
|
|
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pci_choose_state - Choose the power state of a PCI device
|
|
|
|
* @dev: PCI device to be suspended
|
|
|
|
* @state: target sleep state for the whole system. This is the value
|
|
|
|
* that is passed to suspend() function.
|
|
|
|
*
|
|
|
|
* Returns PCI power state suitable for given device and given system
|
|
|
|
* message.
|
|
|
|
*/
|
|
|
|
|
|
|
|
pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
|
|
|
|
{
|
2007-07-20 04:03:22 +02:00
|
|
|
pci_power_t ret;
|
2005-03-19 06:15:48 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
if (!pci_find_capability(dev, PCI_CAP_ID_PM))
|
|
|
|
return PCI_D0;
|
|
|
|
|
2008-07-07 03:32:02 +02:00
|
|
|
ret = platform_pci_choose_state(dev);
|
|
|
|
if (ret != PCI_POWER_ERROR)
|
|
|
|
return ret;
|
2005-09-04 00:56:57 +02:00
|
|
|
|
|
|
|
switch (state.event) {
|
|
|
|
case PM_EVENT_ON:
|
|
|
|
return PCI_D0;
|
|
|
|
case PM_EVENT_FREEZE:
|
2006-08-15 08:11:05 +02:00
|
|
|
case PM_EVENT_PRETHAW:
|
|
|
|
/* REVISIT both freeze and pre-thaw "should" use D0 */
|
2005-09-04 00:56:57 +02:00
|
|
|
case PM_EVENT_SUSPEND:
|
2008-02-23 19:13:25 +01:00
|
|
|
case PM_EVENT_HIBERNATE:
|
2005-09-04 00:56:57 +02:00
|
|
|
return PCI_D3hot;
|
2005-04-17 00:20:36 +02:00
|
|
|
default:
|
2008-06-13 18:52:11 +02:00
|
|
|
dev_info(&dev->dev, "unrecognized suspend event %d\n",
|
|
|
|
state.event);
|
2005-04-17 00:20:36 +02:00
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
return PCI_D0;
|
|
|
|
}
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(pci_choose_state);
|
|
|
|
|
2009-02-15 19:55:47 +01:00
|
|
|
#define PCI_EXP_SAVE_REGS 7
|
|
|
|
|
2009-04-09 08:57:39 +02:00
|
|
|
#define pcie_cap_has_devctl(type, flags) 1
|
|
|
|
#define pcie_cap_has_lnkctl(type, flags) \
|
|
|
|
((flags & PCI_EXP_FLAGS_VERS) > 1 || \
|
|
|
|
(type == PCI_EXP_TYPE_ROOT_PORT || \
|
|
|
|
type == PCI_EXP_TYPE_ENDPOINT || \
|
|
|
|
type == PCI_EXP_TYPE_LEG_END))
|
|
|
|
#define pcie_cap_has_sltctl(type, flags) \
|
|
|
|
((flags & PCI_EXP_FLAGS_VERS) > 1 || \
|
|
|
|
((type == PCI_EXP_TYPE_ROOT_PORT) || \
|
|
|
|
(type == PCI_EXP_TYPE_DOWNSTREAM && \
|
|
|
|
(flags & PCI_EXP_FLAGS_SLOT))))
|
|
|
|
#define pcie_cap_has_rtctl(type, flags) \
|
|
|
|
((flags & PCI_EXP_FLAGS_VERS) > 1 || \
|
|
|
|
(type == PCI_EXP_TYPE_ROOT_PORT || \
|
|
|
|
type == PCI_EXP_TYPE_RC_EC))
|
|
|
|
|
2012-02-11 09:18:41 +01:00
|
|
|
static struct pci_cap_saved_state *pci_find_saved_cap(
|
|
|
|
struct pci_dev *pci_dev, char cap)
|
|
|
|
{
|
|
|
|
struct pci_cap_saved_state *tmp;
|
|
|
|
struct hlist_node *pos;
|
|
|
|
|
|
|
|
hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
|
|
|
|
if (tmp->cap.cap_nr == cap)
|
|
|
|
return tmp;
|
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2006-08-21 15:22:22 +02:00
|
|
|
static int pci_save_pcie_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos, i = 0;
|
|
|
|
struct pci_cap_saved_state *save_state;
|
|
|
|
u16 *cap;
|
2009-04-09 08:57:39 +02:00
|
|
|
u16 flags;
|
2006-08-21 15:22:22 +02:00
|
|
|
|
2009-11-11 06:30:56 +01:00
|
|
|
pos = pci_pcie_cap(dev);
|
|
|
|
if (!pos)
|
2006-08-21 15:22:22 +02:00
|
|
|
return 0;
|
|
|
|
|
2007-03-08 21:06:13 +01:00
|
|
|
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
|
2006-08-21 15:22:22 +02:00
|
|
|
if (!save_state) {
|
2009-01-08 01:22:37 +01:00
|
|
|
dev_err(&dev->dev, "buffer not found in %s\n", __func__);
|
2006-08-21 15:22:22 +02:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2011-05-10 18:02:11 +02:00
|
|
|
cap = (u16 *)&save_state->cap.data[0];
|
2006-08-21 15:22:22 +02:00
|
|
|
|
2009-04-09 08:57:39 +02:00
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
|
|
|
|
|
|
|
|
if (pcie_cap_has_devctl(dev->pcie_type, flags))
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
|
|
|
|
if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
|
|
|
|
if (pcie_cap_has_sltctl(dev->pcie_type, flags))
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
|
|
|
|
if (pcie_cap_has_rtctl(dev->pcie_type, flags))
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
|
2008-12-07 22:02:58 +01:00
|
|
|
|
PCI: remove redundant capabilities checking in pci_{save, restore}_pcie_state
Unlike PCI Express v1's Capabilities Structure, v2's requires the entire
structure to be implemented. In v2 structures, register fields that
are not implemented are present but hardwired to 0x0. These may
include: Link Capabilities, Status, and Control; Slot Capabilities,
Status, and Control; Root Capabilities, Status, and Control; and all of
the '2' (Device, Link, and Slot) Capabilities, Status, and Control
registers.
This patch removes the redundant capability checks corresponding to the
Link 2's and Slot 2's, Capabilities, Status, and Control registers as they
will be present if Device Capabilities 2's registers are (which explains
why the macros for each of the three are identical).
Signed-off-by: Myron Stowe <myron.stowe@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-01 23:16:43 +02:00
|
|
|
pos = pci_pcie_cap2(dev);
|
|
|
|
if (!pos)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
|
2006-08-21 15:22:22 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_restore_pcie_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int i = 0, pos;
|
|
|
|
struct pci_cap_saved_state *save_state;
|
|
|
|
u16 *cap;
|
2009-04-09 08:57:39 +02:00
|
|
|
u16 flags;
|
2006-08-21 15:22:22 +02:00
|
|
|
|
|
|
|
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
|
|
|
if (!save_state || pos <= 0)
|
|
|
|
return;
|
2011-05-10 18:02:11 +02:00
|
|
|
cap = (u16 *)&save_state->cap.data[0];
|
2006-08-21 15:22:22 +02:00
|
|
|
|
2009-04-09 08:57:39 +02:00
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
|
|
|
|
|
|
|
|
if (pcie_cap_has_devctl(dev->pcie_type, flags))
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
|
|
|
|
if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
|
|
|
|
if (pcie_cap_has_sltctl(dev->pcie_type, flags))
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
|
|
|
|
if (pcie_cap_has_rtctl(dev->pcie_type, flags))
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
|
PCI: remove redundant capabilities checking in pci_{save, restore}_pcie_state
Unlike PCI Express v1's Capabilities Structure, v2's requires the entire
structure to be implemented. In v2 structures, register fields that
are not implemented are present but hardwired to 0x0. These may
include: Link Capabilities, Status, and Control; Slot Capabilities,
Status, and Control; Root Capabilities, Status, and Control; and all of
the '2' (Device, Link, and Slot) Capabilities, Status, and Control
registers.
This patch removes the redundant capability checks corresponding to the
Link 2's and Slot 2's, Capabilities, Status, and Control registers as they
will be present if Device Capabilities 2's registers are (which explains
why the macros for each of the three are identical).
Signed-off-by: Myron Stowe <myron.stowe@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-01 23:16:43 +02:00
|
|
|
|
|
|
|
pos = pci_pcie_cap2(dev);
|
|
|
|
if (!pos)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
|
2006-08-21 15:22:22 +02:00
|
|
|
}
|
|
|
|
|
2006-11-09 01:17:15 +01:00
|
|
|
|
|
|
|
static int pci_save_pcix_state(struct pci_dev *dev)
|
|
|
|
{
|
2008-12-07 22:02:58 +01:00
|
|
|
int pos;
|
2006-11-09 01:17:15 +01:00
|
|
|
struct pci_cap_saved_state *save_state;
|
|
|
|
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (pos <= 0)
|
|
|
|
return 0;
|
|
|
|
|
2007-12-18 02:56:47 +01:00
|
|
|
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
|
2006-11-09 01:17:15 +01:00
|
|
|
if (!save_state) {
|
2009-01-08 01:22:37 +01:00
|
|
|
dev_err(&dev->dev, "buffer not found in %s\n", __func__);
|
2006-11-09 01:17:15 +01:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2011-05-10 18:02:11 +02:00
|
|
|
pci_read_config_word(dev, pos + PCI_X_CMD,
|
|
|
|
(u16 *)save_state->cap.data);
|
2008-12-07 22:02:58 +01:00
|
|
|
|
2006-11-09 01:17:15 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_restore_pcix_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int i = 0, pos;
|
|
|
|
struct pci_cap_saved_state *save_state;
|
|
|
|
u16 *cap;
|
|
|
|
|
|
|
|
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (!save_state || pos <= 0)
|
|
|
|
return;
|
2011-05-10 18:02:11 +02:00
|
|
|
cap = (u16 *)&save_state->cap.data[0];
|
2006-11-09 01:17:15 +01:00
|
|
|
|
|
|
|
pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pci_save_state - save the PCI configuration space of a device before suspending
|
|
|
|
* @dev: - PCI device that we're dealing with
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
pci_save_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
/* XXX: 100% dword access ok here? */
|
|
|
|
for (i = 0; i < 16; i++)
|
2009-11-25 03:55:51 +01:00
|
|
|
pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
|
2009-01-16 21:54:43 +01:00
|
|
|
dev->state_saved = true;
|
2006-08-21 15:22:22 +02:00
|
|
|
if ((i = pci_save_pcie_state(dev)) != 0)
|
|
|
|
return i;
|
2006-11-09 01:17:15 +01:00
|
|
|
if ((i = pci_save_pcix_state(dev)) != 0)
|
|
|
|
return i;
|
2005-04-17 00:20:36 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
PCI: Fix regression in pci_restore_state(), v3
Commit 26f41062f28d ("PCI: check for pci bar restore completion and
retry") attempted to address problems with PCI BAR restoration on
systems where FLR had not been completed before pci_restore_state() was
called, but it did that in an utterly wrong way.
First off, instead of retrying the writes for the BAR registers only, it
did that for all of the PCI config space of the device, including the
status register (whose value after the write quite obviously need not be
the same as the written one). Second, it added arbitrary delay to
pci_restore_state() even for systems where the PCI config space
restoration was successful at first attempt. Finally, the mdelay(10) it
added to every iteration of the writing loop was way too much of a delay
for any reasonable device.
All of this actually caused resume failures for some devices on Mikko's
system.
To fix the regression, make pci_restore_state() only retry the writes
for BAR registers and only wait if the first read from the register
doesn't return the written value. Additionaly, make it wait for 1 ms,
instead of 10 ms, after every failing attempt to write into config
space.
Reported-by: Mikko Vinni <mmvinni@yahoo.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-04-15 21:40:40 +02:00
|
|
|
static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
|
|
|
|
u32 saved_val, int retry)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
pci_read_config_dword(pdev, offset, &val);
|
|
|
|
if (val == saved_val)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (;;) {
|
|
|
|
dev_dbg(&pdev->dev, "restoring config space at offset "
|
|
|
|
"%#x (was %#x, writing %#x)\n", offset, val, saved_val);
|
|
|
|
pci_write_config_dword(pdev, offset, saved_val);
|
|
|
|
if (retry-- <= 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pci_read_config_dword(pdev, offset, &val);
|
|
|
|
if (val == saved_val)
|
|
|
|
return;
|
|
|
|
|
|
|
|
mdelay(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-04-16 23:07:50 +02:00
|
|
|
static void pci_restore_config_space_range(struct pci_dev *pdev,
|
|
|
|
int start, int end, int retry)
|
PCI: Fix regression in pci_restore_state(), v3
Commit 26f41062f28d ("PCI: check for pci bar restore completion and
retry") attempted to address problems with PCI BAR restoration on
systems where FLR had not been completed before pci_restore_state() was
called, but it did that in an utterly wrong way.
First off, instead of retrying the writes for the BAR registers only, it
did that for all of the PCI config space of the device, including the
status register (whose value after the write quite obviously need not be
the same as the written one). Second, it added arbitrary delay to
pci_restore_state() even for systems where the PCI config space
restoration was successful at first attempt. Finally, the mdelay(10) it
added to every iteration of the writing loop was way too much of a delay
for any reasonable device.
All of this actually caused resume failures for some devices on Mikko's
system.
To fix the regression, make pci_restore_state() only retry the writes
for BAR registers and only wait if the first read from the register
doesn't return the written value. Additionaly, make it wait for 1 ms,
instead of 10 ms, after every failing attempt to write into config
space.
Reported-by: Mikko Vinni <mmvinni@yahoo.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-04-15 21:40:40 +02:00
|
|
|
{
|
|
|
|
int index;
|
|
|
|
|
|
|
|
for (index = end; index >= start; index--)
|
|
|
|
pci_restore_config_dword(pdev, 4 * index,
|
|
|
|
pdev->saved_config_space[index],
|
|
|
|
retry);
|
|
|
|
}
|
|
|
|
|
2012-04-16 23:07:50 +02:00
|
|
|
static void pci_restore_config_space(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
|
|
|
|
pci_restore_config_space_range(pdev, 10, 15, 0);
|
|
|
|
/* Restore BARs before the command register. */
|
|
|
|
pci_restore_config_space_range(pdev, 4, 9, 10);
|
|
|
|
pci_restore_config_space_range(pdev, 0, 3, 0);
|
|
|
|
} else {
|
|
|
|
pci_restore_config_space_range(pdev, 0, 15, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pci_restore_state - Restore the saved state of a PCI device
|
|
|
|
* @dev: - PCI device that we're dealing with
|
|
|
|
*/
|
2010-12-01 00:43:26 +01:00
|
|
|
void pci_restore_state(struct pci_dev *dev)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2009-08-08 02:46:19 +02:00
|
|
|
if (!dev->state_saved)
|
2010-12-01 00:43:26 +01:00
|
|
|
return;
|
2009-09-09 23:49:59 +02:00
|
|
|
|
2006-08-21 15:22:22 +02:00
|
|
|
/* PCI Express register must be restored first */
|
|
|
|
pci_restore_pcie_state(dev);
|
2011-12-17 14:24:40 +01:00
|
|
|
pci_restore_ats_state(dev);
|
2006-08-21 15:22:22 +02:00
|
|
|
|
2012-04-16 23:07:50 +02:00
|
|
|
pci_restore_config_space(dev);
|
PCI: Fix regression in pci_restore_state(), v3
Commit 26f41062f28d ("PCI: check for pci bar restore completion and
retry") attempted to address problems with PCI BAR restoration on
systems where FLR had not been completed before pci_restore_state() was
called, but it did that in an utterly wrong way.
First off, instead of retrying the writes for the BAR registers only, it
did that for all of the PCI config space of the device, including the
status register (whose value after the write quite obviously need not be
the same as the written one). Second, it added arbitrary delay to
pci_restore_state() even for systems where the PCI config space
restoration was successful at first attempt. Finally, the mdelay(10) it
added to every iteration of the writing loop was way too much of a delay
for any reasonable device.
All of this actually caused resume failures for some devices on Mikko's
system.
To fix the regression, make pci_restore_state() only retry the writes
for BAR registers and only wait if the first read from the register
doesn't return the written value. Additionaly, make it wait for 1 ms,
instead of 10 ms, after every failing attempt to write into config
space.
Reported-by: Mikko Vinni <mmvinni@yahoo.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-04-15 21:40:40 +02:00
|
|
|
|
2006-11-09 01:17:15 +01:00
|
|
|
pci_restore_pcix_state(dev);
|
2006-02-08 10:11:38 +01:00
|
|
|
pci_restore_msi_state(dev);
|
2009-03-20 04:25:12 +01:00
|
|
|
pci_restore_iov_state(dev);
|
2007-01-25 09:34:08 +01:00
|
|
|
|
2009-09-09 23:49:59 +02:00
|
|
|
dev->state_saved = false;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2011-05-10 18:02:27 +02:00
|
|
|
struct pci_saved_state {
|
|
|
|
u32 config_space[16];
|
|
|
|
struct pci_cap_saved_data cap[0];
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_store_saved_state - Allocate and return an opaque struct containing
|
|
|
|
* the device saved state.
|
|
|
|
* @dev: PCI device that we're dealing with
|
|
|
|
*
|
|
|
|
* Rerturn NULL if no state or error.
|
|
|
|
*/
|
|
|
|
struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct pci_saved_state *state;
|
|
|
|
struct pci_cap_saved_state *tmp;
|
|
|
|
struct pci_cap_saved_data *cap;
|
|
|
|
struct hlist_node *pos;
|
|
|
|
size_t size;
|
|
|
|
|
|
|
|
if (!dev->state_saved)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
|
|
|
|
|
|
|
|
hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
|
|
|
|
size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
|
|
|
|
|
|
|
|
state = kzalloc(size, GFP_KERNEL);
|
|
|
|
if (!state)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
memcpy(state->config_space, dev->saved_config_space,
|
|
|
|
sizeof(state->config_space));
|
|
|
|
|
|
|
|
cap = state->cap;
|
|
|
|
hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
|
|
|
|
size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
|
|
|
|
memcpy(cap, &tmp->cap, len);
|
|
|
|
cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
|
|
|
|
}
|
|
|
|
/* Empty cap_save terminates list */
|
|
|
|
|
|
|
|
return state;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_store_saved_state);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_load_saved_state - Reload the provided save state into struct pci_dev.
|
|
|
|
* @dev: PCI device that we're dealing with
|
|
|
|
* @state: Saved state returned from pci_store_saved_state()
|
|
|
|
*/
|
|
|
|
int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
|
|
|
|
{
|
|
|
|
struct pci_cap_saved_data *cap;
|
|
|
|
|
|
|
|
dev->state_saved = false;
|
|
|
|
|
|
|
|
if (!state)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
memcpy(dev->saved_config_space, state->config_space,
|
|
|
|
sizeof(state->config_space));
|
|
|
|
|
|
|
|
cap = state->cap;
|
|
|
|
while (cap->size) {
|
|
|
|
struct pci_cap_saved_state *tmp;
|
|
|
|
|
|
|
|
tmp = pci_find_saved_cap(dev, cap->cap_nr);
|
|
|
|
if (!tmp || tmp->cap.size != cap->size)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
memcpy(tmp->cap.data, cap->data, tmp->cap.size);
|
|
|
|
cap = (struct pci_cap_saved_data *)((u8 *)cap +
|
|
|
|
sizeof(struct pci_cap_saved_data) + cap->size);
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->state_saved = true;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_load_saved_state);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_load_and_free_saved_state - Reload the save state pointed to by state,
|
|
|
|
* and free the memory allocated for it.
|
|
|
|
* @dev: PCI device that we're dealing with
|
|
|
|
* @state: Pointer to saved state returned from pci_store_saved_state()
|
|
|
|
*/
|
|
|
|
int pci_load_and_free_saved_state(struct pci_dev *dev,
|
|
|
|
struct pci_saved_state **state)
|
|
|
|
{
|
|
|
|
int ret = pci_load_saved_state(dev, *state);
|
|
|
|
kfree(*state);
|
|
|
|
*state = NULL;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
|
|
|
|
|
2006-12-18 02:30:00 +01:00
|
|
|
static int do_pci_enable_device(struct pci_dev *dev, int bars)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = pci_set_power_state(dev, PCI_D0);
|
|
|
|
if (err < 0 && err != -EIO)
|
|
|
|
return err;
|
|
|
|
err = pcibios_enable_device(dev, bars);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
pci_fixup_device(pci_fixup_enable, dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2007-07-27 07:43:35 +02:00
|
|
|
* pci_reenable_device - Resume abandoned device
|
2006-12-18 02:30:00 +01:00
|
|
|
* @dev: PCI device to be resumed
|
|
|
|
*
|
|
|
|
* Note this function is a backend of pci_default_resume and is not supposed
|
|
|
|
* to be called by normal code, write proper resume handler and use it instead.
|
|
|
|
*/
|
2007-07-27 07:43:35 +02:00
|
|
|
int pci_reenable_device(struct pci_dev *dev)
|
2006-12-18 02:30:00 +01:00
|
|
|
{
|
2009-04-03 09:41:46 +02:00
|
|
|
if (pci_is_enabled(dev))
|
2006-12-18 02:30:00 +01:00
|
|
|
return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-12-20 05:28:08 +01:00
|
|
|
static int __pci_enable_device_flags(struct pci_dev *dev,
|
|
|
|
resource_size_t flags)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
int err;
|
2007-12-20 05:28:08 +01:00
|
|
|
int i, bars = 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2010-11-05 20:16:36 +01:00
|
|
|
/*
|
|
|
|
* Power state could be unknown at this point, either due to a fresh
|
|
|
|
* boot or a device removal call. So get the current power state
|
|
|
|
* so that things like MSI message writing will behave as expected
|
|
|
|
* (e.g. if the device really is in D0 at enable time).
|
|
|
|
*/
|
|
|
|
if (dev->pm_cap) {
|
|
|
|
u16 pmcsr;
|
|
|
|
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
|
|
|
|
dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
|
|
|
|
}
|
|
|
|
|
2006-12-18 02:28:43 +01:00
|
|
|
if (atomic_add_return(1, &dev->enable_cnt) > 1)
|
|
|
|
return 0; /* already enabled */
|
|
|
|
|
2011-12-18 03:33:37 +01:00
|
|
|
/* only skip sriov related */
|
|
|
|
for (i = 0; i <= PCI_ROM_RESOURCE; i++)
|
|
|
|
if (dev->resource[i].flags & flags)
|
|
|
|
bars |= (1 << i);
|
|
|
|
for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
|
2007-12-20 05:28:08 +01:00
|
|
|
if (dev->resource[i].flags & flags)
|
|
|
|
bars |= (1 << i);
|
|
|
|
|
2006-12-18 02:30:00 +01:00
|
|
|
err = do_pci_enable_device(dev, bars);
|
2005-07-28 20:37:33 +02:00
|
|
|
if (err < 0)
|
2006-12-18 02:30:00 +01:00
|
|
|
atomic_dec(&dev->enable_cnt);
|
2006-12-18 02:28:43 +01:00
|
|
|
return err;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2007-12-20 05:28:08 +01:00
|
|
|
/**
|
|
|
|
* pci_enable_device_io - Initialize a device for use with IO space
|
|
|
|
* @dev: PCI device to be initialized
|
|
|
|
*
|
|
|
|
* Initialize device before it's used by a driver. Ask low-level code
|
|
|
|
* to enable I/O resources. Wake up the device if it was suspended.
|
|
|
|
* Beware, this function can fail.
|
|
|
|
*/
|
|
|
|
int pci_enable_device_io(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return __pci_enable_device_flags(dev, IORESOURCE_IO);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_enable_device_mem - Initialize a device for use with Memory space
|
|
|
|
* @dev: PCI device to be initialized
|
|
|
|
*
|
|
|
|
* Initialize device before it's used by a driver. Ask low-level code
|
|
|
|
* to enable Memory resources. Wake up the device if it was suspended.
|
|
|
|
* Beware, this function can fail.
|
|
|
|
*/
|
|
|
|
int pci_enable_device_mem(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return __pci_enable_device_flags(dev, IORESOURCE_MEM);
|
|
|
|
}
|
|
|
|
|
PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-22 21:40:31 +01:00
|
|
|
/**
|
|
|
|
* pci_enable_device - Initialize device before it's used by a driver.
|
|
|
|
* @dev: PCI device to be initialized
|
|
|
|
*
|
|
|
|
* Initialize device before it's used by a driver. Ask low-level code
|
|
|
|
* to enable I/O and memory. Wake up the device if it was suspended.
|
|
|
|
* Beware, this function can fail.
|
|
|
|
*
|
|
|
|
* Note we don't actually enable the device many times if we call
|
|
|
|
* this function repeatedly (we just increment the count).
|
|
|
|
*/
|
|
|
|
int pci_enable_device(struct pci_dev *dev)
|
|
|
|
{
|
2007-12-20 05:28:08 +01:00
|
|
|
return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
|
PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-22 21:40:31 +01:00
|
|
|
}
|
|
|
|
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
/*
|
|
|
|
* Managed PCI resources. This manages device on/off, intx/msi/msix
|
|
|
|
* on/off and BAR regions. pci_dev itself records msi/msix status, so
|
|
|
|
* there's no need to track it separately. pci_devres is initialized
|
|
|
|
* when a device is enabled using managed PCI device enable interface.
|
|
|
|
*/
|
|
|
|
struct pci_devres {
|
2007-02-25 13:36:01 +01:00
|
|
|
unsigned int enabled:1;
|
|
|
|
unsigned int pinned:1;
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
unsigned int orig_intx:1;
|
|
|
|
unsigned int restore_intx:1;
|
|
|
|
u32 region_mask;
|
|
|
|
};
|
|
|
|
|
|
|
|
static void pcim_release(struct device *gendev, void *res)
|
|
|
|
{
|
|
|
|
struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
|
|
|
|
struct pci_devres *this = res;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (dev->msi_enabled)
|
|
|
|
pci_disable_msi(dev);
|
|
|
|
if (dev->msix_enabled)
|
|
|
|
pci_disable_msix(dev);
|
|
|
|
|
|
|
|
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
|
|
|
|
if (this->region_mask & (1 << i))
|
|
|
|
pci_release_region(dev, i);
|
|
|
|
|
|
|
|
if (this->restore_intx)
|
|
|
|
pci_intx(dev, this->orig_intx);
|
|
|
|
|
2007-02-25 13:36:01 +01:00
|
|
|
if (this->enabled && !this->pinned)
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
pci_disable_device(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pci_devres *dr, *new_dr;
|
|
|
|
|
|
|
|
dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
|
|
|
|
if (dr)
|
|
|
|
return dr;
|
|
|
|
|
|
|
|
new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
|
|
|
|
if (!new_dr)
|
|
|
|
return NULL;
|
|
|
|
return devres_get(&pdev->dev, new_dr, NULL, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
if (pci_is_managed(pdev))
|
|
|
|
return devres_find(&pdev->dev, pcim_release, NULL, NULL);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcim_enable_device - Managed pci_enable_device()
|
|
|
|
* @pdev: PCI device to be initialized
|
|
|
|
*
|
|
|
|
* Managed pci_enable_device().
|
|
|
|
*/
|
|
|
|
int pcim_enable_device(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pci_devres *dr;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
dr = get_pci_dr(pdev);
|
|
|
|
if (unlikely(!dr))
|
|
|
|
return -ENOMEM;
|
2008-01-30 10:20:04 +01:00
|
|
|
if (dr->enabled)
|
|
|
|
return 0;
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
|
|
|
|
rc = pci_enable_device(pdev);
|
|
|
|
if (!rc) {
|
|
|
|
pdev->is_managed = 1;
|
2007-02-25 13:36:01 +01:00
|
|
|
dr->enabled = 1;
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
}
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcim_pin_device - Pin managed PCI device
|
|
|
|
* @pdev: PCI device to pin
|
|
|
|
*
|
|
|
|
* Pin managed PCI device @pdev. Pinned device won't be disabled on
|
|
|
|
* driver detach. @pdev must have been enabled with
|
|
|
|
* pcim_enable_device().
|
|
|
|
*/
|
|
|
|
void pcim_pin_device(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pci_devres *dr;
|
|
|
|
|
|
|
|
dr = find_pci_dr(pdev);
|
2007-02-25 13:36:01 +01:00
|
|
|
WARN_ON(!dr || !dr->enabled);
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
if (dr)
|
2007-02-25 13:36:01 +01:00
|
|
|
dr->pinned = 1;
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pcibios_disable_device - disable arch specific PCI resources for device dev
|
|
|
|
* @dev: the PCI device to disable
|
|
|
|
*
|
|
|
|
* Disables architecture specific PCI resources for the device. This
|
|
|
|
* is the default implementation. Architecture implementations can
|
|
|
|
* override this.
|
|
|
|
*/
|
2012-06-19 14:54:49 +02:00
|
|
|
void __weak pcibios_disable_device (struct pci_dev *dev) {}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-01-07 13:03:42 +01:00
|
|
|
static void do_pci_disable_device(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
u16 pci_command;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &pci_command);
|
|
|
|
if (pci_command & PCI_COMMAND_MASTER) {
|
|
|
|
pci_command &= ~PCI_COMMAND_MASTER;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, pci_command);
|
|
|
|
}
|
|
|
|
|
|
|
|
pcibios_disable_device(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_disable_enabled_device - Disable device without updating enable_cnt
|
|
|
|
* @dev: PCI device to disable
|
|
|
|
*
|
|
|
|
* NOTE: This function is a backend of PCI power management routines and is
|
|
|
|
* not supposed to be called drivers.
|
|
|
|
*/
|
|
|
|
void pci_disable_enabled_device(struct pci_dev *dev)
|
|
|
|
{
|
2009-04-03 09:41:46 +02:00
|
|
|
if (pci_is_enabled(dev))
|
2009-01-07 13:03:42 +01:00
|
|
|
do_pci_disable_device(dev);
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pci_disable_device - Disable PCI device after use
|
|
|
|
* @dev: PCI device to be disabled
|
|
|
|
*
|
|
|
|
* Signal to the system that the PCI device is not in use by the system
|
|
|
|
* anymore. This only involves disabling PCI bus-mastering, if active.
|
PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-22 21:40:31 +01:00
|
|
|
*
|
|
|
|
* Note we don't actually disable the device until all callers of
|
2010-05-18 14:45:47 +02:00
|
|
|
* pci_enable_device() have called pci_disable_device().
|
2005-04-17 00:20:36 +02:00
|
|
|
*/
|
|
|
|
void
|
|
|
|
pci_disable_device(struct pci_dev *dev)
|
|
|
|
{
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
struct pci_devres *dr;
|
2006-05-26 04:58:27 +02:00
|
|
|
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
dr = find_pci_dr(dev);
|
|
|
|
if (dr)
|
2007-02-25 13:36:01 +01:00
|
|
|
dr->enabled = 0;
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
|
PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-22 21:40:31 +01:00
|
|
|
if (atomic_sub_return(1, &dev->enable_cnt) != 0)
|
|
|
|
return;
|
|
|
|
|
2009-01-07 13:03:42 +01:00
|
|
|
do_pci_disable_device(dev);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-01-07 13:03:42 +01:00
|
|
|
dev->is_busmaster = 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2007-04-06 23:39:36 +02:00
|
|
|
/**
|
|
|
|
* pcibios_set_pcie_reset_state - set reset state for device dev
|
2009-12-03 12:49:24 +01:00
|
|
|
* @dev: the PCIe device reset
|
2007-04-06 23:39:36 +02:00
|
|
|
* @state: Reset state to enter into
|
|
|
|
*
|
|
|
|
*
|
2009-12-03 12:49:24 +01:00
|
|
|
* Sets the PCIe reset state for the device. This is the default
|
2007-04-06 23:39:36 +02:00
|
|
|
* implementation. Architecture implementations can override this.
|
|
|
|
*/
|
2012-06-19 14:54:49 +02:00
|
|
|
int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
|
|
|
|
enum pcie_reset_state state)
|
2007-04-06 23:39:36 +02:00
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_set_pcie_reset_state - set reset state for device dev
|
2009-12-03 12:49:24 +01:00
|
|
|
* @dev: the PCIe device reset
|
2007-04-06 23:39:36 +02:00
|
|
|
* @state: Reset state to enter into
|
|
|
|
*
|
|
|
|
*
|
|
|
|
* Sets the PCI reset state for the device.
|
|
|
|
*/
|
|
|
|
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
|
|
|
|
{
|
|
|
|
return pcibios_set_pcie_reset_state(dev, state);
|
|
|
|
}
|
|
|
|
|
2010-02-17 23:36:58 +01:00
|
|
|
/**
|
|
|
|
* pci_check_pme_status - Check if given device has generated PME.
|
|
|
|
* @dev: Device to check.
|
|
|
|
*
|
|
|
|
* Check the PME status of the device and if set, clear it and clear PME enable
|
|
|
|
* (if set). Return 'true' if PME status and PME enable were both set or
|
|
|
|
* 'false' otherwise.
|
|
|
|
*/
|
|
|
|
bool pci_check_pme_status(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pmcsr_pos;
|
|
|
|
u16 pmcsr;
|
|
|
|
bool ret = false;
|
|
|
|
|
|
|
|
if (!dev->pm_cap)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
|
|
|
|
pci_read_config_word(dev, pmcsr_pos, &pmcsr);
|
|
|
|
if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Clear PME status. */
|
|
|
|
pmcsr |= PCI_PM_CTRL_PME_STATUS;
|
|
|
|
if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
|
|
|
|
/* Disable PME to avoid interrupt flood. */
|
|
|
|
pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
|
|
|
|
ret = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_write_config_word(dev, pmcsr_pos, pmcsr);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-02-17 23:44:09 +01:00
|
|
|
/**
|
|
|
|
* pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
|
|
|
|
* @dev: Device to handle.
|
PCI / PM: Extend PME polling to all PCI devices
The land of PCI power management is a land of sorrow and ugliness,
especially in the area of signaling events by devices. There are
devices that set their PME Status bits, but don't really bother
to send a PME message or assert PME#. There are hardware vendors
who don't connect PME# lines to the system core logic (they know
who they are). There are PCI Express Root Ports that don't bother
to trigger interrupts when they receive PME messages from the devices
below. There are ACPI BIOSes that forget to provide _PRW methods for
devices capable of signaling wakeup. Finally, there are BIOSes that
do provide _PRW methods for such devices, but then don't bother to
call Notify() for those devices from the corresponding _Lxx/_Exx
GPE-handling methods. In all of these cases the kernel doesn't have
a chance to receive a proper notification that it should wake up a
device, so devices stay in low-power states forever. Worse yet, in
some cases they continuously send PME Messages that are silently
ignored, because the kernel simply doesn't know that it should clear
the device's PME Status bit.
This problem was first observed for "parallel" (non-Express) PCI
devices on add-on cards and Matthew Garrett addressed it by adding
code that polls PME Status bits of such devices, if they are enabled
to signal PME, to the kernel. Recently, however, it has turned out
that PCI Express devices are also affected by this issue and that it
is not limited to add-on devices, so it seems necessary to extend
the PME polling to all PCI devices, including PCI Express and planar
ones. Still, it would be wasteful to poll the PME Status bits of
devices that are known to receive proper PME notifications, so make
the kernel (1) poll the PME Status bits of all PCI and PCIe devices
enabled to signal PME and (2) disable the PME Status polling for
devices for which correct PME notifications are received.
Tested-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-03 23:16:33 +02:00
|
|
|
* @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
|
2010-02-17 23:44:09 +01:00
|
|
|
*
|
|
|
|
* Check if @dev has generated PME and queue a resume request for it in that
|
|
|
|
* case.
|
|
|
|
*/
|
PCI / PM: Extend PME polling to all PCI devices
The land of PCI power management is a land of sorrow and ugliness,
especially in the area of signaling events by devices. There are
devices that set their PME Status bits, but don't really bother
to send a PME message or assert PME#. There are hardware vendors
who don't connect PME# lines to the system core logic (they know
who they are). There are PCI Express Root Ports that don't bother
to trigger interrupts when they receive PME messages from the devices
below. There are ACPI BIOSes that forget to provide _PRW methods for
devices capable of signaling wakeup. Finally, there are BIOSes that
do provide _PRW methods for such devices, but then don't bother to
call Notify() for those devices from the corresponding _Lxx/_Exx
GPE-handling methods. In all of these cases the kernel doesn't have
a chance to receive a proper notification that it should wake up a
device, so devices stay in low-power states forever. Worse yet, in
some cases they continuously send PME Messages that are silently
ignored, because the kernel simply doesn't know that it should clear
the device's PME Status bit.
This problem was first observed for "parallel" (non-Express) PCI
devices on add-on cards and Matthew Garrett addressed it by adding
code that polls PME Status bits of such devices, if they are enabled
to signal PME, to the kernel. Recently, however, it has turned out
that PCI Express devices are also affected by this issue and that it
is not limited to add-on devices, so it seems necessary to extend
the PME polling to all PCI devices, including PCI Express and planar
ones. Still, it would be wasteful to poll the PME Status bits of
devices that are known to receive proper PME notifications, so make
the kernel (1) poll the PME Status bits of all PCI and PCIe devices
enabled to signal PME and (2) disable the PME Status polling for
devices for which correct PME notifications are received.
Tested-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-03 23:16:33 +02:00
|
|
|
static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
|
2010-02-17 23:44:09 +01:00
|
|
|
{
|
PCI / PM: Extend PME polling to all PCI devices
The land of PCI power management is a land of sorrow and ugliness,
especially in the area of signaling events by devices. There are
devices that set their PME Status bits, but don't really bother
to send a PME message or assert PME#. There are hardware vendors
who don't connect PME# lines to the system core logic (they know
who they are). There are PCI Express Root Ports that don't bother
to trigger interrupts when they receive PME messages from the devices
below. There are ACPI BIOSes that forget to provide _PRW methods for
devices capable of signaling wakeup. Finally, there are BIOSes that
do provide _PRW methods for such devices, but then don't bother to
call Notify() for those devices from the corresponding _Lxx/_Exx
GPE-handling methods. In all of these cases the kernel doesn't have
a chance to receive a proper notification that it should wake up a
device, so devices stay in low-power states forever. Worse yet, in
some cases they continuously send PME Messages that are silently
ignored, because the kernel simply doesn't know that it should clear
the device's PME Status bit.
This problem was first observed for "parallel" (non-Express) PCI
devices on add-on cards and Matthew Garrett addressed it by adding
code that polls PME Status bits of such devices, if they are enabled
to signal PME, to the kernel. Recently, however, it has turned out
that PCI Express devices are also affected by this issue and that it
is not limited to add-on devices, so it seems necessary to extend
the PME polling to all PCI devices, including PCI Express and planar
ones. Still, it would be wasteful to poll the PME Status bits of
devices that are known to receive proper PME notifications, so make
the kernel (1) poll the PME Status bits of all PCI and PCIe devices
enabled to signal PME and (2) disable the PME Status polling for
devices for which correct PME notifications are received.
Tested-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-03 23:16:33 +02:00
|
|
|
if (pme_poll_reset && dev->pme_poll)
|
|
|
|
dev->pme_poll = false;
|
|
|
|
|
PM: Make it possible to avoid races between wakeup and system sleep
One of the arguments during the suspend blockers discussion was that
the mainline kernel didn't contain any mechanisms making it possible
to avoid races between wakeup and system suspend.
Generally, there are two problems in that area. First, if a wakeup
event occurs exactly when /sys/power/state is being written to, it
may be delivered to user space right before the freezer kicks in, so
the user space consumer of the event may not be able to process it
before the system is suspended. Second, if a wakeup event occurs
after user space has been frozen, it is not generally guaranteed that
the ongoing transition of the system into a sleep state will be
aborted.
To address these issues introduce a new global sysfs attribute,
/sys/power/wakeup_count, associated with a running counter of wakeup
events and three helper functions, pm_stay_awake(), pm_relax(), and
pm_wakeup_event(), that may be used by kernel subsystems to control
the behavior of this attribute and to request the PM core to abort
system transitions into a sleep state already in progress.
The /sys/power/wakeup_count file may be read from or written to by
user space. Reads will always succeed (unless interrupted by a
signal) and return the current value of the wakeup events counter.
Writes, however, will only succeed if the written number is equal to
the current value of the wakeup events counter. If a write is
successful, it will cause the kernel to save the current value of the
wakeup events counter and to abort the subsequent system transition
into a sleep state if any wakeup events are reported after the write
has returned.
[The assumption is that before writing to /sys/power/state user space
will first read from /sys/power/wakeup_count. Next, user space
consumers of wakeup events will have a chance to acknowledge or
veto the upcoming system transition to a sleep state. Finally, if
the transition is allowed to proceed, /sys/power/wakeup_count will
be written to and if that succeeds, /sys/power/state will be written
to as well. Still, if any wakeup events are reported to the PM core
by kernel subsystems after that point, the transition will be
aborted.]
Additionally, put a wakeup events counter into struct dev_pm_info and
make these per-device wakeup event counters available via sysfs,
so that it's possible to check the activity of various wakeup event
sources within the kernel.
To illustrate how subsystems can use pm_wakeup_event(), make the
low-level PCI runtime PM wakeup-handling code use it.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Acked-by: markgross <markgross@thegnar.org>
Reviewed-by: Alan Stern <stern@rowland.harvard.edu>
2010-07-05 22:43:53 +02:00
|
|
|
if (pci_check_pme_status(dev)) {
|
|
|
|
pci_wakeup_event(dev);
|
2010-12-29 13:22:08 +01:00
|
|
|
pm_request_resume(&dev->dev);
|
PM: Make it possible to avoid races between wakeup and system sleep
One of the arguments during the suspend blockers discussion was that
the mainline kernel didn't contain any mechanisms making it possible
to avoid races between wakeup and system suspend.
Generally, there are two problems in that area. First, if a wakeup
event occurs exactly when /sys/power/state is being written to, it
may be delivered to user space right before the freezer kicks in, so
the user space consumer of the event may not be able to process it
before the system is suspended. Second, if a wakeup event occurs
after user space has been frozen, it is not generally guaranteed that
the ongoing transition of the system into a sleep state will be
aborted.
To address these issues introduce a new global sysfs attribute,
/sys/power/wakeup_count, associated with a running counter of wakeup
events and three helper functions, pm_stay_awake(), pm_relax(), and
pm_wakeup_event(), that may be used by kernel subsystems to control
the behavior of this attribute and to request the PM core to abort
system transitions into a sleep state already in progress.
The /sys/power/wakeup_count file may be read from or written to by
user space. Reads will always succeed (unless interrupted by a
signal) and return the current value of the wakeup events counter.
Writes, however, will only succeed if the written number is equal to
the current value of the wakeup events counter. If a write is
successful, it will cause the kernel to save the current value of the
wakeup events counter and to abort the subsequent system transition
into a sleep state if any wakeup events are reported after the write
has returned.
[The assumption is that before writing to /sys/power/state user space
will first read from /sys/power/wakeup_count. Next, user space
consumers of wakeup events will have a chance to acknowledge or
veto the upcoming system transition to a sleep state. Finally, if
the transition is allowed to proceed, /sys/power/wakeup_count will
be written to and if that succeeds, /sys/power/state will be written
to as well. Still, if any wakeup events are reported to the PM core
by kernel subsystems after that point, the transition will be
aborted.]
Additionally, put a wakeup events counter into struct dev_pm_info and
make these per-device wakeup event counters available via sysfs,
so that it's possible to check the activity of various wakeup event
sources within the kernel.
To illustrate how subsystems can use pm_wakeup_event(), make the
low-level PCI runtime PM wakeup-handling code use it.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Acked-by: markgross <markgross@thegnar.org>
Reviewed-by: Alan Stern <stern@rowland.harvard.edu>
2010-07-05 22:43:53 +02:00
|
|
|
}
|
2010-02-17 23:44:09 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
|
|
|
|
* @bus: Top bus of the subtree to walk.
|
|
|
|
*/
|
|
|
|
void pci_pme_wakeup_bus(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
if (bus)
|
PCI / PM: Extend PME polling to all PCI devices
The land of PCI power management is a land of sorrow and ugliness,
especially in the area of signaling events by devices. There are
devices that set their PME Status bits, but don't really bother
to send a PME message or assert PME#. There are hardware vendors
who don't connect PME# lines to the system core logic (they know
who they are). There are PCI Express Root Ports that don't bother
to trigger interrupts when they receive PME messages from the devices
below. There are ACPI BIOSes that forget to provide _PRW methods for
devices capable of signaling wakeup. Finally, there are BIOSes that
do provide _PRW methods for such devices, but then don't bother to
call Notify() for those devices from the corresponding _Lxx/_Exx
GPE-handling methods. In all of these cases the kernel doesn't have
a chance to receive a proper notification that it should wake up a
device, so devices stay in low-power states forever. Worse yet, in
some cases they continuously send PME Messages that are silently
ignored, because the kernel simply doesn't know that it should clear
the device's PME Status bit.
This problem was first observed for "parallel" (non-Express) PCI
devices on add-on cards and Matthew Garrett addressed it by adding
code that polls PME Status bits of such devices, if they are enabled
to signal PME, to the kernel. Recently, however, it has turned out
that PCI Express devices are also affected by this issue and that it
is not limited to add-on devices, so it seems necessary to extend
the PME polling to all PCI devices, including PCI Express and planar
ones. Still, it would be wasteful to poll the PME Status bits of
devices that are known to receive proper PME notifications, so make
the kernel (1) poll the PME Status bits of all PCI and PCIe devices
enabled to signal PME and (2) disable the PME Status polling for
devices for which correct PME notifications are received.
Tested-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-03 23:16:33 +02:00
|
|
|
pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
|
2010-02-17 23:44:09 +01:00
|
|
|
}
|
|
|
|
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
/**
|
|
|
|
* pci_wakeup - Wake up a PCI device
|
|
|
|
* @dev: Device to handle.
|
|
|
|
* @ign: ignored parameter
|
|
|
|
*/
|
|
|
|
static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
|
|
|
|
{
|
|
|
|
pci_wakeup_event(pci_dev);
|
|
|
|
pm_request_resume(&pci_dev->dev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_wakeup_bus - Walk given bus and wake up devices on it
|
|
|
|
* @bus: Top bus of the subtree to walk.
|
|
|
|
*/
|
|
|
|
void pci_wakeup_bus(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
if (bus)
|
|
|
|
pci_walk_bus(bus, pci_wakeup, NULL);
|
|
|
|
}
|
|
|
|
|
2008-07-07 03:34:48 +02:00
|
|
|
/**
|
|
|
|
* pci_pme_capable - check the capability of PCI device to generate PME#
|
|
|
|
* @dev: PCI device to handle.
|
|
|
|
* @state: PCI state from which device will issue PME#.
|
|
|
|
*/
|
2008-07-19 14:39:24 +02:00
|
|
|
bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
|
2008-07-07 03:34:48 +02:00
|
|
|
{
|
2008-07-07 03:36:24 +02:00
|
|
|
if (!dev->pm_cap)
|
2008-07-07 03:34:48 +02:00
|
|
|
return false;
|
|
|
|
|
2008-07-07 03:36:24 +02:00
|
|
|
return !!(dev->pme_support & (1 << state));
|
2008-07-07 03:34:48 +02:00
|
|
|
}
|
|
|
|
|
2010-10-04 20:22:29 +02:00
|
|
|
static void pci_pme_list_scan(struct work_struct *work)
|
|
|
|
{
|
PCI / PM: Extend PME polling to all PCI devices
The land of PCI power management is a land of sorrow and ugliness,
especially in the area of signaling events by devices. There are
devices that set their PME Status bits, but don't really bother
to send a PME message or assert PME#. There are hardware vendors
who don't connect PME# lines to the system core logic (they know
who they are). There are PCI Express Root Ports that don't bother
to trigger interrupts when they receive PME messages from the devices
below. There are ACPI BIOSes that forget to provide _PRW methods for
devices capable of signaling wakeup. Finally, there are BIOSes that
do provide _PRW methods for such devices, but then don't bother to
call Notify() for those devices from the corresponding _Lxx/_Exx
GPE-handling methods. In all of these cases the kernel doesn't have
a chance to receive a proper notification that it should wake up a
device, so devices stay in low-power states forever. Worse yet, in
some cases they continuously send PME Messages that are silently
ignored, because the kernel simply doesn't know that it should clear
the device's PME Status bit.
This problem was first observed for "parallel" (non-Express) PCI
devices on add-on cards and Matthew Garrett addressed it by adding
code that polls PME Status bits of such devices, if they are enabled
to signal PME, to the kernel. Recently, however, it has turned out
that PCI Express devices are also affected by this issue and that it
is not limited to add-on devices, so it seems necessary to extend
the PME polling to all PCI devices, including PCI Express and planar
ones. Still, it would be wasteful to poll the PME Status bits of
devices that are known to receive proper PME notifications, so make
the kernel (1) poll the PME Status bits of all PCI and PCIe devices
enabled to signal PME and (2) disable the PME Status polling for
devices for which correct PME notifications are received.
Tested-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-03 23:16:33 +02:00
|
|
|
struct pci_pme_device *pme_dev, *n;
|
2010-10-04 20:22:29 +02:00
|
|
|
|
|
|
|
mutex_lock(&pci_pme_list_mutex);
|
|
|
|
if (!list_empty(&pci_pme_list)) {
|
PCI / PM: Extend PME polling to all PCI devices
The land of PCI power management is a land of sorrow and ugliness,
especially in the area of signaling events by devices. There are
devices that set their PME Status bits, but don't really bother
to send a PME message or assert PME#. There are hardware vendors
who don't connect PME# lines to the system core logic (they know
who they are). There are PCI Express Root Ports that don't bother
to trigger interrupts when they receive PME messages from the devices
below. There are ACPI BIOSes that forget to provide _PRW methods for
devices capable of signaling wakeup. Finally, there are BIOSes that
do provide _PRW methods for such devices, but then don't bother to
call Notify() for those devices from the corresponding _Lxx/_Exx
GPE-handling methods. In all of these cases the kernel doesn't have
a chance to receive a proper notification that it should wake up a
device, so devices stay in low-power states forever. Worse yet, in
some cases they continuously send PME Messages that are silently
ignored, because the kernel simply doesn't know that it should clear
the device's PME Status bit.
This problem was first observed for "parallel" (non-Express) PCI
devices on add-on cards and Matthew Garrett addressed it by adding
code that polls PME Status bits of such devices, if they are enabled
to signal PME, to the kernel. Recently, however, it has turned out
that PCI Express devices are also affected by this issue and that it
is not limited to add-on devices, so it seems necessary to extend
the PME polling to all PCI devices, including PCI Express and planar
ones. Still, it would be wasteful to poll the PME Status bits of
devices that are known to receive proper PME notifications, so make
the kernel (1) poll the PME Status bits of all PCI and PCIe devices
enabled to signal PME and (2) disable the PME Status polling for
devices for which correct PME notifications are received.
Tested-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-03 23:16:33 +02:00
|
|
|
list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
|
|
|
|
if (pme_dev->dev->pme_poll) {
|
2012-06-23 04:23:49 +02:00
|
|
|
struct pci_dev *bridge;
|
|
|
|
|
|
|
|
bridge = pme_dev->dev->bus->self;
|
|
|
|
/*
|
|
|
|
* If bridge is in low power state, the
|
|
|
|
* configuration space of subordinate devices
|
|
|
|
* may be not accessible
|
|
|
|
*/
|
|
|
|
if (bridge && bridge->current_state != PCI_D0)
|
|
|
|
continue;
|
PCI / PM: Extend PME polling to all PCI devices
The land of PCI power management is a land of sorrow and ugliness,
especially in the area of signaling events by devices. There are
devices that set their PME Status bits, but don't really bother
to send a PME message or assert PME#. There are hardware vendors
who don't connect PME# lines to the system core logic (they know
who they are). There are PCI Express Root Ports that don't bother
to trigger interrupts when they receive PME messages from the devices
below. There are ACPI BIOSes that forget to provide _PRW methods for
devices capable of signaling wakeup. Finally, there are BIOSes that
do provide _PRW methods for such devices, but then don't bother to
call Notify() for those devices from the corresponding _Lxx/_Exx
GPE-handling methods. In all of these cases the kernel doesn't have
a chance to receive a proper notification that it should wake up a
device, so devices stay in low-power states forever. Worse yet, in
some cases they continuously send PME Messages that are silently
ignored, because the kernel simply doesn't know that it should clear
the device's PME Status bit.
This problem was first observed for "parallel" (non-Express) PCI
devices on add-on cards and Matthew Garrett addressed it by adding
code that polls PME Status bits of such devices, if they are enabled
to signal PME, to the kernel. Recently, however, it has turned out
that PCI Express devices are also affected by this issue and that it
is not limited to add-on devices, so it seems necessary to extend
the PME polling to all PCI devices, including PCI Express and planar
ones. Still, it would be wasteful to poll the PME Status bits of
devices that are known to receive proper PME notifications, so make
the kernel (1) poll the PME Status bits of all PCI and PCIe devices
enabled to signal PME and (2) disable the PME Status polling for
devices for which correct PME notifications are received.
Tested-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-03 23:16:33 +02:00
|
|
|
pci_pme_wakeup(pme_dev->dev, NULL);
|
|
|
|
} else {
|
|
|
|
list_del(&pme_dev->list);
|
|
|
|
kfree(pme_dev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!list_empty(&pci_pme_list))
|
|
|
|
schedule_delayed_work(&pci_pme_work,
|
|
|
|
msecs_to_jiffies(PME_TIMEOUT));
|
2010-10-04 20:22:29 +02:00
|
|
|
}
|
|
|
|
mutex_unlock(&pci_pme_list_mutex);
|
|
|
|
}
|
|
|
|
|
2008-07-07 03:34:48 +02:00
|
|
|
/**
|
|
|
|
* pci_pme_active - enable or disable PCI device's PME# function
|
|
|
|
* @dev: PCI device to handle.
|
|
|
|
* @enable: 'true' to enable PME# generation; 'false' to disable it.
|
|
|
|
*
|
|
|
|
* The caller must verify that the device is capable of generating PME# before
|
|
|
|
* calling this function with @enable equal to 'true'.
|
|
|
|
*/
|
2008-08-08 00:14:24 +02:00
|
|
|
void pci_pme_active(struct pci_dev *dev, bool enable)
|
2008-07-07 03:34:48 +02:00
|
|
|
{
|
|
|
|
u16 pmcsr;
|
|
|
|
|
2008-07-07 03:36:24 +02:00
|
|
|
if (!dev->pm_cap)
|
2008-07-07 03:34:48 +02:00
|
|
|
return;
|
|
|
|
|
2008-07-07 03:36:24 +02:00
|
|
|
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
|
2008-07-07 03:34:48 +02:00
|
|
|
/* Clear PME_Status by writing 1 to it and enable PME# */
|
|
|
|
pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
|
|
|
|
if (!enable)
|
|
|
|
pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
|
|
|
|
|
2008-07-07 03:36:24 +02:00
|
|
|
pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
|
2008-07-07 03:34:48 +02:00
|
|
|
|
2010-10-04 20:22:29 +02:00
|
|
|
/* PCI (as opposed to PCIe) PME requires that the device have
|
|
|
|
its PME# line hooked up correctly. Not all hardware vendors
|
|
|
|
do this, so the PME never gets delivered and the device
|
|
|
|
remains asleep. The easiest way around this is to
|
|
|
|
periodically walk the list of suspended devices and check
|
|
|
|
whether any have their PME flag set. The assumption is that
|
|
|
|
we'll wake up often enough anyway that this won't be a huge
|
|
|
|
hit, and the power savings from the devices will still be a
|
|
|
|
win. */
|
|
|
|
|
PCI / PM: Extend PME polling to all PCI devices
The land of PCI power management is a land of sorrow and ugliness,
especially in the area of signaling events by devices. There are
devices that set their PME Status bits, but don't really bother
to send a PME message or assert PME#. There are hardware vendors
who don't connect PME# lines to the system core logic (they know
who they are). There are PCI Express Root Ports that don't bother
to trigger interrupts when they receive PME messages from the devices
below. There are ACPI BIOSes that forget to provide _PRW methods for
devices capable of signaling wakeup. Finally, there are BIOSes that
do provide _PRW methods for such devices, but then don't bother to
call Notify() for those devices from the corresponding _Lxx/_Exx
GPE-handling methods. In all of these cases the kernel doesn't have
a chance to receive a proper notification that it should wake up a
device, so devices stay in low-power states forever. Worse yet, in
some cases they continuously send PME Messages that are silently
ignored, because the kernel simply doesn't know that it should clear
the device's PME Status bit.
This problem was first observed for "parallel" (non-Express) PCI
devices on add-on cards and Matthew Garrett addressed it by adding
code that polls PME Status bits of such devices, if they are enabled
to signal PME, to the kernel. Recently, however, it has turned out
that PCI Express devices are also affected by this issue and that it
is not limited to add-on devices, so it seems necessary to extend
the PME polling to all PCI devices, including PCI Express and planar
ones. Still, it would be wasteful to poll the PME Status bits of
devices that are known to receive proper PME notifications, so make
the kernel (1) poll the PME Status bits of all PCI and PCIe devices
enabled to signal PME and (2) disable the PME Status polling for
devices for which correct PME notifications are received.
Tested-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-03 23:16:33 +02:00
|
|
|
if (dev->pme_poll) {
|
2010-10-04 20:22:29 +02:00
|
|
|
struct pci_pme_device *pme_dev;
|
|
|
|
if (enable) {
|
|
|
|
pme_dev = kmalloc(sizeof(struct pci_pme_device),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!pme_dev)
|
|
|
|
goto out;
|
|
|
|
pme_dev->dev = dev;
|
|
|
|
mutex_lock(&pci_pme_list_mutex);
|
|
|
|
list_add(&pme_dev->list, &pci_pme_list);
|
|
|
|
if (list_is_singular(&pci_pme_list))
|
|
|
|
schedule_delayed_work(&pci_pme_work,
|
|
|
|
msecs_to_jiffies(PME_TIMEOUT));
|
|
|
|
mutex_unlock(&pci_pme_list_mutex);
|
|
|
|
} else {
|
|
|
|
mutex_lock(&pci_pme_list_mutex);
|
|
|
|
list_for_each_entry(pme_dev, &pci_pme_list, list) {
|
|
|
|
if (pme_dev->dev == dev) {
|
|
|
|
list_del(&pme_dev->list);
|
|
|
|
kfree(pme_dev);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
mutex_unlock(&pci_pme_list_mutex);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
2011-12-05 20:51:18 +01:00
|
|
|
dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
|
2008-07-07 03:34:48 +02:00
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
2010-02-17 23:44:58 +01:00
|
|
|
* __pci_enable_wake - enable PCI device as wakeup event source
|
2007-04-26 09:12:06 +02:00
|
|
|
* @dev: PCI device affected
|
|
|
|
* @state: PCI state from which device will issue wakeup events
|
2010-02-17 23:44:58 +01:00
|
|
|
* @runtime: True if the events are to be generated at run time
|
2007-04-26 09:12:06 +02:00
|
|
|
* @enable: True to enable event generation; false to disable
|
|
|
|
*
|
|
|
|
* This enables the device as a wakeup event source, or disables it.
|
|
|
|
* When such events involves platform-specific hooks, those hooks are
|
|
|
|
* called automatically by this routine.
|
|
|
|
*
|
|
|
|
* Devices with legacy power management (no standard PCI PM capabilities)
|
2008-07-07 03:34:48 +02:00
|
|
|
* always require such platform hooks.
|
2007-04-26 09:12:06 +02:00
|
|
|
*
|
2008-07-07 03:34:48 +02:00
|
|
|
* RETURN VALUE:
|
|
|
|
* 0 is returned on success
|
|
|
|
* -EINVAL is returned if device is not supposed to wake up the system
|
|
|
|
* Error code depending on the platform is returned if both the platform and
|
|
|
|
* the native mechanism fail to enable the generation of wake-up events
|
2005-04-17 00:20:36 +02:00
|
|
|
*/
|
2010-02-17 23:44:58 +01:00
|
|
|
int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
|
|
|
|
bool runtime, bool enable)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2009-09-08 23:12:59 +02:00
|
|
|
int ret = 0;
|
2007-04-26 09:12:06 +02:00
|
|
|
|
2010-02-17 23:44:58 +01:00
|
|
|
if (enable && !runtime && !device_may_wakeup(&dev->dev))
|
2008-07-07 03:34:48 +02:00
|
|
|
return -EINVAL;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-09-08 23:14:49 +02:00
|
|
|
/* Don't do the same thing twice in a row for one device. */
|
|
|
|
if (!!enable == !!dev->wakeup_prepared)
|
|
|
|
return 0;
|
|
|
|
|
2008-07-07 03:34:48 +02:00
|
|
|
/*
|
|
|
|
* According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
|
|
|
|
* Anderson we should be doing PME# wake enable followed by ACPI wake
|
|
|
|
* enable. To disable wake-up we call the platform first, for symmetry.
|
2007-04-26 09:12:06 +02:00
|
|
|
*/
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-09-08 23:12:59 +02:00
|
|
|
if (enable) {
|
|
|
|
int error;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-09-08 23:12:59 +02:00
|
|
|
if (pci_pme_capable(dev, state))
|
|
|
|
pci_pme_active(dev, true);
|
|
|
|
else
|
|
|
|
ret = 1;
|
2010-02-17 23:44:58 +01:00
|
|
|
error = runtime ? platform_pci_run_wake(dev, true) :
|
|
|
|
platform_pci_sleep_wake(dev, true);
|
2009-09-08 23:12:59 +02:00
|
|
|
if (ret)
|
|
|
|
ret = error;
|
2009-09-08 23:14:49 +02:00
|
|
|
if (!ret)
|
|
|
|
dev->wakeup_prepared = true;
|
2009-09-08 23:12:59 +02:00
|
|
|
} else {
|
2010-02-17 23:44:58 +01:00
|
|
|
if (runtime)
|
|
|
|
platform_pci_run_wake(dev, false);
|
|
|
|
else
|
|
|
|
platform_pci_sleep_wake(dev, false);
|
2009-09-08 23:12:59 +02:00
|
|
|
pci_pme_active(dev, false);
|
2009-09-08 23:14:49 +02:00
|
|
|
dev->wakeup_prepared = false;
|
2009-09-08 23:12:59 +02:00
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-09-08 23:12:59 +02:00
|
|
|
return ret;
|
2008-07-07 03:34:48 +02:00
|
|
|
}
|
2010-02-17 23:44:58 +01:00
|
|
|
EXPORT_SYMBOL(__pci_enable_wake);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-08-18 21:38:00 +02:00
|
|
|
/**
|
|
|
|
* pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
|
|
|
|
* @dev: PCI device to prepare
|
|
|
|
* @enable: True to enable wake-up event generation; false to disable
|
|
|
|
*
|
|
|
|
* Many drivers want the device to wake up the system from D3_hot or D3_cold
|
|
|
|
* and this function allows them to set that up cleanly - pci_enable_wake()
|
|
|
|
* should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
|
|
|
|
* ordering constraints.
|
|
|
|
*
|
|
|
|
* This function only returns error code if the device is not capable of
|
|
|
|
* generating PME# from both D3_hot and D3_cold, and the platform is unable to
|
|
|
|
* enable wake-up power for it.
|
|
|
|
*/
|
|
|
|
int pci_wake_from_d3(struct pci_dev *dev, bool enable)
|
|
|
|
{
|
|
|
|
return pci_pme_capable(dev, PCI_D3cold) ?
|
|
|
|
pci_enable_wake(dev, PCI_D3cold, enable) :
|
|
|
|
pci_enable_wake(dev, PCI_D3hot, enable);
|
|
|
|
}
|
|
|
|
|
2008-07-07 03:35:26 +02:00
|
|
|
/**
|
2008-07-28 20:49:26 +02:00
|
|
|
* pci_target_state - find an appropriate low power state for a given PCI dev
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
|
|
|
* Use underlying platform code to find a supported low power state for @dev.
|
|
|
|
* If the platform can't manage @dev, return the deepest state from which it
|
|
|
|
* can generate wake events, based on any available PME info.
|
2008-07-07 03:35:26 +02:00
|
|
|
*/
|
2008-07-19 14:39:24 +02:00
|
|
|
pci_power_t pci_target_state(struct pci_dev *dev)
|
2008-07-07 03:35:26 +02:00
|
|
|
{
|
|
|
|
pci_power_t target_state = PCI_D3hot;
|
|
|
|
|
|
|
|
if (platform_pci_power_manageable(dev)) {
|
|
|
|
/*
|
|
|
|
* Call the platform to choose the target state of the device
|
|
|
|
* and enable wake-up from this state if supported.
|
|
|
|
*/
|
|
|
|
pci_power_t state = platform_pci_choose_state(dev);
|
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
case PCI_POWER_ERROR:
|
|
|
|
case PCI_UNKNOWN:
|
|
|
|
break;
|
|
|
|
case PCI_D1:
|
|
|
|
case PCI_D2:
|
|
|
|
if (pci_no_d1d2(dev))
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
target_state = state;
|
|
|
|
}
|
2009-06-14 21:25:02 +02:00
|
|
|
} else if (!dev->pm_cap) {
|
|
|
|
target_state = PCI_D0;
|
2008-07-07 03:35:26 +02:00
|
|
|
} else if (device_may_wakeup(&dev->dev)) {
|
|
|
|
/*
|
|
|
|
* Find the deepest state from which the device can generate
|
|
|
|
* wake-up events, make it the target state and enable device
|
|
|
|
* to generate PME#.
|
|
|
|
*/
|
2008-07-07 03:36:24 +02:00
|
|
|
if (dev->pme_support) {
|
|
|
|
while (target_state
|
|
|
|
&& !(dev->pme_support & (1 << target_state)))
|
|
|
|
target_state--;
|
2008-07-07 03:35:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-19 14:39:24 +02:00
|
|
|
return target_state;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
|
|
|
|
* @dev: Device to handle.
|
|
|
|
*
|
|
|
|
* Choose the power state appropriate for the device depending on whether
|
|
|
|
* it can wake up the system and/or is power manageable by the platform
|
|
|
|
* (PCI_D3hot is the default) and put the device into that state.
|
|
|
|
*/
|
|
|
|
int pci_prepare_to_sleep(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
pci_power_t target_state = pci_target_state(dev);
|
|
|
|
int error;
|
|
|
|
|
|
|
|
if (target_state == PCI_POWER_ERROR)
|
|
|
|
return -EIO;
|
|
|
|
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
/* D3cold during system suspend/hibernate is not supported */
|
|
|
|
if (target_state > PCI_D3hot)
|
|
|
|
target_state = PCI_D3hot;
|
|
|
|
|
2009-03-30 21:46:27 +02:00
|
|
|
pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
|
2008-07-13 22:45:06 +02:00
|
|
|
|
2008-07-07 03:35:26 +02:00
|
|
|
error = pci_set_power_state(dev, target_state);
|
|
|
|
|
|
|
|
if (error)
|
|
|
|
pci_enable_wake(dev, target_state, false);
|
|
|
|
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2008-07-21 18:27:18 +02:00
|
|
|
* pci_back_from_sleep - turn PCI device on during system-wide transition into working state
|
2008-07-07 03:35:26 +02:00
|
|
|
* @dev: Device to handle.
|
|
|
|
*
|
2010-03-16 11:47:56 +01:00
|
|
|
* Disable device's system wake-up capability and put it into D0.
|
2008-07-07 03:35:26 +02:00
|
|
|
*/
|
|
|
|
int pci_back_from_sleep(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
pci_enable_wake(dev, PCI_D0, false);
|
|
|
|
return pci_set_power_state(dev, PCI_D0);
|
|
|
|
}
|
|
|
|
|
2010-02-17 23:44:58 +01:00
|
|
|
/**
|
|
|
|
* pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
|
|
|
|
* @dev: PCI device being suspended.
|
|
|
|
*
|
|
|
|
* Prepare @dev to generate wake-up events at run time and put it into a low
|
|
|
|
* power state.
|
|
|
|
*/
|
|
|
|
int pci_finish_runtime_suspend(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
pci_power_t target_state = pci_target_state(dev);
|
|
|
|
int error;
|
|
|
|
|
|
|
|
if (target_state == PCI_POWER_ERROR)
|
|
|
|
return -EIO;
|
|
|
|
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
dev->runtime_d3cold = target_state == PCI_D3cold;
|
|
|
|
|
2010-02-17 23:44:58 +01:00
|
|
|
__pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
|
|
|
|
|
|
|
|
error = pci_set_power_state(dev, target_state);
|
|
|
|
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
if (error) {
|
2010-02-17 23:44:58 +01:00
|
|
|
__pci_enable_wake(dev, target_state, true, false);
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
dev->runtime_d3cold = false;
|
|
|
|
}
|
2010-02-17 23:44:58 +01:00
|
|
|
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
2010-02-17 23:44:09 +01:00
|
|
|
/**
|
|
|
|
* pci_dev_run_wake - Check if device can generate run-time wake-up events.
|
|
|
|
* @dev: Device to check.
|
|
|
|
*
|
|
|
|
* Return true if the device itself is cabable of generating wake-up events
|
|
|
|
* (through the platform or using the native PCIe PME) or if the device supports
|
|
|
|
* PME and one of its upstream bridges can generate wake-up events.
|
|
|
|
*/
|
|
|
|
bool pci_dev_run_wake(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct pci_bus *bus = dev->bus;
|
|
|
|
|
|
|
|
if (device_run_wake(&dev->dev))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (!dev->pme_support)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
while (bus->parent) {
|
|
|
|
struct pci_dev *bridge = bus->self;
|
|
|
|
|
|
|
|
if (device_run_wake(&bridge->dev))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
bus = bus->parent;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We have reached the root bus. */
|
|
|
|
if (bus->bridge)
|
|
|
|
return device_run_wake(bus->bridge);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_dev_run_wake);
|
|
|
|
|
2008-07-07 03:34:48 +02:00
|
|
|
/**
|
|
|
|
* pci_pm_init - Initialize PM functions of given PCI device
|
|
|
|
* @dev: PCI device to handle.
|
|
|
|
*/
|
|
|
|
void pci_pm_init(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pm;
|
|
|
|
u16 pmc;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2010-02-27 21:37:37 +01:00
|
|
|
pm_runtime_forbid(&dev->dev);
|
2010-02-08 19:16:33 +01:00
|
|
|
device_enable_async_suspend(&dev->dev);
|
2009-09-08 23:14:49 +02:00
|
|
|
dev->wakeup_prepared = false;
|
2010-02-27 21:37:37 +01:00
|
|
|
|
2008-07-07 03:36:24 +02:00
|
|
|
dev->pm_cap = 0;
|
|
|
|
|
2008-07-07 03:34:48 +02:00
|
|
|
/* find PCI PM capability in list */
|
|
|
|
pm = pci_find_capability(dev, PCI_CAP_ID_PM);
|
|
|
|
if (!pm)
|
2009-01-16 17:14:51 +01:00
|
|
|
return;
|
2008-07-07 03:34:48 +02:00
|
|
|
/* Check device's ability to generate PME# */
|
|
|
|
pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
|
2007-04-26 09:12:06 +02:00
|
|
|
|
2008-07-07 03:34:48 +02:00
|
|
|
if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
|
|
|
|
dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
|
|
|
|
pmc & PCI_PM_CAP_VER_MASK);
|
2009-01-16 17:14:51 +01:00
|
|
|
return;
|
2008-07-07 03:34:48 +02:00
|
|
|
}
|
|
|
|
|
2008-07-07 03:36:24 +02:00
|
|
|
dev->pm_cap = pm;
|
2009-12-31 12:15:54 +01:00
|
|
|
dev->d3_delay = PCI_PM_D3_WAIT;
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 04:23:51 +02:00
|
|
|
dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
|
2008-07-07 03:36:24 +02:00
|
|
|
|
|
|
|
dev->d1_support = false;
|
|
|
|
dev->d2_support = false;
|
|
|
|
if (!pci_no_d1d2(dev)) {
|
2008-08-22 17:37:02 +02:00
|
|
|
if (pmc & PCI_PM_CAP_D1)
|
2008-07-07 03:36:24 +02:00
|
|
|
dev->d1_support = true;
|
2008-08-22 17:37:02 +02:00
|
|
|
if (pmc & PCI_PM_CAP_D2)
|
2008-07-07 03:36:24 +02:00
|
|
|
dev->d2_support = true;
|
2008-08-22 17:37:02 +02:00
|
|
|
|
|
|
|
if (dev->d1_support || dev->d2_support)
|
|
|
|
dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
|
2008-09-23 20:43:34 +02:00
|
|
|
dev->d1_support ? " D1" : "",
|
|
|
|
dev->d2_support ? " D2" : "");
|
2008-07-07 03:36:24 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
pmc &= PCI_PM_CAP_PME_MASK;
|
|
|
|
if (pmc) {
|
2009-11-04 18:32:42 +01:00
|
|
|
dev_printk(KERN_DEBUG, &dev->dev,
|
|
|
|
"PME# supported from%s%s%s%s%s\n",
|
2008-08-22 17:37:02 +02:00
|
|
|
(pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
|
|
|
|
(pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
|
|
|
|
(pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
|
|
|
|
(pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
|
|
|
|
(pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
|
2008-07-07 03:36:24 +02:00
|
|
|
dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
|
PCI / PM: Extend PME polling to all PCI devices
The land of PCI power management is a land of sorrow and ugliness,
especially in the area of signaling events by devices. There are
devices that set their PME Status bits, but don't really bother
to send a PME message or assert PME#. There are hardware vendors
who don't connect PME# lines to the system core logic (they know
who they are). There are PCI Express Root Ports that don't bother
to trigger interrupts when they receive PME messages from the devices
below. There are ACPI BIOSes that forget to provide _PRW methods for
devices capable of signaling wakeup. Finally, there are BIOSes that
do provide _PRW methods for such devices, but then don't bother to
call Notify() for those devices from the corresponding _Lxx/_Exx
GPE-handling methods. In all of these cases the kernel doesn't have
a chance to receive a proper notification that it should wake up a
device, so devices stay in low-power states forever. Worse yet, in
some cases they continuously send PME Messages that are silently
ignored, because the kernel simply doesn't know that it should clear
the device's PME Status bit.
This problem was first observed for "parallel" (non-Express) PCI
devices on add-on cards and Matthew Garrett addressed it by adding
code that polls PME Status bits of such devices, if they are enabled
to signal PME, to the kernel. Recently, however, it has turned out
that PCI Express devices are also affected by this issue and that it
is not limited to add-on devices, so it seems necessary to extend
the PME polling to all PCI devices, including PCI Express and planar
ones. Still, it would be wasteful to poll the PME Status bits of
devices that are known to receive proper PME notifications, so make
the kernel (1) poll the PME Status bits of all PCI and PCIe devices
enabled to signal PME and (2) disable the PME Status polling for
devices for which correct PME notifications are received.
Tested-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-03 23:16:33 +02:00
|
|
|
dev->pme_poll = true;
|
2008-07-07 03:34:48 +02:00
|
|
|
/*
|
|
|
|
* Make device's PM flags reflect the wake-up capability, but
|
|
|
|
* let the user space enable it to wake up the system as needed.
|
|
|
|
*/
|
|
|
|
device_set_wakeup_capable(&dev->dev, true);
|
|
|
|
/* Disable the PME# generation functionality */
|
2008-07-07 03:36:24 +02:00
|
|
|
pci_pme_active(dev, false);
|
|
|
|
} else {
|
|
|
|
dev->pme_support = 0;
|
2008-07-07 03:34:48 +02:00
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2008-12-17 21:10:05 +01:00
|
|
|
/**
|
|
|
|
* platform_pci_wakeup_init - init platform wakeup if present
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
|
|
|
* Some devices don't have PCI PM caps but can still generate wakeup
|
|
|
|
* events through platform methods (like ACPI events). If @dev supports
|
|
|
|
* platform wakeup events, set the device flag to indicate as much. This
|
|
|
|
* may be redundant if the device also supports PCI PM caps, but double
|
|
|
|
* initialization should be safe in that case.
|
|
|
|
*/
|
|
|
|
void platform_pci_wakeup_init(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
if (!platform_pci_can_wakeup(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
device_set_wakeup_capable(&dev->dev, true);
|
|
|
|
platform_pci_sleep_wake(dev, false);
|
|
|
|
}
|
|
|
|
|
2012-02-11 09:18:41 +01:00
|
|
|
static void pci_add_saved_cap(struct pci_dev *pci_dev,
|
|
|
|
struct pci_cap_saved_state *new_cap)
|
|
|
|
{
|
|
|
|
hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
|
|
|
|
}
|
|
|
|
|
2008-12-07 22:02:58 +01:00
|
|
|
/**
|
|
|
|
* pci_add_save_buffer - allocate buffer for saving given capability registers
|
|
|
|
* @dev: the PCI device
|
|
|
|
* @cap: the capability to allocate the buffer for
|
|
|
|
* @size: requested size of the buffer
|
|
|
|
*/
|
|
|
|
static int pci_add_cap_save_buffer(
|
|
|
|
struct pci_dev *dev, char cap, unsigned int size)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
struct pci_cap_saved_state *save_state;
|
|
|
|
|
|
|
|
pos = pci_find_capability(dev, cap);
|
|
|
|
if (pos <= 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
|
|
|
|
if (!save_state)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2011-05-10 18:02:11 +02:00
|
|
|
save_state->cap.cap_nr = cap;
|
|
|
|
save_state->cap.size = size;
|
2008-12-07 22:02:58 +01:00
|
|
|
pci_add_saved_cap(dev, save_state);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
|
|
|
|
* @dev: the PCI device
|
|
|
|
*/
|
|
|
|
void pci_allocate_cap_save_buffers(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int error;
|
|
|
|
|
2009-02-15 19:55:47 +01:00
|
|
|
error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
|
|
|
|
PCI_EXP_SAVE_REGS * sizeof(u16));
|
2008-12-07 22:02:58 +01:00
|
|
|
if (error)
|
|
|
|
dev_err(&dev->dev,
|
|
|
|
"unable to preallocate PCI Express save buffer\n");
|
|
|
|
|
|
|
|
error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
|
|
|
|
if (error)
|
|
|
|
dev_err(&dev->dev,
|
|
|
|
"unable to preallocate PCI-X save buffer\n");
|
|
|
|
}
|
|
|
|
|
2012-02-11 09:18:30 +01:00
|
|
|
void pci_free_cap_save_buffers(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct pci_cap_saved_state *tmp;
|
|
|
|
struct hlist_node *pos, *n;
|
|
|
|
|
|
|
|
hlist_for_each_entry_safe(tmp, pos, n, &dev->saved_cap_space, next)
|
|
|
|
kfree(tmp);
|
|
|
|
}
|
|
|
|
|
2008-10-14 08:02:53 +02:00
|
|
|
/**
|
|
|
|
* pci_enable_ari - enable ARI forwarding if hardware support it
|
|
|
|
* @dev: the PCI device
|
|
|
|
*/
|
|
|
|
void pci_enable_ari(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u32 cap;
|
2012-06-01 23:16:37 +02:00
|
|
|
u16 ctrl;
|
2008-10-23 07:15:39 +02:00
|
|
|
struct pci_dev *bridge;
|
2008-10-14 08:02:53 +02:00
|
|
|
|
2012-03-01 00:06:33 +01:00
|
|
|
if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
|
2008-10-14 08:02:53 +02:00
|
|
|
return;
|
|
|
|
|
2008-10-23 07:15:39 +02:00
|
|
|
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
|
|
|
|
if (!pos)
|
2008-10-14 08:02:53 +02:00
|
|
|
return;
|
|
|
|
|
2008-10-23 07:15:39 +02:00
|
|
|
bridge = dev->bus->self;
|
2012-06-01 23:16:31 +02:00
|
|
|
if (!bridge)
|
2008-10-23 07:15:39 +02:00
|
|
|
return;
|
|
|
|
|
2012-06-01 23:16:37 +02:00
|
|
|
/* ARI is a PCIe cap v2 feature */
|
|
|
|
pos = pci_pcie_cap2(bridge);
|
2008-10-14 08:02:53 +02:00
|
|
|
if (!pos)
|
|
|
|
return;
|
|
|
|
|
2008-10-23 07:15:39 +02:00
|
|
|
pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
|
2008-10-14 08:02:53 +02:00
|
|
|
if (!(cap & PCI_EXP_DEVCAP2_ARI))
|
|
|
|
return;
|
|
|
|
|
2008-10-23 07:15:39 +02:00
|
|
|
pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
|
2008-10-14 08:02:53 +02:00
|
|
|
ctrl |= PCI_EXP_DEVCTL2_ARI;
|
2008-10-23 07:15:39 +02:00
|
|
|
pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
|
2008-10-14 08:02:53 +02:00
|
|
|
|
2008-10-23 07:15:39 +02:00
|
|
|
bridge->ari_enabled = 1;
|
2008-10-14 08:02:53 +02:00
|
|
|
}
|
|
|
|
|
2010-10-19 22:07:57 +02:00
|
|
|
/**
|
2012-06-01 23:16:37 +02:00
|
|
|
* pci_enable_ido - enable ID-based Ordering on a device
|
2010-10-19 22:07:57 +02:00
|
|
|
* @dev: the PCI device
|
|
|
|
* @type: which types of IDO to enable
|
|
|
|
*
|
|
|
|
* Enable ID-based ordering on @dev. @type can contain the bits
|
|
|
|
* %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
|
|
|
|
* which types of transactions are allowed to be re-ordered.
|
|
|
|
*/
|
|
|
|
void pci_enable_ido(struct pci_dev *dev, unsigned long type)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u16 ctrl;
|
|
|
|
|
2012-06-01 23:16:37 +02:00
|
|
|
/* ID-based Ordering is a PCIe cap v2 feature */
|
|
|
|
pos = pci_pcie_cap2(dev);
|
2010-10-19 22:07:57 +02:00
|
|
|
if (!pos)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
|
|
|
if (type & PCI_EXP_IDO_REQUEST)
|
|
|
|
ctrl |= PCI_EXP_IDO_REQ_EN;
|
|
|
|
if (type & PCI_EXP_IDO_COMPLETION)
|
|
|
|
ctrl |= PCI_EXP_IDO_CMP_EN;
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_enable_ido);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_disable_ido - disable ID-based ordering on a device
|
|
|
|
* @dev: the PCI device
|
|
|
|
* @type: which types of IDO to disable
|
|
|
|
*/
|
|
|
|
void pci_disable_ido(struct pci_dev *dev, unsigned long type)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u16 ctrl;
|
|
|
|
|
2012-06-01 23:16:37 +02:00
|
|
|
/* ID-based Ordering is a PCIe cap v2 feature */
|
|
|
|
pos = pci_pcie_cap2(dev);
|
2010-10-19 22:07:57 +02:00
|
|
|
if (!pos)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
|
|
|
if (type & PCI_EXP_IDO_REQUEST)
|
|
|
|
ctrl &= ~PCI_EXP_IDO_REQ_EN;
|
|
|
|
if (type & PCI_EXP_IDO_COMPLETION)
|
|
|
|
ctrl &= ~PCI_EXP_IDO_CMP_EN;
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_disable_ido);
|
|
|
|
|
2011-01-10 21:46:36 +01:00
|
|
|
/**
|
|
|
|
* pci_enable_obff - enable optimized buffer flush/fill
|
|
|
|
* @dev: PCI device
|
|
|
|
* @type: type of signaling to use
|
|
|
|
*
|
|
|
|
* Try to enable @type OBFF signaling on @dev. It will try using WAKE#
|
|
|
|
* signaling if possible, falling back to message signaling only if
|
|
|
|
* WAKE# isn't supported. @type should indicate whether the PCIe link
|
|
|
|
* be brought out of L0s or L1 to send the message. It should be either
|
|
|
|
* %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
|
|
|
|
*
|
|
|
|
* If your device can benefit from receiving all messages, even at the
|
|
|
|
* power cost of bringing the link back up from a low power state, use
|
|
|
|
* %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
|
|
|
|
* preferred type).
|
|
|
|
*
|
|
|
|
* RETURNS:
|
|
|
|
* Zero on success, appropriate error number on failure.
|
|
|
|
*/
|
|
|
|
int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u32 cap;
|
|
|
|
u16 ctrl;
|
|
|
|
int ret;
|
|
|
|
|
2012-06-01 23:16:37 +02:00
|
|
|
/* OBFF is a PCIe cap v2 feature */
|
|
|
|
pos = pci_pcie_cap2(dev);
|
2011-01-10 21:46:36 +01:00
|
|
|
if (!pos)
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
|
|
|
|
if (!(cap & PCI_EXP_OBFF_MASK))
|
|
|
|
return -ENOTSUPP; /* no OBFF support at all */
|
|
|
|
|
|
|
|
/* Make sure the topology supports OBFF as well */
|
2012-06-19 15:35:34 +02:00
|
|
|
if (dev->bus->self) {
|
2011-01-10 21:46:36 +01:00
|
|
|
ret = pci_enable_obff(dev->bus->self, type);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
|
|
|
if (cap & PCI_EXP_OBFF_WAKE)
|
|
|
|
ctrl |= PCI_EXP_OBFF_WAKE_EN;
|
|
|
|
else {
|
|
|
|
switch (type) {
|
|
|
|
case PCI_EXP_OBFF_SIGNAL_L0:
|
|
|
|
if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
|
|
|
|
ctrl |= PCI_EXP_OBFF_MSGA_EN;
|
|
|
|
break;
|
|
|
|
case PCI_EXP_OBFF_SIGNAL_ALWAYS:
|
|
|
|
ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
|
|
|
|
ctrl |= PCI_EXP_OBFF_MSGB_EN;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "bad OBFF signal type\n");
|
|
|
|
return -ENOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_enable_obff);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_disable_obff - disable optimized buffer flush/fill
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
|
|
|
* Disable OBFF on @dev.
|
|
|
|
*/
|
|
|
|
void pci_disable_obff(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u16 ctrl;
|
|
|
|
|
2012-06-01 23:16:37 +02:00
|
|
|
/* OBFF is a PCIe cap v2 feature */
|
|
|
|
pos = pci_pcie_cap2(dev);
|
2011-01-10 21:46:36 +01:00
|
|
|
if (!pos)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
|
|
|
ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_disable_obff);
|
|
|
|
|
2011-01-14 17:53:04 +01:00
|
|
|
/**
|
|
|
|
* pci_ltr_supported - check whether a device supports LTR
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
|
|
|
* RETURNS:
|
|
|
|
* True if @dev supports latency tolerance reporting, false otherwise.
|
|
|
|
*/
|
2012-06-01 23:16:25 +02:00
|
|
|
static bool pci_ltr_supported(struct pci_dev *dev)
|
2011-01-14 17:53:04 +01:00
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u32 cap;
|
|
|
|
|
2012-06-01 23:16:37 +02:00
|
|
|
/* LTR is a PCIe cap v2 feature */
|
|
|
|
pos = pci_pcie_cap2(dev);
|
2011-01-14 17:53:04 +01:00
|
|
|
if (!pos)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
|
|
|
|
|
|
|
|
return cap & PCI_EXP_DEVCAP2_LTR;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_enable_ltr - enable latency tolerance reporting
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
|
|
|
* Enable LTR on @dev if possible, which means enabling it first on
|
|
|
|
* upstream ports.
|
|
|
|
*
|
|
|
|
* RETURNS:
|
|
|
|
* Zero on success, errno on failure.
|
|
|
|
*/
|
|
|
|
int pci_enable_ltr(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u16 ctrl;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!pci_ltr_supported(dev))
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
2012-06-01 23:16:37 +02:00
|
|
|
/* LTR is a PCIe cap v2 feature */
|
|
|
|
pos = pci_pcie_cap2(dev);
|
2011-01-14 17:53:04 +01:00
|
|
|
if (!pos)
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
/* Only primary function can enable/disable LTR */
|
|
|
|
if (PCI_FUNC(dev->devfn) != 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* Enable upstream ports first */
|
2012-06-19 15:35:34 +02:00
|
|
|
if (dev->bus->self) {
|
2011-01-14 17:53:04 +01:00
|
|
|
ret = pci_enable_ltr(dev->bus->self);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
|
|
|
ctrl |= PCI_EXP_LTR_EN;
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_enable_ltr);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_disable_ltr - disable latency tolerance reporting
|
|
|
|
* @dev: PCI device
|
|
|
|
*/
|
|
|
|
void pci_disable_ltr(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u16 ctrl;
|
|
|
|
|
|
|
|
if (!pci_ltr_supported(dev))
|
|
|
|
return;
|
|
|
|
|
2012-06-01 23:16:37 +02:00
|
|
|
/* LTR is a PCIe cap v2 feature */
|
|
|
|
pos = pci_pcie_cap2(dev);
|
2011-01-14 17:53:04 +01:00
|
|
|
if (!pos)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Only primary function can enable/disable LTR */
|
|
|
|
if (PCI_FUNC(dev->devfn) != 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
|
|
|
ctrl &= ~PCI_EXP_LTR_EN;
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_disable_ltr);
|
|
|
|
|
|
|
|
static int __pci_ltr_scale(int *val)
|
|
|
|
{
|
|
|
|
int scale = 0;
|
|
|
|
|
|
|
|
while (*val > 1023) {
|
|
|
|
*val = (*val + 31) / 32;
|
|
|
|
scale++;
|
|
|
|
}
|
|
|
|
return scale;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_set_ltr - set LTR latency values
|
|
|
|
* @dev: PCI device
|
|
|
|
* @snoop_lat_ns: snoop latency in nanoseconds
|
|
|
|
* @nosnoop_lat_ns: nosnoop latency in nanoseconds
|
|
|
|
*
|
|
|
|
* Figure out the scale and set the LTR values accordingly.
|
|
|
|
*/
|
|
|
|
int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
|
|
|
|
{
|
|
|
|
int pos, ret, snoop_scale, nosnoop_scale;
|
|
|
|
u16 val;
|
|
|
|
|
|
|
|
if (!pci_ltr_supported(dev))
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
|
|
|
|
nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
|
|
|
|
|
|
|
|
if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
|
|
|
|
nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
|
|
|
|
(nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
|
|
|
|
if (!pos)
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
|
|
|
|
ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
|
|
|
|
if (ret != 4)
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
|
|
|
|
ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
|
|
|
|
if (ret != 4)
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_set_ltr);
|
|
|
|
|
2009-12-04 21:15:21 +01:00
|
|
|
static int pci_acs_enable;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_request_acs - ask for ACS to be enabled if supported
|
|
|
|
*/
|
|
|
|
void pci_request_acs(void)
|
|
|
|
{
|
|
|
|
pci_acs_enable = 1;
|
|
|
|
}
|
|
|
|
|
2009-10-07 19:27:17 +02:00
|
|
|
/**
|
|
|
|
* pci_enable_acs - enable ACS if hardware support it
|
|
|
|
* @dev: the PCI device
|
|
|
|
*/
|
|
|
|
void pci_enable_acs(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u16 cap;
|
|
|
|
u16 ctrl;
|
|
|
|
|
2009-12-04 21:15:21 +01:00
|
|
|
if (!pci_acs_enable)
|
|
|
|
return;
|
|
|
|
|
2009-11-11 06:36:17 +01:00
|
|
|
if (!pci_is_pcie(dev))
|
2009-10-07 19:27:17 +02:00
|
|
|
return;
|
|
|
|
|
|
|
|
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
|
|
|
|
if (!pos)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
|
|
|
|
pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
|
|
|
|
|
|
|
|
/* Source Validation */
|
|
|
|
ctrl |= (cap & PCI_ACS_SV);
|
|
|
|
|
|
|
|
/* P2P Request Redirect */
|
|
|
|
ctrl |= (cap & PCI_ACS_RR);
|
|
|
|
|
|
|
|
/* P2P Completion Redirect */
|
|
|
|
ctrl |= (cap & PCI_ACS_CR);
|
|
|
|
|
|
|
|
/* Upstream Forwarding */
|
|
|
|
ctrl |= (cap & PCI_ACS_UF);
|
|
|
|
|
|
|
|
pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
|
|
|
|
}
|
|
|
|
|
2012-06-11 07:27:07 +02:00
|
|
|
/**
|
|
|
|
* pci_acs_enabled - test ACS against required flags for a given device
|
|
|
|
* @pdev: device to test
|
|
|
|
* @acs_flags: required PCI ACS flags
|
|
|
|
*
|
|
|
|
* Return true if the device supports the provided flags. Automatically
|
|
|
|
* filters out flags that are not implemented on multifunction devices.
|
|
|
|
*/
|
|
|
|
bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
|
|
|
|
{
|
|
|
|
int pos, ret;
|
|
|
|
u16 ctrl;
|
|
|
|
|
|
|
|
ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
|
|
|
|
if (ret >= 0)
|
|
|
|
return ret > 0;
|
|
|
|
|
|
|
|
if (!pci_is_pcie(pdev))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Filter out flags not applicable to multifunction */
|
|
|
|
if (pdev->multifunction)
|
|
|
|
acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
|
|
|
|
PCI_ACS_EC | PCI_ACS_DT);
|
|
|
|
|
|
|
|
if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM ||
|
|
|
|
pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
|
|
pdev->multifunction) {
|
|
|
|
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
|
|
|
|
if (!pos)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
|
|
|
|
if ((ctrl & acs_flags) != acs_flags)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_acs_path_enable - test ACS flags from start to end in a hierarchy
|
|
|
|
* @start: starting downstream device
|
|
|
|
* @end: ending upstream device or NULL to search to the root bus
|
|
|
|
* @acs_flags: required flags
|
|
|
|
*
|
|
|
|
* Walk up a device tree from start to end testing PCI ACS support. If
|
|
|
|
* any step along the way does not support the required flags, return false.
|
|
|
|
*/
|
|
|
|
bool pci_acs_path_enabled(struct pci_dev *start,
|
|
|
|
struct pci_dev *end, u16 acs_flags)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev, *parent = start;
|
|
|
|
|
|
|
|
do {
|
|
|
|
pdev = parent;
|
|
|
|
|
|
|
|
if (!pci_acs_enabled(pdev, acs_flags))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (pci_is_root_bus(pdev->bus))
|
|
|
|
return (end == NULL);
|
|
|
|
|
|
|
|
parent = pdev->bus->self;
|
|
|
|
} while (pdev != end);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2008-12-11 19:24:23 +01:00
|
|
|
/**
|
|
|
|
* pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
|
|
|
|
* @dev: the PCI device
|
|
|
|
* @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
|
|
|
|
*
|
|
|
|
* Perform INTx swizzling for a device behind one level of bridge. This is
|
|
|
|
* required by section 9.1 of the PCI-to-PCI bridge specification for devices
|
2009-07-01 23:24:30 +02:00
|
|
|
* behind bridges on add-in cards. For devices with ARI enabled, the slot
|
|
|
|
* number is always 0 (see the Implementation Note in section 2.2.8.1 of
|
|
|
|
* the PCI Express Base Specification, Revision 2.1)
|
2008-12-11 19:24:23 +01:00
|
|
|
*/
|
2012-04-12 17:33:07 +02:00
|
|
|
u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
|
2008-12-11 19:24:23 +01:00
|
|
|
{
|
2009-07-01 23:24:30 +02:00
|
|
|
int slot;
|
|
|
|
|
|
|
|
if (pci_ari_enabled(dev->bus))
|
|
|
|
slot = 0;
|
|
|
|
else
|
|
|
|
slot = PCI_SLOT(dev->devfn);
|
|
|
|
|
|
|
|
return (((pin - 1) + slot) % 4) + 1;
|
2008-12-11 19:24:23 +01:00
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
int
|
|
|
|
pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
|
|
|
|
{
|
|
|
|
u8 pin;
|
|
|
|
|
2005-11-03 01:24:39 +01:00
|
|
|
pin = dev->pin;
|
2005-04-17 00:20:36 +02:00
|
|
|
if (!pin)
|
|
|
|
return -1;
|
2008-12-10 00:11:46 +01:00
|
|
|
|
2009-05-26 09:07:33 +02:00
|
|
|
while (!pci_is_root_bus(dev->bus)) {
|
2008-12-11 19:24:23 +01:00
|
|
|
pin = pci_swizzle_interrupt_pin(dev, pin);
|
2005-04-17 00:20:36 +02:00
|
|
|
dev = dev->bus->self;
|
|
|
|
}
|
|
|
|
*bridge = dev;
|
|
|
|
return pin;
|
|
|
|
}
|
|
|
|
|
2008-12-17 05:36:55 +01:00
|
|
|
/**
|
|
|
|
* pci_common_swizzle - swizzle INTx all the way to root bridge
|
|
|
|
* @dev: the PCI device
|
|
|
|
* @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
|
|
|
|
*
|
|
|
|
* Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
|
|
|
|
* bridges all the way up to a PCI root bus.
|
|
|
|
*/
|
|
|
|
u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
|
|
|
|
{
|
|
|
|
u8 pin = *pinp;
|
|
|
|
|
2009-05-26 09:08:36 +02:00
|
|
|
while (!pci_is_root_bus(dev->bus)) {
|
2008-12-17 05:36:55 +01:00
|
|
|
pin = pci_swizzle_interrupt_pin(dev, pin);
|
|
|
|
dev = dev->bus->self;
|
|
|
|
}
|
|
|
|
*pinp = pin;
|
|
|
|
return PCI_SLOT(dev->devfn);
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pci_release_region - Release a PCI bar
|
|
|
|
* @pdev: PCI device whose resources were previously reserved by pci_request_region
|
|
|
|
* @bar: BAR to release
|
|
|
|
*
|
|
|
|
* Releases the PCI I/O and memory resources previously reserved by a
|
|
|
|
* successful call to pci_request_region. Call this function only
|
|
|
|
* after all use of the PCI regions has ceased.
|
|
|
|
*/
|
|
|
|
void pci_release_region(struct pci_dev *pdev, int bar)
|
|
|
|
{
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
struct pci_devres *dr;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
if (pci_resource_len(pdev, bar) == 0)
|
|
|
|
return;
|
|
|
|
if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
|
|
|
|
release_region(pci_resource_start(pdev, bar),
|
|
|
|
pci_resource_len(pdev, bar));
|
|
|
|
else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
|
|
|
|
release_mem_region(pci_resource_start(pdev, bar),
|
|
|
|
pci_resource_len(pdev, bar));
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
|
|
|
|
dr = find_pci_dr(pdev);
|
|
|
|
if (dr)
|
|
|
|
dr->region_mask &= ~(1 << bar);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2009-01-10 02:03:20 +01:00
|
|
|
* __pci_request_region - Reserved PCI I/O and memory resource
|
2005-04-17 00:20:36 +02:00
|
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
|
|
* @bar: BAR to be reserved
|
|
|
|
* @res_name: Name to be associated with resource.
|
2009-01-10 02:03:20 +01:00
|
|
|
* @exclusive: whether the region access is exclusive or not
|
2005-04-17 00:20:36 +02:00
|
|
|
*
|
|
|
|
* Mark the PCI region associated with PCI device @pdev BR @bar as
|
|
|
|
* being reserved by owner @res_name. Do not access any
|
|
|
|
* address inside the PCI regions unless this call returns
|
|
|
|
* successfully.
|
|
|
|
*
|
2009-01-10 02:03:20 +01:00
|
|
|
* If @exclusive is set, then the region is marked so that userspace
|
|
|
|
* is explicitly not allowed to map the resource via /dev/mem or
|
|
|
|
* sysfs MMIO access.
|
|
|
|
*
|
2005-04-17 00:20:36 +02:00
|
|
|
* Returns 0 on success, or %EBUSY on error. A warning
|
|
|
|
* message is also printed on failure.
|
|
|
|
*/
|
2008-10-23 04:55:31 +02:00
|
|
|
static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
|
|
|
|
int exclusive)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
struct pci_devres *dr;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
if (pci_resource_len(pdev, bar) == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
|
|
|
|
if (!request_region(pci_resource_start(pdev, bar),
|
|
|
|
pci_resource_len(pdev, bar), res_name))
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
|
2008-10-23 04:55:31 +02:00
|
|
|
if (!__request_mem_region(pci_resource_start(pdev, bar),
|
|
|
|
pci_resource_len(pdev, bar), res_name,
|
|
|
|
exclusive))
|
2005-04-17 00:20:36 +02:00
|
|
|
goto err_out;
|
|
|
|
}
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
|
|
|
|
dr = find_pci_dr(pdev);
|
|
|
|
if (dr)
|
|
|
|
dr->region_mask |= 1 << bar;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out:
|
2009-10-27 20:26:47 +01:00
|
|
|
dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
|
2008-10-20 06:07:37 +02:00
|
|
|
&pdev->resource[bar]);
|
2005-04-17 00:20:36 +02:00
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2008-10-23 04:55:31 +02:00
|
|
|
/**
|
2009-01-10 02:03:20 +01:00
|
|
|
* pci_request_region - Reserve PCI I/O and memory resource
|
2008-10-23 04:55:31 +02:00
|
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
|
|
* @bar: BAR to be reserved
|
2009-01-10 02:03:20 +01:00
|
|
|
* @res_name: Name to be associated with resource
|
2008-10-23 04:55:31 +02:00
|
|
|
*
|
2009-01-10 02:03:20 +01:00
|
|
|
* Mark the PCI region associated with PCI device @pdev BAR @bar as
|
2008-10-23 04:55:31 +02:00
|
|
|
* being reserved by owner @res_name. Do not access any
|
|
|
|
* address inside the PCI regions unless this call returns
|
|
|
|
* successfully.
|
|
|
|
*
|
|
|
|
* Returns 0 on success, or %EBUSY on error. A warning
|
|
|
|
* message is also printed on failure.
|
|
|
|
*/
|
|
|
|
int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
|
|
|
|
{
|
|
|
|
return __pci_request_region(pdev, bar, res_name, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_request_region_exclusive - Reserved PCI I/O and memory resource
|
|
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
|
|
* @bar: BAR to be reserved
|
|
|
|
* @res_name: Name to be associated with resource.
|
|
|
|
*
|
|
|
|
* Mark the PCI region associated with PCI device @pdev BR @bar as
|
|
|
|
* being reserved by owner @res_name. Do not access any
|
|
|
|
* address inside the PCI regions unless this call returns
|
|
|
|
* successfully.
|
|
|
|
*
|
|
|
|
* Returns 0 on success, or %EBUSY on error. A warning
|
|
|
|
* message is also printed on failure.
|
|
|
|
*
|
|
|
|
* The key difference that _exclusive makes it that userspace is
|
|
|
|
* explicitly not allowed to map the resource via /dev/mem or
|
|
|
|
* sysfs.
|
|
|
|
*/
|
|
|
|
int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
|
|
|
|
{
|
|
|
|
return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
|
|
|
|
}
|
2006-12-18 02:31:06 +01:00
|
|
|
/**
|
|
|
|
* pci_release_selected_regions - Release selected PCI I/O and memory resources
|
|
|
|
* @pdev: PCI device whose resources were previously reserved
|
|
|
|
* @bars: Bitmask of BARs to be released
|
|
|
|
*
|
|
|
|
* Release selected PCI I/O and memory resources previously reserved.
|
|
|
|
* Call this function only after all use of the PCI regions has ceased.
|
|
|
|
*/
|
|
|
|
void pci_release_selected_regions(struct pci_dev *pdev, int bars)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 6; i++)
|
|
|
|
if (bars & (1 << i))
|
|
|
|
pci_release_region(pdev, i);
|
|
|
|
}
|
|
|
|
|
2008-10-23 04:55:31 +02:00
|
|
|
int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
|
|
|
|
const char *res_name, int excl)
|
2006-12-18 02:31:06 +01:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 6; i++)
|
|
|
|
if (bars & (1 << i))
|
2008-10-23 04:55:31 +02:00
|
|
|
if (__pci_request_region(pdev, i, res_name, excl))
|
2006-12-18 02:31:06 +01:00
|
|
|
goto err_out;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out:
|
|
|
|
while(--i >= 0)
|
|
|
|
if (bars & (1 << i))
|
|
|
|
pci_release_region(pdev, i);
|
|
|
|
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-10-23 04:55:31 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_request_selected_regions - Reserve selected PCI I/O and memory resources
|
|
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
|
|
* @bars: Bitmask of BARs to be requested
|
|
|
|
* @res_name: Name to be associated with resource
|
|
|
|
*/
|
|
|
|
int pci_request_selected_regions(struct pci_dev *pdev, int bars,
|
|
|
|
const char *res_name)
|
|
|
|
{
|
|
|
|
return __pci_request_selected_regions(pdev, bars, res_name, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
|
|
|
|
int bars, const char *res_name)
|
|
|
|
{
|
|
|
|
return __pci_request_selected_regions(pdev, bars, res_name,
|
|
|
|
IORESOURCE_EXCLUSIVE);
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pci_release_regions - Release reserved PCI I/O and memory resources
|
|
|
|
* @pdev: PCI device whose resources were previously reserved by pci_request_regions
|
|
|
|
*
|
|
|
|
* Releases all PCI I/O and memory resources previously reserved by a
|
|
|
|
* successful call to pci_request_regions. Call this function only
|
|
|
|
* after all use of the PCI regions has ceased.
|
|
|
|
*/
|
|
|
|
|
|
|
|
void pci_release_regions(struct pci_dev *pdev)
|
|
|
|
{
|
2006-12-18 02:31:06 +01:00
|
|
|
pci_release_selected_regions(pdev, (1 << 6) - 1);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_request_regions - Reserved PCI I/O and memory resources
|
|
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
|
|
* @res_name: Name to be associated with resource.
|
|
|
|
*
|
|
|
|
* Mark all PCI regions associated with PCI device @pdev as
|
|
|
|
* being reserved by owner @res_name. Do not access any
|
|
|
|
* address inside the PCI regions unless this call returns
|
|
|
|
* successfully.
|
|
|
|
*
|
|
|
|
* Returns 0 on success, or %EBUSY on error. A warning
|
|
|
|
* message is also printed on failure.
|
|
|
|
*/
|
2006-03-05 03:52:42 +01:00
|
|
|
int pci_request_regions(struct pci_dev *pdev, const char *res_name)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2006-12-18 02:31:06 +01:00
|
|
|
return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2008-10-23 04:55:31 +02:00
|
|
|
/**
|
|
|
|
* pci_request_regions_exclusive - Reserved PCI I/O and memory resources
|
|
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
|
|
* @res_name: Name to be associated with resource.
|
|
|
|
*
|
|
|
|
* Mark all PCI regions associated with PCI device @pdev as
|
|
|
|
* being reserved by owner @res_name. Do not access any
|
|
|
|
* address inside the PCI regions unless this call returns
|
|
|
|
* successfully.
|
|
|
|
*
|
|
|
|
* pci_request_regions_exclusive() will mark the region so that
|
|
|
|
* /dev/mem and the sysfs MMIO access will not be allowed.
|
|
|
|
*
|
|
|
|
* Returns 0 on success, or %EBUSY on error. A warning
|
|
|
|
* message is also printed on failure.
|
|
|
|
*/
|
|
|
|
int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
|
|
|
|
{
|
|
|
|
return pci_request_selected_regions_exclusive(pdev,
|
|
|
|
((1 << 6) - 1), res_name);
|
|
|
|
}
|
|
|
|
|
2008-12-23 04:08:29 +01:00
|
|
|
static void __pci_set_master(struct pci_dev *dev, bool enable)
|
|
|
|
{
|
|
|
|
u16 old_cmd, cmd;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
|
|
|
|
if (enable)
|
|
|
|
cmd = old_cmd | PCI_COMMAND_MASTER;
|
|
|
|
else
|
|
|
|
cmd = old_cmd & ~PCI_COMMAND_MASTER;
|
|
|
|
if (cmd != old_cmd) {
|
|
|
|
dev_dbg(&dev->dev, "%s bus mastering\n",
|
|
|
|
enable ? "enabling" : "disabling");
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
|
|
}
|
|
|
|
dev->is_busmaster = enable;
|
|
|
|
}
|
2008-10-23 04:55:31 +02:00
|
|
|
|
2012-06-26 05:30:57 +02:00
|
|
|
/**
|
|
|
|
* pcibios_setup - process "pci=" kernel boot arguments
|
|
|
|
* @str: string used to pass in "pci=" kernel boot arguments
|
|
|
|
*
|
|
|
|
* Process kernel boot arguments. This is the default implementation.
|
|
|
|
* Architecture specific implementations can override this as necessary.
|
|
|
|
*/
|
|
|
|
char * __weak __init pcibios_setup(char *str)
|
|
|
|
{
|
|
|
|
return str;
|
|
|
|
}
|
|
|
|
|
2011-10-28 23:48:38 +02:00
|
|
|
/**
|
|
|
|
* pcibios_set_master - enable PCI bus-mastering for device dev
|
|
|
|
* @dev: the PCI device to enable
|
|
|
|
*
|
|
|
|
* Enables PCI bus-mastering for the device. This is the default
|
|
|
|
* implementation. Architecture specific implementations can override
|
|
|
|
* this if necessary.
|
|
|
|
*/
|
|
|
|
void __weak pcibios_set_master(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
u8 lat;
|
|
|
|
|
2011-10-28 23:49:20 +02:00
|
|
|
/* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
|
|
|
|
if (pci_is_pcie(dev))
|
|
|
|
return;
|
|
|
|
|
2011-10-28 23:48:38 +02:00
|
|
|
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
|
|
|
|
if (lat < 16)
|
|
|
|
lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
|
|
|
|
else if (lat > pcibios_max_latency)
|
|
|
|
lat = pcibios_max_latency;
|
|
|
|
else
|
|
|
|
return;
|
|
|
|
dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
|
|
|
|
pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pci_set_master - enables bus-mastering for device dev
|
|
|
|
* @dev: the PCI device to enable
|
|
|
|
*
|
|
|
|
* Enables bus-mastering on the device and calls pcibios_set_master()
|
|
|
|
* to do the needed arch specific settings.
|
|
|
|
*/
|
2008-12-23 04:08:29 +01:00
|
|
|
void pci_set_master(struct pci_dev *dev)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2008-12-23 04:08:29 +01:00
|
|
|
__pci_set_master(dev, true);
|
2005-04-17 00:20:36 +02:00
|
|
|
pcibios_set_master(dev);
|
|
|
|
}
|
|
|
|
|
2008-12-23 04:08:29 +01:00
|
|
|
/**
|
|
|
|
* pci_clear_master - disables bus-mastering for device dev
|
|
|
|
* @dev: the PCI device to disable
|
|
|
|
*/
|
|
|
|
void pci_clear_master(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
__pci_set_master(dev, false);
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
2006-10-10 16:01:21 +02:00
|
|
|
* pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
|
|
|
|
* @dev: the PCI device for which MWI is to be enabled
|
2005-04-17 00:20:36 +02:00
|
|
|
*
|
2006-10-10 16:01:21 +02:00
|
|
|
* Helper function for pci_set_mwi.
|
|
|
|
* Originally copied from drivers/net/acenic.c.
|
2005-04-17 00:20:36 +02:00
|
|
|
* Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
|
|
|
|
*
|
|
|
|
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
|
|
|
|
*/
|
2009-09-22 10:34:48 +02:00
|
|
|
int pci_set_cacheline_size(struct pci_dev *dev)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
u8 cacheline_size;
|
|
|
|
|
|
|
|
if (!pci_cache_line_size)
|
2009-09-22 10:34:48 +02:00
|
|
|
return -EINVAL;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* Validate current setting: the PCI_CACHE_LINE_SIZE must be
|
|
|
|
equal to or multiple of the right value. */
|
|
|
|
pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
|
|
|
|
if (cacheline_size >= pci_cache_line_size &&
|
|
|
|
(cacheline_size % pci_cache_line_size) == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Write the correct value. */
|
|
|
|
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
|
|
|
|
/* Read it back. */
|
|
|
|
pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
|
|
|
|
if (cacheline_size == pci_cache_line_size)
|
|
|
|
return 0;
|
|
|
|
|
2008-06-13 18:52:11 +02:00
|
|
|
dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
|
|
|
|
"supported\n", pci_cache_line_size << 2);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2009-09-22 10:34:48 +02:00
|
|
|
EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
|
|
|
|
|
|
|
|
#ifdef PCI_DISABLE_MWI
|
|
|
|
int pci_set_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pci_try_set_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void pci_clear_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_set_mwi - enables memory-write-invalidate PCI transaction
|
|
|
|
* @dev: the PCI device for which MWI is enabled
|
|
|
|
*
|
2007-07-09 20:55:54 +02:00
|
|
|
* Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
|
2005-04-17 00:20:36 +02:00
|
|
|
*
|
|
|
|
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
pci_set_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
u16 cmd;
|
|
|
|
|
2006-10-10 16:01:21 +02:00
|
|
|
rc = pci_set_cacheline_size(dev);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
|
|
if (! (cmd & PCI_COMMAND_INVALIDATE)) {
|
2008-06-13 18:52:11 +02:00
|
|
|
dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
|
2005-04-17 00:20:36 +02:00
|
|
|
cmd |= PCI_COMMAND_INVALIDATE;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-09 20:55:54 +02:00
|
|
|
/**
|
|
|
|
* pci_try_set_mwi - enables memory-write-invalidate PCI transaction
|
|
|
|
* @dev: the PCI device for which MWI is enabled
|
|
|
|
*
|
|
|
|
* Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
|
|
|
|
* Callers are not required to check the return value.
|
|
|
|
*
|
|
|
|
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
|
|
|
|
*/
|
|
|
|
int pci_try_set_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int rc = pci_set_mwi(dev);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/**
|
|
|
|
* pci_clear_mwi - disables Memory-Write-Invalidate for device dev
|
|
|
|
* @dev: the PCI device to disable
|
|
|
|
*
|
|
|
|
* Disables PCI Memory-Write-Invalidate transaction on the device
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
pci_clear_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
u16 cmd;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
|
|
if (cmd & PCI_COMMAND_INVALIDATE) {
|
|
|
|
cmd &= ~PCI_COMMAND_INVALIDATE;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
|
|
}
|
|
|
|
}
|
2006-10-10 16:01:21 +02:00
|
|
|
#endif /* ! PCI_DISABLE_MWI */
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-08-15 21:23:41 +02:00
|
|
|
/**
|
|
|
|
* pci_intx - enables/disables PCI INTx for device dev
|
2005-10-23 20:57:38 +02:00
|
|
|
* @pdev: the PCI device to operate on
|
|
|
|
* @enable: boolean: whether to enable or disable PCI INTx
|
2005-08-15 21:23:41 +02:00
|
|
|
*
|
|
|
|
* Enables/disables PCI INTx for device dev
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
pci_intx(struct pci_dev *pdev, int enable)
|
|
|
|
{
|
|
|
|
u16 pci_command, new;
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
|
|
|
|
|
|
|
|
if (enable) {
|
|
|
|
new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
|
|
|
|
} else {
|
|
|
|
new = pci_command | PCI_COMMAND_INTX_DISABLE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (new != pci_command) {
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
struct pci_devres *dr;
|
|
|
|
|
2005-09-09 19:02:22 +02:00
|
|
|
pci_write_config_word(pdev, PCI_COMMAND, new);
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
|
|
|
|
dr = find_pci_dr(pdev);
|
|
|
|
if (dr && !dr->restore_intx) {
|
|
|
|
dr->restore_intx = 1;
|
|
|
|
dr->orig_intx = !enable;
|
|
|
|
}
|
2005-08-15 21:23:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-04 09:46:00 +01:00
|
|
|
/**
|
|
|
|
* pci_intx_mask_supported - probe for INTx masking support
|
2012-01-21 20:02:35 +01:00
|
|
|
* @dev: the PCI device to operate on
|
2011-11-04 09:46:00 +01:00
|
|
|
*
|
|
|
|
* Check if the device dev support INTx masking via the config space
|
|
|
|
* command word.
|
|
|
|
*/
|
|
|
|
bool pci_intx_mask_supported(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
bool mask_supported = false;
|
|
|
|
u16 orig, new;
|
|
|
|
|
2012-06-16 22:40:22 +02:00
|
|
|
if (dev->broken_intx_masking)
|
|
|
|
return false;
|
|
|
|
|
2011-11-04 09:46:00 +01:00
|
|
|
pci_cfg_access_lock(dev);
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &orig);
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND,
|
|
|
|
orig ^ PCI_COMMAND_INTX_DISABLE);
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &new);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* There's no way to protect against hardware bugs or detect them
|
|
|
|
* reliably, but as long as we know what the value should be, let's
|
|
|
|
* go ahead and check it.
|
|
|
|
*/
|
|
|
|
if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
|
|
|
|
dev_err(&dev->dev, "Command register changed from "
|
|
|
|
"0x%x to 0x%x: driver or hardware bug?\n", orig, new);
|
|
|
|
} else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
|
|
|
|
mask_supported = true;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, orig);
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_cfg_access_unlock(dev);
|
|
|
|
return mask_supported;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
|
|
|
|
|
|
|
|
static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
|
|
|
|
{
|
|
|
|
struct pci_bus *bus = dev->bus;
|
|
|
|
bool mask_updated = true;
|
|
|
|
u32 cmd_status_dword;
|
|
|
|
u16 origcmd, newcmd;
|
|
|
|
unsigned long flags;
|
|
|
|
bool irq_pending;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We do a single dword read to retrieve both command and status.
|
|
|
|
* Document assumptions that make this possible.
|
|
|
|
*/
|
|
|
|
BUILD_BUG_ON(PCI_COMMAND % 4);
|
|
|
|
BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
|
|
|
|
|
|
|
|
raw_spin_lock_irqsave(&pci_lock, flags);
|
|
|
|
|
|
|
|
bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
|
|
|
|
|
|
|
|
irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check interrupt status register to see whether our device
|
|
|
|
* triggered the interrupt (when masking) or the next IRQ is
|
|
|
|
* already pending (when unmasking).
|
|
|
|
*/
|
|
|
|
if (mask != irq_pending) {
|
|
|
|
mask_updated = false;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
origcmd = cmd_status_dword;
|
|
|
|
newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
|
|
|
|
if (mask)
|
|
|
|
newcmd |= PCI_COMMAND_INTX_DISABLE;
|
|
|
|
if (newcmd != origcmd)
|
|
|
|
bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
|
|
|
|
|
|
|
|
done:
|
|
|
|
raw_spin_unlock_irqrestore(&pci_lock, flags);
|
|
|
|
|
|
|
|
return mask_updated;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_check_and_mask_intx - mask INTx on pending interrupt
|
2012-01-21 20:02:35 +01:00
|
|
|
* @dev: the PCI device to operate on
|
2011-11-04 09:46:00 +01:00
|
|
|
*
|
|
|
|
* Check if the device dev has its INTx line asserted, mask it and
|
|
|
|
* return true in that case. False is returned if not interrupt was
|
|
|
|
* pending.
|
|
|
|
*/
|
|
|
|
bool pci_check_and_mask_intx(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return pci_check_and_set_intx_mask(dev, true);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_check_and_mask_intx - unmask INTx of no interrupt is pending
|
2012-01-21 20:02:35 +01:00
|
|
|
* @dev: the PCI device to operate on
|
2011-11-04 09:46:00 +01:00
|
|
|
*
|
|
|
|
* Check if the device dev has its INTx line asserted, unmask it if not
|
|
|
|
* and return true. False is returned and the mask remains active if
|
|
|
|
* there was still an interrupt pending.
|
|
|
|
*/
|
|
|
|
bool pci_check_and_unmask_intx(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return pci_check_and_set_intx_mask(dev, false);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
|
|
|
|
|
2007-03-05 09:30:07 +01:00
|
|
|
/**
|
|
|
|
* pci_msi_off - disables any msi or msix capabilities
|
2007-03-17 03:55:52 +01:00
|
|
|
* @dev: the PCI device to operate on
|
2007-03-05 09:30:07 +01:00
|
|
|
*
|
|
|
|
* If you want to use msi see pci_enable_msi and friends.
|
|
|
|
* This is a lower level primitive that allows us to disable
|
|
|
|
* msi operation at the device level.
|
|
|
|
*/
|
|
|
|
void pci_msi_off(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u16 control;
|
|
|
|
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
|
|
|
if (pos) {
|
|
|
|
pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
|
|
|
|
control &= ~PCI_MSI_FLAGS_ENABLE;
|
|
|
|
pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
|
|
|
|
}
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
|
|
|
if (pos) {
|
|
|
|
pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
|
|
|
|
control &= ~PCI_MSIX_FLAGS_ENABLE;
|
|
|
|
pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
|
|
|
|
}
|
|
|
|
}
|
2010-06-24 06:49:06 +02:00
|
|
|
EXPORT_SYMBOL_GPL(pci_msi_off);
|
2007-03-05 09:30:07 +01:00
|
|
|
|
2008-02-05 07:27:55 +01:00
|
|
|
int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
|
|
|
|
{
|
|
|
|
return dma_set_max_seg_size(&dev->dev, size);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_set_dma_max_seg_size);
|
|
|
|
|
2008-02-05 07:28:14 +01:00
|
|
|
int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
|
|
|
|
{
|
|
|
|
return dma_set_seg_boundary(&dev->dev, mask);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_set_dma_seg_boundary);
|
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
static int pcie_flr(struct pci_dev *dev, int probe)
|
2008-10-21 11:38:25 +02:00
|
|
|
{
|
2009-06-13 09:52:13 +02:00
|
|
|
int i;
|
|
|
|
int pos;
|
2008-10-21 11:38:25 +02:00
|
|
|
u32 cap;
|
2009-12-03 21:27:51 +01:00
|
|
|
u16 status, control;
|
2008-10-21 11:38:25 +02:00
|
|
|
|
2009-11-11 06:30:56 +01:00
|
|
|
pos = pci_pcie_cap(dev);
|
2009-06-13 09:52:13 +02:00
|
|
|
if (!pos)
|
2008-10-21 11:38:25 +02:00
|
|
|
return -ENOTTY;
|
2009-06-13 09:52:13 +02:00
|
|
|
|
|
|
|
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
|
2008-10-21 11:38:25 +02:00
|
|
|
if (!(cap & PCI_EXP_DEVCAP_FLR))
|
|
|
|
return -ENOTTY;
|
|
|
|
|
2008-11-11 10:17:47 +01:00
|
|
|
if (probe)
|
|
|
|
return 0;
|
|
|
|
|
2008-10-21 11:38:25 +02:00
|
|
|
/* Wait for Transaction Pending bit clean */
|
2009-06-13 09:52:13 +02:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
if (i)
|
|
|
|
msleep((1 << (i - 1)) * 100);
|
2009-02-09 07:53:47 +01:00
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
|
|
|
|
if (!(status & PCI_EXP_DEVSTA_TRPND))
|
|
|
|
goto clear;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_err(&dev->dev, "transaction is not cleared; "
|
|
|
|
"proceeding with reset anyway\n");
|
|
|
|
|
|
|
|
clear:
|
2009-12-03 21:27:51 +01:00
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
|
|
|
|
control |= PCI_EXP_DEVCTL_BCR_FLR;
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
|
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
msleep(100);
|
2008-10-21 11:38:25 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2008-11-11 10:17:47 +01:00
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
static int pci_af_flr(struct pci_dev *dev, int probe)
|
2008-11-11 10:17:48 +01:00
|
|
|
{
|
2009-06-13 09:52:13 +02:00
|
|
|
int i;
|
|
|
|
int pos;
|
2008-11-11 10:17:48 +01:00
|
|
|
u8 cap;
|
2009-06-13 09:52:13 +02:00
|
|
|
u8 status;
|
2008-11-11 10:17:48 +01:00
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_AF);
|
|
|
|
if (!pos)
|
2008-11-11 10:17:48 +01:00
|
|
|
return -ENOTTY;
|
2009-06-13 09:52:13 +02:00
|
|
|
|
|
|
|
pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
|
2008-11-11 10:17:48 +01:00
|
|
|
if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
|
|
|
|
return -ENOTTY;
|
|
|
|
|
|
|
|
if (probe)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Wait for Transaction Pending bit clean */
|
2009-06-13 09:52:13 +02:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
if (i)
|
|
|
|
msleep((1 << (i - 1)) * 100);
|
|
|
|
|
|
|
|
pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
|
|
|
|
if (!(status & PCI_AF_STATUS_TP))
|
|
|
|
goto clear;
|
|
|
|
}
|
2009-02-09 07:53:47 +01:00
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
dev_err(&dev->dev, "transaction is not cleared; "
|
|
|
|
"proceeding with reset anyway\n");
|
2009-02-09 07:53:47 +01:00
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
clear:
|
|
|
|
pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
|
2008-11-11 10:17:48 +01:00
|
|
|
msleep(100);
|
2009-06-13 09:52:13 +02:00
|
|
|
|
2008-11-11 10:17:48 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-03-05 21:48:44 +01:00
|
|
|
/**
|
|
|
|
* pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
|
|
|
|
* @dev: Device to reset.
|
|
|
|
* @probe: If set, only check if the device can be reset this way.
|
|
|
|
*
|
|
|
|
* If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
|
|
|
|
* unset, it will be reinitialized internally when going from PCI_D3hot to
|
|
|
|
* PCI_D0. If that's the case and the device is not in a low-power state
|
|
|
|
* already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
|
|
|
|
*
|
|
|
|
* NOTE: This causes the caller to sleep for twice the device power transition
|
|
|
|
* cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
|
|
|
|
* by devault (i.e. unless the @dev's d3_delay field has a different value).
|
|
|
|
* Moreover, only devices in D0 can be reset by this function.
|
|
|
|
*/
|
2009-06-13 09:52:14 +02:00
|
|
|
static int pci_pm_reset(struct pci_dev *dev, int probe)
|
2008-11-11 10:17:47 +01:00
|
|
|
{
|
2009-06-13 09:52:14 +02:00
|
|
|
u16 csr;
|
|
|
|
|
|
|
|
if (!dev->pm_cap)
|
|
|
|
return -ENOTTY;
|
2008-11-11 10:17:47 +01:00
|
|
|
|
2009-06-13 09:52:14 +02:00
|
|
|
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
|
|
|
|
if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
|
|
|
|
return -ENOTTY;
|
2008-11-11 10:17:47 +01:00
|
|
|
|
2009-06-13 09:52:14 +02:00
|
|
|
if (probe)
|
|
|
|
return 0;
|
2008-11-11 10:17:48 +01:00
|
|
|
|
2009-06-13 09:52:14 +02:00
|
|
|
if (dev->current_state != PCI_D0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
csr &= ~PCI_PM_CTRL_STATE_MASK;
|
|
|
|
csr |= PCI_D3hot;
|
|
|
|
pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
|
2009-12-31 12:15:54 +01:00
|
|
|
pci_dev_d3_sleep(dev);
|
2009-06-13 09:52:14 +02:00
|
|
|
|
|
|
|
csr &= ~PCI_PM_CTRL_STATE_MASK;
|
|
|
|
csr |= PCI_D0;
|
|
|
|
pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
|
2009-12-31 12:15:54 +01:00
|
|
|
pci_dev_d3_sleep(dev);
|
2009-06-13 09:52:14 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-06-13 09:52:15 +02:00
|
|
|
static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
|
|
|
|
{
|
|
|
|
u16 ctrl;
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
|
2009-06-26 08:04:46 +02:00
|
|
|
if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
|
2009-06-13 09:52:15 +02:00
|
|
|
return -ENOTTY;
|
|
|
|
|
|
|
|
list_for_each_entry(pdev, &dev->bus->devices, bus_list)
|
|
|
|
if (pdev != dev)
|
|
|
|
return -ENOTTY;
|
|
|
|
|
|
|
|
if (probe)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
|
|
|
|
ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
|
|
|
|
pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
|
|
|
|
msleep(100);
|
|
|
|
|
|
|
|
ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
|
|
|
|
pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
|
|
|
|
msleep(100);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-04-24 21:15:18 +02:00
|
|
|
static int __pci_dev_reset(struct pci_dev *dev, int probe)
|
2008-11-11 10:17:47 +01:00
|
|
|
{
|
2009-06-13 09:52:13 +02:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
might_sleep();
|
|
|
|
|
2009-12-07 06:03:21 +01:00
|
|
|
rc = pci_dev_specific_reset(dev, probe);
|
|
|
|
if (rc != -ENOTTY)
|
|
|
|
goto done;
|
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
rc = pcie_flr(dev, probe);
|
|
|
|
if (rc != -ENOTTY)
|
|
|
|
goto done;
|
2008-11-11 10:17:47 +01:00
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
rc = pci_af_flr(dev, probe);
|
2009-06-13 09:52:14 +02:00
|
|
|
if (rc != -ENOTTY)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
rc = pci_pm_reset(dev, probe);
|
2009-06-13 09:52:15 +02:00
|
|
|
if (rc != -ENOTTY)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
rc = pci_parent_bus_reset(dev, probe);
|
2009-06-13 09:52:13 +02:00
|
|
|
done:
|
2012-04-24 21:15:18 +02:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_dev_reset(struct pci_dev *dev, int probe)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (!probe) {
|
|
|
|
pci_cfg_access_lock(dev);
|
|
|
|
/* block PM suspend, driver probe, etc. */
|
|
|
|
device_lock(&dev->dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = __pci_dev_reset(dev, probe);
|
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
if (!probe) {
|
2010-02-17 19:57:05 +01:00
|
|
|
device_unlock(&dev->dev);
|
2011-11-04 09:45:59 +01:00
|
|
|
pci_cfg_access_unlock(dev);
|
2009-06-13 09:52:13 +02:00
|
|
|
}
|
|
|
|
return rc;
|
2008-11-11 10:17:47 +01:00
|
|
|
}
|
|
|
|
/**
|
2009-06-13 09:52:13 +02:00
|
|
|
* __pci_reset_function - reset a PCI device function
|
|
|
|
* @dev: PCI device to reset
|
2008-11-11 10:17:47 +01:00
|
|
|
*
|
|
|
|
* Some devices allow an individual function to be reset without affecting
|
|
|
|
* other functions in the same device. The PCI device must be responsive
|
|
|
|
* to PCI config space in order to use this function.
|
|
|
|
*
|
|
|
|
* The device function is presumed to be unused when this function is called.
|
|
|
|
* Resetting the device will make the contents of PCI configuration space
|
|
|
|
* random, so any caller of this must be prepared to reinitialise the
|
|
|
|
* device including MSI, bus mastering, BARs, decoding IO and memory spaces,
|
|
|
|
* etc.
|
|
|
|
*
|
2009-06-13 09:52:13 +02:00
|
|
|
* Returns 0 if the device function was successfully reset or negative if the
|
2008-11-11 10:17:47 +01:00
|
|
|
* device doesn't support resetting a single function.
|
|
|
|
*/
|
2009-06-13 09:52:13 +02:00
|
|
|
int __pci_reset_function(struct pci_dev *dev)
|
2008-11-11 10:17:47 +01:00
|
|
|
{
|
2009-06-13 09:52:13 +02:00
|
|
|
return pci_dev_reset(dev, 0);
|
2008-11-11 10:17:47 +01:00
|
|
|
}
|
2009-06-13 09:52:13 +02:00
|
|
|
EXPORT_SYMBOL_GPL(__pci_reset_function);
|
2008-10-21 11:38:25 +02:00
|
|
|
|
2012-01-12 18:06:46 +01:00
|
|
|
/**
|
|
|
|
* __pci_reset_function_locked - reset a PCI device function while holding
|
|
|
|
* the @dev mutex lock.
|
|
|
|
* @dev: PCI device to reset
|
|
|
|
*
|
|
|
|
* Some devices allow an individual function to be reset without affecting
|
|
|
|
* other functions in the same device. The PCI device must be responsive
|
|
|
|
* to PCI config space in order to use this function.
|
|
|
|
*
|
|
|
|
* The device function is presumed to be unused and the caller is holding
|
|
|
|
* the device mutex lock when this function is called.
|
|
|
|
* Resetting the device will make the contents of PCI configuration space
|
|
|
|
* random, so any caller of this must be prepared to reinitialise the
|
|
|
|
* device including MSI, bus mastering, BARs, decoding IO and memory spaces,
|
|
|
|
* etc.
|
|
|
|
*
|
|
|
|
* Returns 0 if the device function was successfully reset or negative if the
|
|
|
|
* device doesn't support resetting a single function.
|
|
|
|
*/
|
|
|
|
int __pci_reset_function_locked(struct pci_dev *dev)
|
|
|
|
{
|
2012-04-24 21:15:18 +02:00
|
|
|
return __pci_dev_reset(dev, 0);
|
2012-01-12 18:06:46 +01:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
|
|
|
|
|
2009-07-27 22:37:48 +02:00
|
|
|
/**
|
|
|
|
* pci_probe_reset_function - check whether the device can be safely reset
|
|
|
|
* @dev: PCI device to reset
|
|
|
|
*
|
|
|
|
* Some devices allow an individual function to be reset without affecting
|
|
|
|
* other functions in the same device. The PCI device must be responsive
|
|
|
|
* to PCI config space in order to use this function.
|
|
|
|
*
|
|
|
|
* Returns 0 if the device function can be reset or negative if the
|
|
|
|
* device doesn't support resetting a single function.
|
|
|
|
*/
|
|
|
|
int pci_probe_reset_function(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return pci_dev_reset(dev, 1);
|
|
|
|
}
|
|
|
|
|
2008-10-21 11:38:25 +02:00
|
|
|
/**
|
2009-06-13 09:52:13 +02:00
|
|
|
* pci_reset_function - quiesce and reset a PCI device function
|
|
|
|
* @dev: PCI device to reset
|
2008-10-21 11:38:25 +02:00
|
|
|
*
|
|
|
|
* Some devices allow an individual function to be reset without affecting
|
|
|
|
* other functions in the same device. The PCI device must be responsive
|
|
|
|
* to PCI config space in order to use this function.
|
|
|
|
*
|
|
|
|
* This function does not just reset the PCI portion of a device, but
|
|
|
|
* clears all the state associated with the device. This function differs
|
2009-06-13 09:52:13 +02:00
|
|
|
* from __pci_reset_function in that it saves and restores device state
|
2008-10-21 11:38:25 +02:00
|
|
|
* over the reset.
|
|
|
|
*
|
2009-06-13 09:52:13 +02:00
|
|
|
* Returns 0 if the device function was successfully reset or negative if the
|
2008-10-21 11:38:25 +02:00
|
|
|
* device doesn't support resetting a single function.
|
|
|
|
*/
|
|
|
|
int pci_reset_function(struct pci_dev *dev)
|
|
|
|
{
|
2009-06-13 09:52:13 +02:00
|
|
|
int rc;
|
2008-10-21 11:38:25 +02:00
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
rc = pci_dev_reset(dev, 1);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2008-10-21 11:38:25 +02:00
|
|
|
|
|
|
|
pci_save_state(dev);
|
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
/*
|
|
|
|
* both INTx and MSI are disabled after the Interrupt Disable bit
|
|
|
|
* is set and the Bus Master bit is cleared.
|
|
|
|
*/
|
2008-10-21 11:38:25 +02:00
|
|
|
pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
|
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
rc = pci_dev_reset(dev, 0);
|
2008-10-21 11:38:25 +02:00
|
|
|
|
|
|
|
pci_restore_state(dev);
|
|
|
|
|
2009-06-13 09:52:13 +02:00
|
|
|
return rc;
|
2008-10-21 11:38:25 +02:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_reset_function);
|
|
|
|
|
2007-05-15 13:59:13 +02:00
|
|
|
/**
|
|
|
|
* pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
|
|
|
|
* @dev: PCI device to query
|
|
|
|
*
|
|
|
|
* Returns mmrbc: maximum designed memory read count in bytes
|
|
|
|
* or appropriate error value.
|
|
|
|
*/
|
|
|
|
int pcix_get_max_mmrbc(struct pci_dev *dev)
|
|
|
|
{
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
int cap;
|
2007-05-15 13:59:13 +02:00
|
|
|
u32 stat;
|
|
|
|
|
|
|
|
cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (!cap)
|
|
|
|
return -EINVAL;
|
|
|
|
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
|
2007-05-15 13:59:13 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
PCI: fix return value from pcix_get_max_mmrbc()
For the PCI_X_STATUS register, pcix_get_max_mmrbc() is returning an incorrect
value, which is based on:
(stat & PCI_X_STATUS_MAX_READ) >> 12
Valid return values are 512, 1024, 2048, 4096, which correspond to a 'stat'
(masked and right shifted by 21) of 0, 1, 2, 3, respectively.
A right shift by 11 would generate the correct return value when 'stat' (masked
and right shifted by 21) has a value of 1 or 2. But for a value of 0 or 3 it's
not possible to generate the correct return value by only right shifting.
Fix is based on pcix_get_mmrbc()'s similar dealings with the PCI_X_CMD register.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:40 +01:00
|
|
|
return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
|
2007-05-15 13:59:13 +02:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcix_get_max_mmrbc);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcix_get_mmrbc - get PCI-X maximum memory read byte count
|
|
|
|
* @dev: PCI device to query
|
|
|
|
*
|
|
|
|
* Returns mmrbc: maximum memory read count in bytes
|
|
|
|
* or appropriate error value.
|
|
|
|
*/
|
|
|
|
int pcix_get_mmrbc(struct pci_dev *dev)
|
|
|
|
{
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
int cap;
|
PCI: fix access of PCI_X_CMD by pcix get and set mmrbc functions
An e1000 driver on a system with a PCI-X bus was always being returned
a value of 135 from both pcix_get_mmrbc() and pcix_set_mmrbc(). This
value reflects an error return of PCIBIOS_BAD_REGISTER_NUMBER from
pci_bus_read_config_dword(,, cap + PCI_X_CMD,).
This is because for a dword, the following portion of the PCI_OP_READ()
macro:
if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;
expands to:
if (pos & 3) return PCIBIOS_BAD_REGISTER_NUMBER;
And is always true for 'cap + PCI_X_CMD', which is 0xe4 + 2 = 0xe6. ('cap' is
the result of calling pci_find_capability(, PCI_CAP_ID_PCIX).)
The same problem exists for pci_bus_write_config_dword(,, cap + PCI_X_CMD,).
In both cases, instead of calling _dword(), _word() should be called.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:48 +01:00
|
|
|
u16 cmd;
|
2007-05-15 13:59:13 +02:00
|
|
|
|
|
|
|
cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (!cap)
|
|
|
|
return -EINVAL;
|
|
|
|
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
|
|
|
|
return -EINVAL;
|
2007-05-15 13:59:13 +02:00
|
|
|
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
|
2007-05-15 13:59:13 +02:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcix_get_mmrbc);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcix_set_mmrbc - set PCI-X maximum memory read byte count
|
|
|
|
* @dev: PCI device to query
|
|
|
|
* @mmrbc: maximum memory read count in bytes
|
|
|
|
* valid values are 512, 1024, 2048, 4096
|
|
|
|
*
|
|
|
|
* If possible sets maximum memory read byte count, some bridges have erratas
|
|
|
|
* that prevent this.
|
|
|
|
*/
|
|
|
|
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
|
|
|
|
{
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
int cap;
|
PCI: fix access of PCI_X_CMD by pcix get and set mmrbc functions
An e1000 driver on a system with a PCI-X bus was always being returned
a value of 135 from both pcix_get_mmrbc() and pcix_set_mmrbc(). This
value reflects an error return of PCIBIOS_BAD_REGISTER_NUMBER from
pci_bus_read_config_dword(,, cap + PCI_X_CMD,).
This is because for a dword, the following portion of the PCI_OP_READ()
macro:
if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;
expands to:
if (pos & 3) return PCIBIOS_BAD_REGISTER_NUMBER;
And is always true for 'cap + PCI_X_CMD', which is 0xe4 + 2 = 0xe6. ('cap' is
the result of calling pci_find_capability(, PCI_CAP_ID_PCIX).)
The same problem exists for pci_bus_write_config_dword(,, cap + PCI_X_CMD,).
In both cases, instead of calling _dword(), _word() should be called.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:48 +01:00
|
|
|
u32 stat, v, o;
|
|
|
|
u16 cmd;
|
2007-05-15 13:59:13 +02:00
|
|
|
|
2007-08-13 14:53:14 +02:00
|
|
|
if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
return -EINVAL;
|
2007-05-15 13:59:13 +02:00
|
|
|
|
|
|
|
v = ffs(mmrbc) - 10;
|
|
|
|
|
|
|
|
cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (!cap)
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
return -EINVAL;
|
2007-05-15 13:59:13 +02:00
|
|
|
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
|
|
|
|
return -EINVAL;
|
2007-05-15 13:59:13 +02:00
|
|
|
|
|
|
|
if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
|
|
|
|
return -E2BIG;
|
|
|
|
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
|
|
|
|
return -EINVAL;
|
2007-05-15 13:59:13 +02:00
|
|
|
|
|
|
|
o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
|
|
|
|
if (o != v) {
|
2012-06-21 00:41:16 +02:00
|
|
|
if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
|
2007-05-15 13:59:13 +02:00
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
cmd &= ~PCI_X_CMD_MAX_READ;
|
|
|
|
cmd |= v << 2;
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
|
|
|
|
return -EIO;
|
2007-05-15 13:59:13 +02:00
|
|
|
}
|
PCI: cleanup error return for pcix get and set mmrbc functions
pcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if
successful, or an appropriate error value, if not.
Distinguishing errors from correct values and understanding the meaning of an
error can be somewhat confusing in that:
correct values: 512, 1024, 2048, 4096
errors: -EINVAL -22
PCIBIOS_FUNC_NOT_SUPPORTED 0x81
PCIBIOS_BAD_VENDOR_ID 0x83
PCIBIOS_DEVICE_NOT_FOUND 0x86
PCIBIOS_BAD_REGISTER_NUMBER 0x87
PCIBIOS_SET_FAILED 0x88
PCIBIOS_BUFFER_TOO_SMALL 0x89
The PCIBIOS_ errors are returned from the PCI functions generated by the
PCI_OP_READ() and PCI_OP_WRITE() macros.
In a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values
returned from pci_read_config_[word|dword]() and pci_write_config_word().
Following pcix_get_max_mmrbc()'s example, the following patch simply returns
-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL
or -EIO for those encountered by pcix_set_mmrbc().
This simplification was chosen in light of the fact that none of the current
callers of these functions are interested in the specific type of error
encountered. In the future, should this change, one could simply create a
function that maps each PCIBIOS_ error to a corresponding unique errno value,
which could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and
pcix_set_mmrbc().
Additionally, this patch eliminates some unnecessary variables.
Cc: stable@kernel.org
Signed-off-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-03-10 04:26:55 +01:00
|
|
|
return 0;
|
2007-05-15 13:59:13 +02:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcix_set_mmrbc);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcie_get_readrq - get PCI Express read request size
|
|
|
|
* @dev: PCI device to query
|
|
|
|
*
|
|
|
|
* Returns maximum memory read request in bytes
|
|
|
|
* or appropriate error value.
|
|
|
|
*/
|
|
|
|
int pcie_get_readrq(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int ret, cap;
|
|
|
|
u16 ctl;
|
|
|
|
|
2009-11-11 06:30:56 +01:00
|
|
|
cap = pci_pcie_cap(dev);
|
2007-05-15 13:59:13 +02:00
|
|
|
if (!cap)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
|
|
|
if (!ret)
|
2010-08-05 22:23:16 +02:00
|
|
|
ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
|
2007-05-15 13:59:13 +02:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_get_readrq);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcie_set_readrq - set PCI Express maximum memory read request
|
|
|
|
* @dev: PCI device to query
|
2007-07-24 06:42:11 +02:00
|
|
|
* @rq: maximum memory read count in bytes
|
2007-05-15 13:59:13 +02:00
|
|
|
* valid values are 128, 256, 512, 1024, 2048, 4096
|
|
|
|
*
|
2011-06-29 01:26:25 +02:00
|
|
|
* If possible sets maximum memory read request in bytes
|
2007-05-15 13:59:13 +02:00
|
|
|
*/
|
|
|
|
int pcie_set_readrq(struct pci_dev *dev, int rq)
|
|
|
|
{
|
|
|
|
int cap, err = -EINVAL;
|
|
|
|
u16 ctl, v;
|
|
|
|
|
2007-08-13 14:53:14 +02:00
|
|
|
if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
|
2007-05-15 13:59:13 +02:00
|
|
|
goto out;
|
|
|
|
|
2009-11-11 06:30:56 +01:00
|
|
|
cap = pci_pcie_cap(dev);
|
2007-05-15 13:59:13 +02:00
|
|
|
if (!cap)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
2011-10-14 21:56:15 +02:00
|
|
|
/*
|
|
|
|
* If using the "performance" PCIe config, we clamp the
|
|
|
|
* read rq size to the max packet size to prevent the
|
|
|
|
* host bridge generating requests larger than we can
|
|
|
|
* cope with
|
|
|
|
*/
|
|
|
|
if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
|
|
|
|
int mps = pcie_get_mps(dev);
|
|
|
|
|
|
|
|
if (mps < 0)
|
|
|
|
return mps;
|
|
|
|
if (mps < rq)
|
|
|
|
rq = mps;
|
|
|
|
}
|
|
|
|
|
|
|
|
v = (ffs(rq) - 8) << 12;
|
2007-05-15 13:59:13 +02:00
|
|
|
|
|
|
|
if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
|
|
|
|
ctl &= ~PCI_EXP_DEVCTL_READRQ;
|
|
|
|
ctl |= v;
|
2011-06-29 01:26:25 +02:00
|
|
|
err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
|
2007-05-15 13:59:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_set_readrq);
|
|
|
|
|
PCI: Set PCI-E Max Payload Size on fabric
On a given PCI-E fabric, each device, bridge, and root port can have a
different PCI-E maximum payload size. There is a sizable performance
boost for having the largest possible maximum payload size on each PCI-E
device. However, if improperly configured, fatal bus errors can occur.
Thus, it is important to ensure that PCI-E payloads sends by a device
are never larger than the MPS setting of all devices on the way to the
destination.
This can be achieved two ways:
- A conservative approach is to use the smallest common denominator of
the entire tree below a root complex for every device on that fabric.
This means for example that having a 128 bytes MPS USB controller on one
leg of a switch will dramatically reduce performances of a video card or
10GE adapter on another leg of that same switch.
It also means that any hierarchy supporting hotplug slots (including
expresscard or thunderbolt I suppose, dbl check that) will have to be
entirely clamped to 128 bytes since we cannot predict what will be
plugged into those slots, and we cannot change the MPS on a "live"
system.
- A more optimal way is possible, if it falls within a couple of
constraints:
* The top-level host bridge will never generate packets larger than the
smallest TLP (or if it can be controlled independently from its MPS at
least)
* The device will never generate packets larger than MPS (which can be
configured via MRRS)
* No support of direct PCI-E <-> PCI-E transfers between devices without
some additional code to specifically deal with that case
Then we can use an approach that basically ignores downstream requests
and focuses exclusively on upstream requests. In that case, all we need
to care about is that a device MPS is no larger than its parent MPS,
which allows us to keep all switches/bridges to the max MPS supported by
their parent and eventually the PHB.
In this case, your USB controller would no longer "starve" your 10GE
Ethernet and your hotplug slots won't affect your global MPS.
Additionally, the hotplugged devices themselves can be configured to a
larger MPS up to the value configured in the hotplug bridge.
To choose between the two available options, two PCI kernel boot args
have been added to the PCI calls. "pcie_bus_safe" will provide the
former behavior, while "pcie_bus_perf" will perform the latter behavior.
By default, the latter behavior is used.
NOTE: due to the location of the enablement, each arch will need to add
calls to this function. This patch only enables x86.
This patch includes a number of changes recommended by Benjamin
Herrenschmidt.
Tested-by: Jordan_Hargrave@dell.com
Signed-off-by: Jon Mason <mason@myri.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-20 22:20:54 +02:00
|
|
|
/**
|
|
|
|
* pcie_get_mps - get PCI Express maximum payload size
|
|
|
|
* @dev: PCI device to query
|
|
|
|
*
|
|
|
|
* Returns maximum payload size in bytes
|
|
|
|
* or appropriate error value.
|
|
|
|
*/
|
|
|
|
int pcie_get_mps(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int ret, cap;
|
|
|
|
u16 ctl;
|
|
|
|
|
|
|
|
cap = pci_pcie_cap(dev);
|
|
|
|
if (!cap)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
|
|
|
if (!ret)
|
|
|
|
ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcie_set_mps - set PCI Express maximum payload size
|
|
|
|
* @dev: PCI device to query
|
2011-08-20 20:49:43 +02:00
|
|
|
* @mps: maximum payload size in bytes
|
PCI: Set PCI-E Max Payload Size on fabric
On a given PCI-E fabric, each device, bridge, and root port can have a
different PCI-E maximum payload size. There is a sizable performance
boost for having the largest possible maximum payload size on each PCI-E
device. However, if improperly configured, fatal bus errors can occur.
Thus, it is important to ensure that PCI-E payloads sends by a device
are never larger than the MPS setting of all devices on the way to the
destination.
This can be achieved two ways:
- A conservative approach is to use the smallest common denominator of
the entire tree below a root complex for every device on that fabric.
This means for example that having a 128 bytes MPS USB controller on one
leg of a switch will dramatically reduce performances of a video card or
10GE adapter on another leg of that same switch.
It also means that any hierarchy supporting hotplug slots (including
expresscard or thunderbolt I suppose, dbl check that) will have to be
entirely clamped to 128 bytes since we cannot predict what will be
plugged into those slots, and we cannot change the MPS on a "live"
system.
- A more optimal way is possible, if it falls within a couple of
constraints:
* The top-level host bridge will never generate packets larger than the
smallest TLP (or if it can be controlled independently from its MPS at
least)
* The device will never generate packets larger than MPS (which can be
configured via MRRS)
* No support of direct PCI-E <-> PCI-E transfers between devices without
some additional code to specifically deal with that case
Then we can use an approach that basically ignores downstream requests
and focuses exclusively on upstream requests. In that case, all we need
to care about is that a device MPS is no larger than its parent MPS,
which allows us to keep all switches/bridges to the max MPS supported by
their parent and eventually the PHB.
In this case, your USB controller would no longer "starve" your 10GE
Ethernet and your hotplug slots won't affect your global MPS.
Additionally, the hotplugged devices themselves can be configured to a
larger MPS up to the value configured in the hotplug bridge.
To choose between the two available options, two PCI kernel boot args
have been added to the PCI calls. "pcie_bus_safe" will provide the
former behavior, while "pcie_bus_perf" will perform the latter behavior.
By default, the latter behavior is used.
NOTE: due to the location of the enablement, each arch will need to add
calls to this function. This patch only enables x86.
This patch includes a number of changes recommended by Benjamin
Herrenschmidt.
Tested-by: Jordan_Hargrave@dell.com
Signed-off-by: Jon Mason <mason@myri.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-20 22:20:54 +02:00
|
|
|
* valid values are 128, 256, 512, 1024, 2048, 4096
|
|
|
|
*
|
|
|
|
* If possible sets maximum payload size
|
|
|
|
*/
|
|
|
|
int pcie_set_mps(struct pci_dev *dev, int mps)
|
|
|
|
{
|
|
|
|
int cap, err = -EINVAL;
|
|
|
|
u16 ctl, v;
|
|
|
|
|
|
|
|
if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
v = ffs(mps) - 8;
|
|
|
|
if (v > dev->pcie_mpss)
|
|
|
|
goto out;
|
|
|
|
v <<= 5;
|
|
|
|
|
|
|
|
cap = pci_pcie_cap(dev);
|
|
|
|
if (!cap)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
|
|
|
|
ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
|
|
|
|
ctl |= v;
|
|
|
|
err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2006-12-18 02:31:06 +01:00
|
|
|
/**
|
|
|
|
* pci_select_bars - Make BAR mask from the type of resource
|
2007-02-10 23:41:56 +01:00
|
|
|
* @dev: the PCI device for which BAR mask is made
|
2006-12-18 02:31:06 +01:00
|
|
|
* @flags: resource type mask to be selected
|
|
|
|
*
|
|
|
|
* This helper routine makes bar mask from the type of resource.
|
|
|
|
*/
|
|
|
|
int pci_select_bars(struct pci_dev *dev, unsigned long flags)
|
|
|
|
{
|
|
|
|
int i, bars = 0;
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++)
|
|
|
|
if (pci_resource_flags(dev, i) & flags)
|
|
|
|
bars |= (1 << i);
|
|
|
|
return bars;
|
|
|
|
}
|
|
|
|
|
2008-11-21 19:41:27 +01:00
|
|
|
/**
|
|
|
|
* pci_resource_bar - get position of the BAR associated with a resource
|
|
|
|
* @dev: the PCI device
|
|
|
|
* @resno: the resource number
|
|
|
|
* @type: the BAR type to be filled in
|
|
|
|
*
|
|
|
|
* Returns BAR position in config space, or 0 if the BAR is invalid.
|
|
|
|
*/
|
|
|
|
int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
|
|
|
|
{
|
2009-03-20 04:25:11 +01:00
|
|
|
int reg;
|
|
|
|
|
2008-11-21 19:41:27 +01:00
|
|
|
if (resno < PCI_ROM_RESOURCE) {
|
|
|
|
*type = pci_bar_unknown;
|
|
|
|
return PCI_BASE_ADDRESS_0 + 4 * resno;
|
|
|
|
} else if (resno == PCI_ROM_RESOURCE) {
|
|
|
|
*type = pci_bar_mem32;
|
|
|
|
return dev->rom_base_reg;
|
2009-03-20 04:25:11 +01:00
|
|
|
} else if (resno < PCI_BRIDGE_RESOURCES) {
|
|
|
|
/* device specific resource */
|
|
|
|
reg = pci_iov_resource_bar(dev, resno, type);
|
|
|
|
if (reg)
|
|
|
|
return reg;
|
2008-11-21 19:41:27 +01:00
|
|
|
}
|
|
|
|
|
2009-11-04 18:32:57 +01:00
|
|
|
dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
|
2008-11-21 19:41:27 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-02-02 23:38:13 +01:00
|
|
|
/* Some architectures require additional programming to enable VGA */
|
|
|
|
static arch_set_vga_state_t arch_set_vga_state;
|
|
|
|
|
|
|
|
void __init pci_register_set_vga_state(arch_set_vga_state_t func)
|
|
|
|
{
|
|
|
|
arch_set_vga_state = func; /* NULL disables */
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
|
2011-05-25 06:00:49 +02:00
|
|
|
unsigned int command_bits, u32 flags)
|
2010-02-02 23:38:13 +01:00
|
|
|
{
|
|
|
|
if (arch_set_vga_state)
|
|
|
|
return arch_set_vga_state(dev, decode, command_bits,
|
2011-05-25 06:00:49 +02:00
|
|
|
flags);
|
2010-02-02 23:38:13 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-08-11 07:52:06 +02:00
|
|
|
/**
|
|
|
|
* pci_set_vga_state - set VGA decode state on device and parents if requested
|
2009-09-18 00:28:22 +02:00
|
|
|
* @dev: the PCI device
|
|
|
|
* @decode: true = enable decoding, false = disable decoding
|
|
|
|
* @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
|
2011-05-26 04:21:25 +02:00
|
|
|
* @flags: traverse ancestors and change bridges
|
2010-06-01 07:32:24 +02:00
|
|
|
* CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
|
2009-08-11 07:52:06 +02:00
|
|
|
*/
|
|
|
|
int pci_set_vga_state(struct pci_dev *dev, bool decode,
|
2010-06-01 07:32:24 +02:00
|
|
|
unsigned int command_bits, u32 flags)
|
2009-08-11 07:52:06 +02:00
|
|
|
{
|
|
|
|
struct pci_bus *bus;
|
|
|
|
struct pci_dev *bridge;
|
|
|
|
u16 cmd;
|
2010-02-02 23:38:13 +01:00
|
|
|
int rc;
|
2009-08-11 07:52:06 +02:00
|
|
|
|
2010-06-01 07:32:24 +02:00
|
|
|
WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
|
2009-08-11 07:52:06 +02:00
|
|
|
|
2010-02-02 23:38:13 +01:00
|
|
|
/* ARCH specific VGA enables */
|
2010-06-01 07:32:24 +02:00
|
|
|
rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
|
2010-02-02 23:38:13 +01:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2010-06-01 07:32:24 +02:00
|
|
|
if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
|
|
if (decode == true)
|
|
|
|
cmd |= command_bits;
|
|
|
|
else
|
|
|
|
cmd &= ~command_bits;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
|
|
}
|
2009-08-11 07:52:06 +02:00
|
|
|
|
2010-06-01 07:32:24 +02:00
|
|
|
if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
|
2009-08-11 07:52:06 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
bus = dev->bus;
|
|
|
|
while (bus) {
|
|
|
|
bridge = bus->self;
|
|
|
|
if (bridge) {
|
|
|
|
pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
|
|
|
|
&cmd);
|
|
|
|
if (decode == true)
|
|
|
|
cmd |= PCI_BRIDGE_CTL_VGA;
|
|
|
|
else
|
|
|
|
cmd &= ~PCI_BRIDGE_CTL_VGA;
|
|
|
|
pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
|
|
|
|
cmd);
|
|
|
|
}
|
|
|
|
bus = bus->parent;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-03-16 09:13:39 +01:00
|
|
|
#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
|
|
|
|
static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
|
2009-11-06 23:41:23 +01:00
|
|
|
static DEFINE_SPINLOCK(resource_alignment_lock);
|
2009-03-16 09:13:39 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_specified_resource_alignment - get resource alignment specified by user.
|
|
|
|
* @dev: the PCI device to get
|
|
|
|
*
|
|
|
|
* RETURNS: Resource alignment if it is specified.
|
|
|
|
* Zero if it is not specified.
|
|
|
|
*/
|
|
|
|
resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int seg, bus, slot, func, align_order, count;
|
|
|
|
resource_size_t align = 0;
|
|
|
|
char *p;
|
|
|
|
|
|
|
|
spin_lock(&resource_alignment_lock);
|
|
|
|
p = resource_alignment_param;
|
|
|
|
while (*p) {
|
|
|
|
count = 0;
|
|
|
|
if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
|
|
|
|
p[count] == '@') {
|
|
|
|
p += count + 1;
|
|
|
|
} else {
|
|
|
|
align_order = -1;
|
|
|
|
}
|
|
|
|
if (sscanf(p, "%x:%x:%x.%x%n",
|
|
|
|
&seg, &bus, &slot, &func, &count) != 4) {
|
|
|
|
seg = 0;
|
|
|
|
if (sscanf(p, "%x:%x.%x%n",
|
|
|
|
&bus, &slot, &func, &count) != 3) {
|
|
|
|
/* Invalid format */
|
|
|
|
printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
|
|
|
|
p);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
p += count;
|
|
|
|
if (seg == pci_domain_nr(dev->bus) &&
|
|
|
|
bus == dev->bus->number &&
|
|
|
|
slot == PCI_SLOT(dev->devfn) &&
|
|
|
|
func == PCI_FUNC(dev->devfn)) {
|
|
|
|
if (align_order == -1) {
|
|
|
|
align = PAGE_SIZE;
|
|
|
|
} else {
|
|
|
|
align = 1 << align_order;
|
|
|
|
}
|
|
|
|
/* Found */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (*p != ';' && *p != ',') {
|
|
|
|
/* End of param or invalid format */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
p++;
|
|
|
|
}
|
|
|
|
spin_unlock(&resource_alignment_lock);
|
|
|
|
return align;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_is_reassigndev - check if specified PCI is target device to reassign
|
|
|
|
* @dev: the PCI device to check
|
|
|
|
*
|
|
|
|
* RETURNS: non-zero for PCI device is a target device to reassign,
|
|
|
|
* or zero is not.
|
|
|
|
*/
|
|
|
|
int pci_is_reassigndev(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return (pci_specified_resource_alignment(dev) != 0);
|
|
|
|
}
|
|
|
|
|
2012-02-16 06:40:31 +01:00
|
|
|
/*
|
|
|
|
* This function disables memory decoding and releases memory resources
|
|
|
|
* of the device specified by kernel's boot parameter 'pci=resource_alignment='.
|
|
|
|
* It also rounds up size to specified alignment.
|
|
|
|
* Later on, the kernel will assign page-aligned memory resource back
|
|
|
|
* to the device.
|
|
|
|
*/
|
|
|
|
void pci_reassigndev_resource_alignment(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct resource *r;
|
|
|
|
resource_size_t align, size;
|
|
|
|
u16 command;
|
|
|
|
|
|
|
|
if (!pci_is_reassigndev(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
|
|
|
|
(dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
|
|
|
|
dev_warn(&dev->dev,
|
|
|
|
"Can't reassign resources to host bridge.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_info(&dev->dev,
|
|
|
|
"Disabling memory decoding and releasing memory resources.\n");
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &command);
|
|
|
|
command &= ~PCI_COMMAND_MEMORY;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, command);
|
|
|
|
|
|
|
|
align = pci_specified_resource_alignment(dev);
|
|
|
|
for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
|
|
|
|
r = &dev->resource[i];
|
|
|
|
if (!(r->flags & IORESOURCE_MEM))
|
|
|
|
continue;
|
|
|
|
size = resource_size(r);
|
|
|
|
if (size < align) {
|
|
|
|
size = align;
|
|
|
|
dev_info(&dev->dev,
|
|
|
|
"Rounding up size of resource #%d to %#llx.\n",
|
|
|
|
i, (unsigned long long)size);
|
|
|
|
}
|
|
|
|
r->end = size - 1;
|
|
|
|
r->start = 0;
|
|
|
|
}
|
|
|
|
/* Need to disable bridge's resource window,
|
|
|
|
* to enable the kernel to reassign new resource
|
|
|
|
* window later on.
|
|
|
|
*/
|
|
|
|
if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
|
|
|
|
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
|
|
|
|
for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
|
|
|
|
r = &dev->resource[i];
|
|
|
|
if (!(r->flags & IORESOURCE_MEM))
|
|
|
|
continue;
|
|
|
|
r->end = resource_size(r) - 1;
|
|
|
|
r->start = 0;
|
|
|
|
}
|
|
|
|
pci_disable_bridge_window(dev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-03-16 09:13:39 +01:00
|
|
|
ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
|
|
|
|
{
|
|
|
|
if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
|
|
|
|
count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
|
|
|
|
spin_lock(&resource_alignment_lock);
|
|
|
|
strncpy(resource_alignment_param, buf, count);
|
|
|
|
resource_alignment_param[count] = '\0';
|
|
|
|
spin_unlock(&resource_alignment_lock);
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
|
|
|
|
{
|
|
|
|
size_t count;
|
|
|
|
spin_lock(&resource_alignment_lock);
|
|
|
|
count = snprintf(buf, size, "%s", resource_alignment_param);
|
|
|
|
spin_unlock(&resource_alignment_lock);
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
|
|
|
|
{
|
|
|
|
return pci_get_resource_alignment_param(buf, PAGE_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t pci_resource_alignment_store(struct bus_type *bus,
|
|
|
|
const char *buf, size_t count)
|
|
|
|
{
|
|
|
|
return pci_set_resource_alignment_param(buf, count);
|
|
|
|
}
|
|
|
|
|
|
|
|
BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
|
|
|
|
pci_resource_alignment_store);
|
|
|
|
|
|
|
|
static int __init pci_resource_alignment_sysfs_init(void)
|
|
|
|
{
|
|
|
|
return bus_create_file(&pci_bus_type,
|
|
|
|
&bus_attr_resource_alignment);
|
|
|
|
}
|
|
|
|
|
|
|
|
late_initcall(pci_resource_alignment_sysfs_init);
|
|
|
|
|
2007-10-11 22:57:27 +02:00
|
|
|
static void __devinit pci_no_domains(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_PCI_DOMAINS
|
|
|
|
pci_domains_supported = 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2008-11-10 23:30:50 +01:00
|
|
|
/**
|
|
|
|
* pci_ext_cfg_enabled - can we access extended PCI config space?
|
|
|
|
* @dev: The PCI device of the root bridge.
|
|
|
|
*
|
|
|
|
* Returns 1 if we can access PCI extended config space (offsets
|
|
|
|
* greater than 0xff). This is the default implementation. Architecture
|
|
|
|
* implementations can override this.
|
|
|
|
*/
|
2012-06-19 14:54:49 +02:00
|
|
|
int __weak pci_ext_cfg_avail(struct pci_dev *dev)
|
2008-11-10 23:30:50 +01:00
|
|
|
{
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2009-12-09 07:52:13 +01:00
|
|
|
void __weak pci_fixup_cardbus(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_fixup_cardbus);
|
|
|
|
|
2008-11-22 18:37:14 +01:00
|
|
|
static int __init pci_setup(char *str)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
while (str) {
|
|
|
|
char *k = strchr(str, ',');
|
|
|
|
if (k)
|
|
|
|
*k++ = 0;
|
|
|
|
if (*str && (str = pcibios_setup(str)) && *str) {
|
2006-03-06 06:33:34 +01:00
|
|
|
if (!strcmp(str, "nomsi")) {
|
|
|
|
pci_no_msi();
|
2007-10-05 22:17:58 +02:00
|
|
|
} else if (!strcmp(str, "noaer")) {
|
|
|
|
pci_no_aer();
|
2012-02-24 04:23:30 +01:00
|
|
|
} else if (!strncmp(str, "realloc=", 8)) {
|
|
|
|
pci_realloc_get_opt(str + 8);
|
2011-07-07 20:19:10 +02:00
|
|
|
} else if (!strncmp(str, "realloc", 7)) {
|
2012-02-24 04:23:30 +01:00
|
|
|
pci_realloc_get_opt("on");
|
2007-10-11 22:57:27 +02:00
|
|
|
} else if (!strcmp(str, "nodomains")) {
|
|
|
|
pci_no_domains();
|
2012-03-01 00:06:33 +01:00
|
|
|
} else if (!strncmp(str, "noari", 5)) {
|
|
|
|
pcie_ari_disabled = true;
|
2007-02-06 01:36:06 +01:00
|
|
|
} else if (!strncmp(str, "cbiosize=", 9)) {
|
|
|
|
pci_cardbus_io_size = memparse(str + 9, &str);
|
|
|
|
} else if (!strncmp(str, "cbmemsize=", 10)) {
|
|
|
|
pci_cardbus_mem_size = memparse(str + 10, &str);
|
2009-03-16 09:13:39 +01:00
|
|
|
} else if (!strncmp(str, "resource_alignment=", 19)) {
|
|
|
|
pci_set_resource_alignment_param(str + 19,
|
|
|
|
strlen(str + 19));
|
2009-04-23 00:52:09 +02:00
|
|
|
} else if (!strncmp(str, "ecrc=", 5)) {
|
|
|
|
pcie_ecrc_get_policy(str + 5);
|
2009-09-09 23:09:24 +02:00
|
|
|
} else if (!strncmp(str, "hpiosize=", 9)) {
|
|
|
|
pci_hotplug_io_size = memparse(str + 9, &str);
|
|
|
|
} else if (!strncmp(str, "hpmemsize=", 10)) {
|
|
|
|
pci_hotplug_mem_size = memparse(str + 10, &str);
|
2011-10-03 16:50:20 +02:00
|
|
|
} else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
|
|
|
|
pcie_bus_config = PCIE_BUS_TUNE_OFF;
|
PCI: Set PCI-E Max Payload Size on fabric
On a given PCI-E fabric, each device, bridge, and root port can have a
different PCI-E maximum payload size. There is a sizable performance
boost for having the largest possible maximum payload size on each PCI-E
device. However, if improperly configured, fatal bus errors can occur.
Thus, it is important to ensure that PCI-E payloads sends by a device
are never larger than the MPS setting of all devices on the way to the
destination.
This can be achieved two ways:
- A conservative approach is to use the smallest common denominator of
the entire tree below a root complex for every device on that fabric.
This means for example that having a 128 bytes MPS USB controller on one
leg of a switch will dramatically reduce performances of a video card or
10GE adapter on another leg of that same switch.
It also means that any hierarchy supporting hotplug slots (including
expresscard or thunderbolt I suppose, dbl check that) will have to be
entirely clamped to 128 bytes since we cannot predict what will be
plugged into those slots, and we cannot change the MPS on a "live"
system.
- A more optimal way is possible, if it falls within a couple of
constraints:
* The top-level host bridge will never generate packets larger than the
smallest TLP (or if it can be controlled independently from its MPS at
least)
* The device will never generate packets larger than MPS (which can be
configured via MRRS)
* No support of direct PCI-E <-> PCI-E transfers between devices without
some additional code to specifically deal with that case
Then we can use an approach that basically ignores downstream requests
and focuses exclusively on upstream requests. In that case, all we need
to care about is that a device MPS is no larger than its parent MPS,
which allows us to keep all switches/bridges to the max MPS supported by
their parent and eventually the PHB.
In this case, your USB controller would no longer "starve" your 10GE
Ethernet and your hotplug slots won't affect your global MPS.
Additionally, the hotplugged devices themselves can be configured to a
larger MPS up to the value configured in the hotplug bridge.
To choose between the two available options, two PCI kernel boot args
have been added to the PCI calls. "pcie_bus_safe" will provide the
former behavior, while "pcie_bus_perf" will perform the latter behavior.
By default, the latter behavior is used.
NOTE: due to the location of the enablement, each arch will need to add
calls to this function. This patch only enables x86.
This patch includes a number of changes recommended by Benjamin
Herrenschmidt.
Tested-by: Jordan_Hargrave@dell.com
Signed-off-by: Jon Mason <mason@myri.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-20 22:20:54 +02:00
|
|
|
} else if (!strncmp(str, "pcie_bus_safe", 13)) {
|
|
|
|
pcie_bus_config = PCIE_BUS_SAFE;
|
|
|
|
} else if (!strncmp(str, "pcie_bus_perf", 13)) {
|
|
|
|
pcie_bus_config = PCIE_BUS_PERFORMANCE;
|
2011-10-03 16:50:20 +02:00
|
|
|
} else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
|
|
|
|
pcie_bus_config = PCIE_BUS_PEER2PEER;
|
2012-04-30 23:21:02 +02:00
|
|
|
} else if (!strncmp(str, "pcie_scan_all", 13)) {
|
|
|
|
pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
|
2006-03-06 06:33:34 +01:00
|
|
|
} else {
|
|
|
|
printk(KERN_ERR "PCI: Unknown option `%s'\n",
|
|
|
|
str);
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
str = k;
|
|
|
|
}
|
2006-09-26 10:52:41 +02:00
|
|
|
return 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2006-09-26 10:52:41 +02:00
|
|
|
early_param("pci", pci_setup);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-07-27 07:43:35 +02:00
|
|
|
EXPORT_SYMBOL(pci_reenable_device);
|
2007-12-20 05:28:08 +01:00
|
|
|
EXPORT_SYMBOL(pci_enable_device_io);
|
|
|
|
EXPORT_SYMBOL(pci_enable_device_mem);
|
2005-04-17 00:20:36 +02:00
|
|
|
EXPORT_SYMBOL(pci_enable_device);
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 08:00:26 +01:00
|
|
|
EXPORT_SYMBOL(pcim_enable_device);
|
|
|
|
EXPORT_SYMBOL(pcim_pin_device);
|
2005-04-17 00:20:36 +02:00
|
|
|
EXPORT_SYMBOL(pci_disable_device);
|
|
|
|
EXPORT_SYMBOL(pci_find_capability);
|
|
|
|
EXPORT_SYMBOL(pci_bus_find_capability);
|
|
|
|
EXPORT_SYMBOL(pci_release_regions);
|
|
|
|
EXPORT_SYMBOL(pci_request_regions);
|
2008-10-23 04:55:31 +02:00
|
|
|
EXPORT_SYMBOL(pci_request_regions_exclusive);
|
2005-04-17 00:20:36 +02:00
|
|
|
EXPORT_SYMBOL(pci_release_region);
|
|
|
|
EXPORT_SYMBOL(pci_request_region);
|
2008-10-23 04:55:31 +02:00
|
|
|
EXPORT_SYMBOL(pci_request_region_exclusive);
|
2006-12-18 02:31:06 +01:00
|
|
|
EXPORT_SYMBOL(pci_release_selected_regions);
|
|
|
|
EXPORT_SYMBOL(pci_request_selected_regions);
|
2008-10-23 04:55:31 +02:00
|
|
|
EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
|
2005-04-17 00:20:36 +02:00
|
|
|
EXPORT_SYMBOL(pci_set_master);
|
2008-12-23 04:08:29 +01:00
|
|
|
EXPORT_SYMBOL(pci_clear_master);
|
2005-04-17 00:20:36 +02:00
|
|
|
EXPORT_SYMBOL(pci_set_mwi);
|
2007-07-09 20:55:54 +02:00
|
|
|
EXPORT_SYMBOL(pci_try_set_mwi);
|
2005-04-17 00:20:36 +02:00
|
|
|
EXPORT_SYMBOL(pci_clear_mwi);
|
2005-08-15 21:23:41 +02:00
|
|
|
EXPORT_SYMBOL_GPL(pci_intx);
|
2005-04-17 00:20:36 +02:00
|
|
|
EXPORT_SYMBOL(pci_assign_resource);
|
|
|
|
EXPORT_SYMBOL(pci_find_parent_resource);
|
2006-12-18 02:31:06 +01:00
|
|
|
EXPORT_SYMBOL(pci_select_bars);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
EXPORT_SYMBOL(pci_set_power_state);
|
|
|
|
EXPORT_SYMBOL(pci_save_state);
|
|
|
|
EXPORT_SYMBOL(pci_restore_state);
|
2008-07-19 14:39:24 +02:00
|
|
|
EXPORT_SYMBOL(pci_pme_capable);
|
2008-08-08 00:14:24 +02:00
|
|
|
EXPORT_SYMBOL(pci_pme_active);
|
2008-08-18 21:38:00 +02:00
|
|
|
EXPORT_SYMBOL(pci_wake_from_d3);
|
2008-07-19 14:39:24 +02:00
|
|
|
EXPORT_SYMBOL(pci_target_state);
|
2008-07-07 03:35:26 +02:00
|
|
|
EXPORT_SYMBOL(pci_prepare_to_sleep);
|
|
|
|
EXPORT_SYMBOL(pci_back_from_sleep);
|
2007-04-06 23:39:36 +02:00
|
|
|
EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
|