2005-04-17 00:20:36 +02:00
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/*
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* cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
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* M (part of the Centrino chipset).
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*
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2006-06-21 22:15:48 +02:00
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* Since the original Pentium M, most new Intel CPUs support Enhanced
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* SpeedStep.
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*
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2005-04-17 00:20:36 +02:00
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* Despite the "SpeedStep" in the name, this is almost entirely unlike
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* traditional SpeedStep.
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*
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* Modelled on speedstep.c
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*
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* Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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2005-10-31 00:03:48 +01:00
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#include <linux/sched.h> /* current */
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2005-04-17 00:20:36 +02:00
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#include <linux/delay.h>
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#include <linux/compiler.h>
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#include <asm/msr.h>
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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#define PFX "speedstep-centrino: "
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2008-10-09 14:59:17 +02:00
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#define MAINTAINER "cpufreq@vger.kernel.org"
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2005-04-17 00:20:36 +02:00
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2008-07-19 03:11:34 +02:00
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#define dprintk(msg...) \
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cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
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2005-04-17 00:20:36 +02:00
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2006-11-10 20:20:47 +01:00
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#define INTEL_MSR_RANGE (0xffff)
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2005-04-17 00:20:36 +02:00
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struct cpu_id
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{
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__u8 x86; /* CPU family */
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__u8 x86_model; /* model */
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__u8 x86_mask; /* stepping */
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};
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enum {
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CPU_BANIAS,
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CPU_DOTHAN_A1,
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CPU_DOTHAN_A2,
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CPU_DOTHAN_B0,
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2005-06-01 04:03:43 +02:00
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CPU_MP4HT_D0,
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CPU_MP4HT_E0,
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2005-04-17 00:20:36 +02:00
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};
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static const struct cpu_id cpu_ids[] = {
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[CPU_BANIAS] = { 6, 9, 5 },
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[CPU_DOTHAN_A1] = { 6, 13, 1 },
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[CPU_DOTHAN_A2] = { 6, 13, 2 },
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[CPU_DOTHAN_B0] = { 6, 13, 6 },
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2005-06-01 04:03:43 +02:00
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[CPU_MP4HT_D0] = {15, 3, 4 },
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[CPU_MP4HT_E0] = {15, 4, 1 },
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2005-04-17 00:20:36 +02:00
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};
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2005-11-07 09:58:31 +01:00
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#define N_IDS ARRAY_SIZE(cpu_ids)
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2005-04-17 00:20:36 +02:00
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struct cpu_model
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{
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const struct cpu_id *cpu_id;
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const char *model_name;
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unsigned max_freq; /* max clock in kHz */
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struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
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};
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2008-07-19 03:11:34 +02:00
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static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
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const struct cpu_id *x);
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2005-04-17 00:20:36 +02:00
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/* Operating points for current CPU */
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2008-07-19 03:11:34 +02:00
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static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
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static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
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2005-04-17 00:20:36 +02:00
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static struct cpufreq_driver centrino_driver;
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#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
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/* Computes the correct form for IA32_PERF_CTL MSR for a particular
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frequency/voltage operating point; frequency in MHz, volts in mV.
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This is stored as "index" in the structure. */
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#define OP(mhz, mv) \
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{ \
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.frequency = (mhz) * 1000, \
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.index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
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}
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/*
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* These voltage tables were derived from the Intel Pentium M
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* datasheet, document 25261202.pdf, Table 5. I have verified they
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* are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
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* M.
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*/
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/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
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static struct cpufreq_frequency_table banias_900[] =
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{
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OP(600, 844),
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OP(800, 988),
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OP(900, 1004),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
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static struct cpufreq_frequency_table banias_1000[] =
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{
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OP(600, 844),
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OP(800, 972),
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OP(900, 988),
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OP(1000, 1004),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
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static struct cpufreq_frequency_table banias_1100[] =
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{
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OP( 600, 956),
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OP( 800, 1020),
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OP( 900, 1100),
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OP(1000, 1164),
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OP(1100, 1180),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
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static struct cpufreq_frequency_table banias_1200[] =
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{
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OP( 600, 956),
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OP( 800, 1004),
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OP( 900, 1020),
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OP(1000, 1100),
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OP(1100, 1164),
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OP(1200, 1180),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.30GHz (Banias) */
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static struct cpufreq_frequency_table banias_1300[] =
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{
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OP( 600, 956),
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OP( 800, 1260),
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OP(1000, 1292),
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OP(1200, 1356),
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OP(1300, 1388),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.40GHz (Banias) */
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static struct cpufreq_frequency_table banias_1400[] =
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{
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OP( 600, 956),
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OP( 800, 1180),
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OP(1000, 1308),
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OP(1200, 1436),
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OP(1400, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.50GHz (Banias) */
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static struct cpufreq_frequency_table banias_1500[] =
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{
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OP( 600, 956),
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OP( 800, 1116),
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OP(1000, 1228),
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OP(1200, 1356),
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OP(1400, 1452),
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OP(1500, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.60GHz (Banias) */
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static struct cpufreq_frequency_table banias_1600[] =
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{
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OP( 600, 956),
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OP( 800, 1036),
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OP(1000, 1164),
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OP(1200, 1276),
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OP(1400, 1420),
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OP(1600, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.70GHz (Banias) */
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static struct cpufreq_frequency_table banias_1700[] =
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{
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OP( 600, 956),
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OP( 800, 1004),
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OP(1000, 1116),
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OP(1200, 1228),
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OP(1400, 1308),
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OP(1700, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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#undef OP
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#define _BANIAS(cpuid, max, name) \
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{ .cpu_id = cpuid, \
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.model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
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.max_freq = (max)*1000, \
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.op_points = banias_##max, \
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}
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#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
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/* CPU models, their operating frequency range, and freq/voltage
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operating points */
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static struct cpu_model models[] =
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{
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_BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
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BANIAS(1000),
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BANIAS(1100),
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BANIAS(1200),
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BANIAS(1300),
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BANIAS(1400),
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BANIAS(1500),
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BANIAS(1600),
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BANIAS(1700),
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/* NULL model_name is a wildcard */
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{ &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
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{ &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
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{ &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
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2005-06-01 04:03:43 +02:00
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{ &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
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{ &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
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2005-04-17 00:20:36 +02:00
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{ NULL, }
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};
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#undef _BANIAS
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#undef BANIAS
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static int centrino_cpu_init_table(struct cpufreq_policy *policy)
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{
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2007-10-19 20:35:04 +02:00
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struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
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2005-04-17 00:20:36 +02:00
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struct cpu_model *model;
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for(model = models; model->cpu_id != NULL; model++)
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if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
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(model->model_name == NULL ||
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strcmp(cpu->x86_model_id, model->model_name) == 0))
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break;
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if (model->cpu_id == NULL) {
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/* No match at all */
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2006-04-26 15:41:22 +02:00
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dprintk("no support for CPU model \"%s\": "
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2005-04-17 00:20:36 +02:00
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"send /proc/cpuinfo to " MAINTAINER "\n",
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cpu->x86_model_id);
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return -ENOENT;
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}
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if (model->op_points == NULL) {
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/* Matched a non-match */
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2006-04-26 15:41:22 +02:00
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dprintk("no table support for CPU model \"%s\"\n",
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2005-04-17 00:20:36 +02:00
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cpu->x86_model_id);
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2007-07-08 23:39:14 +02:00
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dprintk("try using the acpi-cpufreq driver\n");
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2005-04-17 00:20:36 +02:00
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return -ENOENT;
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}
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2008-07-19 03:11:34 +02:00
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per_cpu(centrino_model, policy->cpu) = model;
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2005-04-17 00:20:36 +02:00
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dprintk("found \"%s\": max frequency: %dkHz\n",
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model->model_name, model->max_freq);
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return 0;
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}
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#else
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2008-07-19 03:11:34 +02:00
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static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
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{
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return -ENODEV;
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}
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2005-04-17 00:20:36 +02:00
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#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
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2008-07-19 03:11:34 +02:00
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static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
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const struct cpu_id *x)
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2005-04-17 00:20:36 +02:00
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{
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if ((c->x86 == x->x86) &&
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(c->x86_model == x->x86_model) &&
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(c->x86_mask == x->x86_mask))
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return 1;
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return 0;
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}
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/* To be called only after centrino_model is initialized */
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static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
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{
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int i;
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/*
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* Extract clock in kHz from PERF_CTL value
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* for centrino, as some DSDTs are buggy.
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* Ideally, this can be done using the acpi_data structure.
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*/
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2008-07-19 03:11:34 +02:00
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if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
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(per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
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(per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
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2005-04-17 00:20:36 +02:00
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msr = (msr >> 8) & 0xff;
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return msr * 100000;
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}
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2008-07-19 03:11:34 +02:00
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if ((!per_cpu(centrino_model, cpu)) ||
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(!per_cpu(centrino_model, cpu)->op_points))
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2005-04-17 00:20:36 +02:00
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return 0;
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msr &= 0xffff;
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2008-07-19 03:11:34 +02:00
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for (i = 0;
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per_cpu(centrino_model, cpu)->op_points[i].frequency
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!= CPUFREQ_TABLE_END;
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i++) {
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if (msr == per_cpu(centrino_model, cpu)->op_points[i].index)
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return per_cpu(centrino_model, cpu)->
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op_points[i].frequency;
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2005-04-17 00:20:36 +02:00
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}
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if (failsafe)
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2008-07-19 03:11:34 +02:00
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return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
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2005-04-17 00:20:36 +02:00
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else
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return 0;
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}
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/* Return the current CPU frequency in kHz */
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static unsigned int get_cur_freq(unsigned int cpu)
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{
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unsigned l, h;
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unsigned clock_freq;
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cpumask_t saved_mask;
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saved_mask = current->cpus_allowed;
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2008-07-25 03:21:31 +02:00
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set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
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2005-04-17 00:20:36 +02:00
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if (smp_processor_id() != cpu)
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return 0;
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rdmsr(MSR_IA32_PERF_STATUS, l, h);
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clock_freq = extract_clock(l, cpu, 0);
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if (unlikely(clock_freq == 0)) {
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/*
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|
* On some CPUs, we can see transient MSR values (which are
|
|
|
|
* not present in _PSS), while CPU is doing some automatic
|
|
|
|
* P-state transition (like TM2). Get the last freq set
|
|
|
|
* in PERF_CTL.
|
|
|
|
*/
|
|
|
|
rdmsr(MSR_IA32_PERF_CTL, l, h);
|
|
|
|
clock_freq = extract_clock(l, cpu, 1);
|
|
|
|
}
|
|
|
|
|
2008-04-05 03:11:05 +02:00
|
|
|
set_cpus_allowed_ptr(current, &saved_mask);
|
2005-04-17 00:20:36 +02:00
|
|
|
return clock_freq;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int centrino_cpu_init(struct cpufreq_policy *policy)
|
|
|
|
{
|
2007-10-19 20:35:04 +02:00
|
|
|
struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
|
2005-04-17 00:20:36 +02:00
|
|
|
unsigned freq;
|
|
|
|
unsigned l, h;
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Only Intel makes Enhanced Speedstep-capable CPUs */
|
2008-07-19 03:11:34 +02:00
|
|
|
if (cpu->x86_vendor != X86_VENDOR_INTEL ||
|
|
|
|
!cpu_has(cpu, X86_FEATURE_EST))
|
2005-04-17 00:20:36 +02:00
|
|
|
return -ENODEV;
|
|
|
|
|
2006-02-28 06:37:44 +01:00
|
|
|
if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
|
2005-04-17 00:20:36 +02:00
|
|
|
centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
|
|
|
|
|
2007-07-08 23:39:14 +02:00
|
|
|
if (policy->cpu != 0)
|
|
|
|
return -ENODEV;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-07-08 23:39:14 +02:00
|
|
|
for (i = 0; i < N_IDS; i++)
|
|
|
|
if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
|
|
|
|
break;
|
2005-08-29 22:54:55 +02:00
|
|
|
|
2007-07-08 23:39:14 +02:00
|
|
|
if (i != N_IDS)
|
2008-07-19 03:11:34 +02:00
|
|
|
per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
|
2005-08-29 22:54:55 +02:00
|
|
|
|
2008-07-19 03:11:34 +02:00
|
|
|
if (!per_cpu(centrino_cpu, policy->cpu)) {
|
2007-07-08 23:39:14 +02:00
|
|
|
dprintk("found unsupported CPU with "
|
|
|
|
"Enhanced SpeedStep: send /proc/cpuinfo to "
|
|
|
|
MAINTAINER "\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-07-08 23:39:14 +02:00
|
|
|
if (centrino_cpu_init_table(policy)) {
|
|
|
|
return -ENODEV;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Check to see if Enhanced SpeedStep is enabled, and try to
|
|
|
|
enable it if not. */
|
|
|
|
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
|
|
|
|
|
|
|
|
if (!(l & (1<<16))) {
|
|
|
|
l |= (1<<16);
|
|
|
|
dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
|
|
|
|
wrmsr(MSR_IA32_MISC_ENABLE, l, h);
|
|
|
|
|
|
|
|
/* check to see if it stuck */
|
|
|
|
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
|
|
|
|
if (!(l & (1<<16))) {
|
2008-07-19 03:11:34 +02:00
|
|
|
printk(KERN_INFO PFX
|
|
|
|
"couldn't enable Enhanced SpeedStep\n");
|
2005-04-17 00:20:36 +02:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
freq = get_cur_freq(policy->cpu);
|
2008-07-19 03:11:34 +02:00
|
|
|
policy->cpuinfo.transition_latency = 10000;
|
|
|
|
/* 10uS transition latency */
|
2005-04-17 00:20:36 +02:00
|
|
|
policy->cur = freq;
|
|
|
|
|
|
|
|
dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
|
|
|
|
|
2008-07-19 03:11:34 +02:00
|
|
|
ret = cpufreq_frequency_table_cpuinfo(policy,
|
|
|
|
per_cpu(centrino_model, policy->cpu)->op_points);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (ret)
|
|
|
|
return (ret);
|
|
|
|
|
2008-07-19 03:11:34 +02:00
|
|
|
cpufreq_frequency_table_get_attr(
|
|
|
|
per_cpu(centrino_model, policy->cpu)->op_points, policy->cpu);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int centrino_cpu_exit(struct cpufreq_policy *policy)
|
|
|
|
{
|
|
|
|
unsigned int cpu = policy->cpu;
|
|
|
|
|
2008-07-19 03:11:34 +02:00
|
|
|
if (!per_cpu(centrino_model, cpu))
|
2005-04-17 00:20:36 +02:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
cpufreq_frequency_table_put_attr(cpu);
|
|
|
|
|
2008-07-19 03:11:34 +02:00
|
|
|
per_cpu(centrino_model, cpu) = NULL;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* centrino_verify - verifies a new CPUFreq policy
|
|
|
|
* @policy: new policy
|
|
|
|
*
|
|
|
|
* Limit must be within this model's frequency range at least one
|
|
|
|
* border included.
|
|
|
|
*/
|
|
|
|
static int centrino_verify (struct cpufreq_policy *policy)
|
|
|
|
{
|
2008-07-19 03:11:34 +02:00
|
|
|
return cpufreq_frequency_table_verify(policy,
|
|
|
|
per_cpu(centrino_model, policy->cpu)->op_points);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* centrino_setpolicy - set a new CPUFreq policy
|
|
|
|
* @policy: new policy
|
|
|
|
* @target_freq: the target frequency
|
2008-07-19 03:11:34 +02:00
|
|
|
* @relation: how that frequency relates to achieved frequency
|
|
|
|
* (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
|
2005-04-17 00:20:36 +02:00
|
|
|
*
|
|
|
|
* Sets a new CPUFreq policy.
|
|
|
|
*/
|
|
|
|
static int centrino_target (struct cpufreq_policy *policy,
|
|
|
|
unsigned int target_freq,
|
|
|
|
unsigned int relation)
|
|
|
|
{
|
|
|
|
unsigned int newstate = 0;
|
2005-12-14 21:05:00 +01:00
|
|
|
unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
|
2005-04-17 00:20:36 +02:00
|
|
|
struct cpufreq_freqs freqs;
|
2005-12-14 21:05:00 +01:00
|
|
|
int retval = 0;
|
|
|
|
unsigned int j, k, first_cpu, tmp;
|
2009-01-04 14:18:05 +01:00
|
|
|
cpumask_var_t saved_mask, covered_cpus;
|
2008-07-15 23:14:37 +02:00
|
|
|
|
2009-01-04 14:18:05 +01:00
|
|
|
if (unlikely(!alloc_cpumask_var(&saved_mask, GFP_KERNEL)))
|
2008-07-15 23:14:37 +02:00
|
|
|
return -ENOMEM;
|
2009-01-04 14:18:05 +01:00
|
|
|
if (unlikely(!alloc_cpumask_var(&covered_cpus, GFP_KERNEL))) {
|
|
|
|
free_cpumask_var(saved_mask);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
cpumask_copy(saved_mask, ¤t->cpus_allowed);
|
2008-07-15 23:14:37 +02:00
|
|
|
|
2008-07-19 03:11:34 +02:00
|
|
|
if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
|
2008-07-15 23:14:37 +02:00
|
|
|
retval = -ENODEV;
|
|
|
|
goto out;
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-12-14 21:05:00 +01:00
|
|
|
if (unlikely(cpufreq_frequency_table_target(policy,
|
2008-07-19 03:11:34 +02:00
|
|
|
per_cpu(centrino_model, cpu)->op_points,
|
2005-12-14 21:05:00 +01:00
|
|
|
target_freq,
|
|
|
|
relation,
|
|
|
|
&newstate))) {
|
2008-07-15 23:14:37 +02:00
|
|
|
retval = -EINVAL;
|
|
|
|
goto out;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2005-12-14 21:05:00 +01:00
|
|
|
first_cpu = 1;
|
2008-11-21 11:37:16 +01:00
|
|
|
for_each_cpu_mask_nr(j, policy->cpus) {
|
|
|
|
const cpumask_t *mask;
|
|
|
|
|
|
|
|
/* cpufreq holds the hotplug lock, so we are safe here */
|
|
|
|
if (!cpu_online(j))
|
|
|
|
continue;
|
|
|
|
|
2005-12-14 21:05:00 +01:00
|
|
|
/*
|
|
|
|
* Support for SMP systems.
|
|
|
|
* Make sure we are running on CPU that wants to change freq
|
|
|
|
*/
|
|
|
|
if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
|
2008-11-21 11:37:16 +01:00
|
|
|
mask = &policy->cpus;
|
2005-12-14 21:05:00 +01:00
|
|
|
else
|
2008-11-21 11:37:16 +01:00
|
|
|
mask = &cpumask_of_cpu(j);
|
2005-12-14 21:05:00 +01:00
|
|
|
|
2008-11-21 11:37:16 +01:00
|
|
|
set_cpus_allowed_ptr(current, mask);
|
2007-04-12 00:22:34 +02:00
|
|
|
preempt_disable();
|
2008-11-21 11:37:16 +01:00
|
|
|
if (unlikely(!cpu_isset(smp_processor_id(), *mask))) {
|
2005-12-14 21:05:00 +01:00
|
|
|
dprintk("couldn't limit to CPUs in this domain\n");
|
|
|
|
retval = -EAGAIN;
|
|
|
|
if (first_cpu) {
|
|
|
|
/* We haven't started the transition yet. */
|
|
|
|
goto migrate_end;
|
|
|
|
}
|
2007-04-12 00:22:34 +02:00
|
|
|
preempt_enable();
|
2005-12-14 21:05:00 +01:00
|
|
|
break;
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-07-19 03:11:34 +02:00
|
|
|
msr = per_cpu(centrino_model, cpu)->op_points[newstate].index;
|
2005-12-14 21:05:00 +01:00
|
|
|
|
|
|
|
if (first_cpu) {
|
|
|
|
rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
|
|
|
|
if (msr == (oldmsr & 0xffff)) {
|
|
|
|
dprintk("no change needed - msr was and needs "
|
|
|
|
"to be %x\n", oldmsr);
|
|
|
|
retval = 0;
|
|
|
|
goto migrate_end;
|
|
|
|
}
|
|
|
|
|
|
|
|
freqs.old = extract_clock(oldmsr, cpu, 0);
|
|
|
|
freqs.new = extract_clock(msr, cpu, 0);
|
|
|
|
|
|
|
|
dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
|
|
|
|
target_freq, freqs.old, freqs.new, msr);
|
|
|
|
|
2008-11-21 11:37:16 +01:00
|
|
|
for_each_cpu_mask_nr(k, policy->cpus) {
|
|
|
|
if (!cpu_online(k))
|
|
|
|
continue;
|
2005-12-14 21:05:00 +01:00
|
|
|
freqs.cpu = k;
|
|
|
|
cpufreq_notify_transition(&freqs,
|
|
|
|
CPUFREQ_PRECHANGE);
|
|
|
|
}
|
|
|
|
|
|
|
|
first_cpu = 0;
|
|
|
|
/* all but 16 LSB are reserved, treat them with care */
|
|
|
|
oldmsr &= ~0xffff;
|
|
|
|
msr &= 0xffff;
|
|
|
|
oldmsr |= msr;
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-12-14 21:05:00 +01:00
|
|
|
wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
|
2007-04-12 00:22:34 +02:00
|
|
|
if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
|
|
|
|
preempt_enable();
|
2005-12-14 21:05:00 +01:00
|
|
|
break;
|
2007-04-12 00:22:34 +02:00
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-07-15 23:14:37 +02:00
|
|
|
cpu_set(j, *covered_cpus);
|
2007-04-12 00:22:34 +02:00
|
|
|
preempt_enable();
|
2005-12-14 21:05:00 +01:00
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-11-21 11:37:16 +01:00
|
|
|
for_each_cpu_mask_nr(k, policy->cpus) {
|
|
|
|
if (!cpu_online(k))
|
|
|
|
continue;
|
2005-12-14 21:05:00 +01:00
|
|
|
freqs.cpu = k;
|
|
|
|
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-12-14 21:05:00 +01:00
|
|
|
if (unlikely(retval)) {
|
|
|
|
/*
|
|
|
|
* We have failed halfway through the frequency change.
|
|
|
|
* We have sent callbacks to policy->cpus and
|
|
|
|
* MSRs have already been written on coverd_cpus.
|
|
|
|
* Best effort undo..
|
|
|
|
*/
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-11-21 11:37:16 +01:00
|
|
|
for_each_cpu_mask_nr(j, *covered_cpus) {
|
|
|
|
set_cpus_allowed_ptr(current, &cpumask_of_cpu(j));
|
|
|
|
wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-12-14 21:05:00 +01:00
|
|
|
tmp = freqs.new;
|
|
|
|
freqs.new = freqs.old;
|
|
|
|
freqs.old = tmp;
|
2008-11-21 11:37:16 +01:00
|
|
|
for_each_cpu_mask_nr(j, policy->cpus) {
|
|
|
|
if (!cpu_online(j))
|
|
|
|
continue;
|
2005-12-14 21:05:00 +01:00
|
|
|
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
|
|
|
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
|
|
|
}
|
|
|
|
}
|
2008-07-15 23:14:37 +02:00
|
|
|
set_cpus_allowed_ptr(current, saved_mask);
|
|
|
|
retval = 0;
|
|
|
|
goto out;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
migrate_end:
|
2007-04-12 00:22:34 +02:00
|
|
|
preempt_enable();
|
2008-07-15 23:14:37 +02:00
|
|
|
set_cpus_allowed_ptr(current, saved_mask);
|
|
|
|
out:
|
2009-01-04 14:18:05 +01:00
|
|
|
free_cpumask_var(saved_mask);
|
|
|
|
free_cpumask_var(covered_cpus);
|
2008-07-15 23:14:37 +02:00
|
|
|
return retval;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct freq_attr* centrino_attr[] = {
|
|
|
|
&cpufreq_freq_attr_scaling_available_freqs,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct cpufreq_driver centrino_driver = {
|
|
|
|
.name = "centrino", /* should be speedstep-centrino,
|
|
|
|
but there's a 16 char limit */
|
|
|
|
.init = centrino_cpu_init,
|
|
|
|
.exit = centrino_cpu_exit,
|
|
|
|
.verify = centrino_verify,
|
|
|
|
.target = centrino_target,
|
|
|
|
.get = get_cur_freq,
|
|
|
|
.attr = centrino_attr,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
|
|
|
|
*
|
|
|
|
* Initializes the Enhanced SpeedStep support. Returns -ENODEV on
|
|
|
|
* unsupported devices, -ENOENT if there's no voltage table for this
|
|
|
|
* particular CPU model, -EINVAL on problems during initiatization,
|
|
|
|
* and zero on success.
|
|
|
|
*
|
|
|
|
* This is quite picky. Not only does the CPU have to advertise the
|
|
|
|
* "est" flag in the cpuid capability flags, we look for a specific
|
|
|
|
* CPU model and stepping, and we need to have the exact model name in
|
|
|
|
* our voltage tables. That is, be paranoid about not releasing
|
|
|
|
* someone's valuable magic smoke.
|
|
|
|
*/
|
|
|
|
static int __init centrino_init(void)
|
|
|
|
{
|
2007-10-19 20:35:04 +02:00
|
|
|
struct cpuinfo_x86 *cpu = &cpu_data(0);
|
2005-04-17 00:20:36 +02:00
|
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if (!cpu_has(cpu, X86_FEATURE_EST))
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return -ENODEV;
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return cpufreq_register_driver(¢rino_driver);
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}
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static void __exit centrino_exit(void)
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{
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cpufreq_unregister_driver(¢rino_driver);
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}
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MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
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MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
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MODULE_LICENSE ("GPL");
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late_initcall(centrino_init);
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module_exit(centrino_exit);
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