115 lines
3.3 KiB
ArmAsm
115 lines
3.3 KiB
ArmAsm
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/*
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Asm versions of Xen pv-ops, suitable for either direct use or inlining.
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The inline versions are the same as the direct-use versions, with the
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pre- and post-amble chopped off.
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This code is encoded for size rather than absolute efficiency,
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with a view to being able to inline as much as possible.
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We only bother with direct forms (ie, vcpu in pda) of the operations
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here; the indirect forms are better handled in C, since they're
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generally too large to inline anyway.
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/percpu.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor-flags.h>
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#define RELOC(x, v) .globl x##_reloc; x##_reloc=v
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#define ENDPATCH(x) .globl x##_end; x##_end=.
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/*
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Enable events. This clears the event mask and tests the pending
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event status with one and operation. If there are pending
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events, then enter the hypervisor to get them handled.
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*/
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ENTRY(xen_irq_enable_direct)
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/* Clear mask and test pending */
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andw $0x00ff, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_pending
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/* Preempt here doesn't matter because that will deal with
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any pending interrupts. The pending check may end up being
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run on the wrong CPU, but that doesn't hurt. */
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jz 1f
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2: call check_events
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1:
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ENDPATCH(xen_irq_enable_direct)
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ret
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ENDPROC(xen_irq_enable_direct)
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RELOC(xen_irq_enable_direct, 2b+1)
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/*
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Disabling events is simply a matter of making the event mask
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non-zero.
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*/
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ENTRY(xen_irq_disable_direct)
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movb $1, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
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ENDPATCH(xen_irq_disable_direct)
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ret
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ENDPROC(xen_irq_disable_direct)
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RELOC(xen_irq_disable_direct, 0)
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/*
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(xen_)save_fl is used to get the current interrupt enable status.
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Callers expect the status to be in X86_EFLAGS_IF, and other bits
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may be set in the return value. We take advantage of this by
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making sure that X86_EFLAGS_IF has the right value (and other bits
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in that byte are 0), but other bits in the return value are
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undefined. We need to toggle the state of the bit, because
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Xen and x86 use opposite senses (mask vs enable).
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*/
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ENTRY(xen_save_fl_direct)
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testb $0xff, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
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setz %ah
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addb %ah,%ah
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ENDPATCH(xen_save_fl_direct)
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ret
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ENDPROC(xen_save_fl_direct)
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RELOC(xen_save_fl_direct, 0)
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/*
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In principle the caller should be passing us a value return
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from xen_save_fl_direct, but for robustness sake we test only
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the X86_EFLAGS_IF flag rather than the whole byte. After
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setting the interrupt mask state, it checks for unmasked
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pending events and enters the hypervisor to get them delivered
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if so.
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*/
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ENTRY(xen_restore_fl_direct)
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testb $X86_EFLAGS_IF>>8, %ah
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setz %al
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movb %al, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
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/* Preempt here doesn't matter because that will deal with
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any pending interrupts. The pending check may end up being
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run on the wrong CPU, but that doesn't hurt. */
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/* check for pending but unmasked */
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cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_pending
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jz 1f
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2: call check_events
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1:
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ENDPATCH(xen_restore_fl_direct)
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ret
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ENDPROC(xen_restore_fl_direct)
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RELOC(xen_restore_fl_direct, 2b+1)
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/*
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Force an event check by making a hypercall,
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but preserve regs before making the call.
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*/
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check_events:
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push %eax
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push %ecx
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push %edx
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call force_evtchn_callback
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pop %edx
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pop %ecx
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pop %eax
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ret
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