2005-04-17 00:20:36 +02:00
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/*
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* drivers/mtd/nand/au1550nd.c
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*
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* Copyright (C) 2004 Embedded Edge, LLC
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*
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2005-11-07 12:15:49 +01:00
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* $Id: au1550nd.c,v 1.13 2005/11/07 11:14:30 gleixner Exp $
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2005-04-17 00:20:36 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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2005-11-09 06:34:55 +01:00
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#include <linux/version.h>
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2005-04-17 00:20:36 +02:00
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#include <asm/io.h>
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/* fixme: this is ugly */
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#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
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2005-09-23 03:44:58 +02:00
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#include <asm/mach-au1x00/au1xxx.h>
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2005-04-17 00:20:36 +02:00
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#else
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#include <asm/au1000.h>
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#ifdef CONFIG_MIPS_PB1550
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2005-11-07 12:15:49 +01:00
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#include <asm/pb1550.h>
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2005-04-17 00:20:36 +02:00
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#endif
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#ifdef CONFIG_MIPS_DB1550
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2005-11-07 12:15:49 +01:00
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#include <asm/db1x00.h>
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2005-04-17 00:20:36 +02:00
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#endif
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#endif
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/*
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* MTD structure for NAND controller
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*/
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static struct mtd_info *au1550_mtd = NULL;
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static void __iomem *p_nand;
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static int nand_width = 1; /* default x8*/
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/*
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* Define partitions for flash device
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*/
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const static struct mtd_partition partition_info[] = {
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2005-11-07 12:15:49 +01:00
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{
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2005-09-23 03:44:58 +02:00
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.name = "NAND FS 0",
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2005-04-17 00:20:36 +02:00
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.offset = 0,
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2005-11-07 12:15:49 +01:00
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.size = 8*1024*1024
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2005-04-17 00:20:36 +02:00
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},
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2005-11-07 12:15:49 +01:00
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{
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2005-09-23 03:44:58 +02:00
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.name = "NAND FS 1",
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2005-04-17 00:20:36 +02:00
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.offset = MTDPART_OFS_APPEND,
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2005-09-23 03:44:58 +02:00
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.size = MTDPART_SIZ_FULL
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2005-04-17 00:20:36 +02:00
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}
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};
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2005-09-23 03:44:58 +02:00
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#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
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2005-04-17 00:20:36 +02:00
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/**
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* au_read_byte - read one byte from the chip
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* @mtd: MTD device structure
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*
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* read function for 8bit buswith
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*/
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static u_char au_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u_char ret = readb(this->IO_ADDR_R);
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au_sync();
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return ret;
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}
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/**
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* au_write_byte - write one byte to the chip
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* @mtd: MTD device structure
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* @byte: pointer to data byte to write
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*
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* write function for 8it buswith
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*/
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static void au_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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writeb(byte, this->IO_ADDR_W);
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au_sync();
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}
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/**
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* au_read_byte16 - read one byte endianess aware from the chip
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* @mtd: MTD device structure
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*
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2005-11-07 12:15:49 +01:00
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* read function for 16bit buswith with
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2005-04-17 00:20:36 +02:00
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* endianess conversion
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*/
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static u_char au_read_byte16(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
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au_sync();
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return ret;
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}
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/**
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* au_write_byte16 - write one byte endianess aware to the chip
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* @mtd: MTD device structure
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* @byte: pointer to data byte to write
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*
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* write function for 16bit buswith with
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* endianess conversion
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*/
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static void au_write_byte16(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
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au_sync();
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}
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/**
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* au_read_word - read one word from the chip
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* @mtd: MTD device structure
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*
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2005-11-07 12:15:49 +01:00
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* read function for 16bit buswith without
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2005-04-17 00:20:36 +02:00
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* endianess conversion
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*/
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static u16 au_read_word(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u16 ret = readw(this->IO_ADDR_R);
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au_sync();
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return ret;
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}
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/**
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* au_write_word - write one word to the chip
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* @mtd: MTD device structure
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* @word: data word to write
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*
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2005-11-07 12:15:49 +01:00
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* write function for 16bit buswith without
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2005-04-17 00:20:36 +02:00
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* endianess conversion
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*/
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static void au_write_word(struct mtd_info *mtd, u16 word)
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{
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struct nand_chip *this = mtd->priv;
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writew(word, this->IO_ADDR_W);
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au_sync();
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}
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/**
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* au_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* write function for 8bit buswith
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*/
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static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i=0; i<len; i++) {
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writeb(buf[i], this->IO_ADDR_W);
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au_sync();
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}
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}
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/**
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2005-11-07 12:15:49 +01:00
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* au_read_buf - read chip data into buffer
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2005-04-17 00:20:36 +02:00
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* read function for 8bit buswith
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*/
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static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i=0; i<len; i++) {
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buf[i] = readb(this->IO_ADDR_R);
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2005-11-07 12:15:49 +01:00
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au_sync();
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2005-04-17 00:20:36 +02:00
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}
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}
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/**
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2005-11-07 12:15:49 +01:00
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* au_verify_buf - Verify chip data against buffer
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2005-04-17 00:20:36 +02:00
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* @mtd: MTD device structure
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* @buf: buffer containing the data to compare
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* @len: number of bytes to compare
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*
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* verify function for 8bit buswith
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*/
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static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i=0; i<len; i++) {
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if (buf[i] != readb(this->IO_ADDR_R))
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return -EFAULT;
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au_sync();
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}
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return 0;
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}
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/**
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* au_write_buf16 - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* write function for 16bit buswith
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*/
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static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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2005-11-07 12:15:49 +01:00
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2005-04-17 00:20:36 +02:00
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for (i=0; i<len; i++) {
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writew(p[i], this->IO_ADDR_W);
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au_sync();
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}
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2005-11-07 12:15:49 +01:00
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2005-04-17 00:20:36 +02:00
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}
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/**
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2005-11-07 12:15:49 +01:00
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* au_read_buf16 - read chip data into buffer
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2005-04-17 00:20:36 +02:00
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* read function for 16bit buswith
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*/
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static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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for (i=0; i<len; i++) {
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p[i] = readw(this->IO_ADDR_R);
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au_sync();
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}
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}
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/**
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2005-11-07 12:15:49 +01:00
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* au_verify_buf16 - Verify chip data against buffer
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2005-04-17 00:20:36 +02:00
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* @mtd: MTD device structure
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* @buf: buffer containing the data to compare
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* @len: number of bytes to compare
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*
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* verify function for 16bit buswith
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*/
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static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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for (i=0; i<len; i++) {
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if (p[i] != readw(this->IO_ADDR_R))
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return -EFAULT;
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au_sync();
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}
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return 0;
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}
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static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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register struct nand_chip *this = mtd->priv;
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switch(cmd){
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case NAND_CTL_SETCLE: this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; break;
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case NAND_CTL_CLRCLE: this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; break;
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case NAND_CTL_SETALE: this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; break;
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2005-11-07 12:15:49 +01:00
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case NAND_CTL_CLRALE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
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/* FIXME: Nobody knows why this is neccecary,
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2005-04-17 00:20:36 +02:00
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* but it works only that way */
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2005-11-07 12:15:49 +01:00
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udelay(1);
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2005-04-17 00:20:36 +02:00
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break;
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2005-11-07 12:15:49 +01:00
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case NAND_CTL_SETNCE:
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2005-04-17 00:20:36 +02:00
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/* assert (force assert) chip enable */
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au_writel((1<<(4+NAND_CS)) , MEM_STNDCTL); break;
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break;
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2005-11-07 12:15:49 +01:00
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case NAND_CTL_CLRNCE:
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2005-04-17 00:20:36 +02:00
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/* deassert chip enable */
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au_writel(0, MEM_STNDCTL); break;
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break;
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}
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this->IO_ADDR_R = this->IO_ADDR_W;
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2005-11-07 12:15:49 +01:00
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2005-04-17 00:20:36 +02:00
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/* Drain the writebuffer */
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au_sync();
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}
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int au1550_device_ready(struct mtd_info *mtd)
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{
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int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
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au_sync();
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return ret;
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}
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/*
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* Main initialization routine
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*/
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2005-09-23 03:44:58 +02:00
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int __init au1xxx_nand_init (void)
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2005-04-17 00:20:36 +02:00
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{
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struct nand_chip *this;
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u16 boot_swapboot = 0; /* default value */
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int retval;
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2005-09-23 03:44:58 +02:00
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u32 mem_staddr;
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u32 nand_phys;
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2005-04-17 00:20:36 +02:00
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/* Allocate memory for MTD device structure and private data */
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2005-11-07 12:15:49 +01:00
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au1550_mtd = kmalloc (sizeof(struct mtd_info) +
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2005-04-17 00:20:36 +02:00
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sizeof (struct nand_chip), GFP_KERNEL);
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if (!au1550_mtd) {
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printk ("Unable to allocate NAND MTD dev structure.\n");
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return -ENOMEM;
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}
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/* Get pointer to private data */
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this = (struct nand_chip *) (&au1550_mtd[1]);
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/* Initialize structures */
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memset((char *) au1550_mtd, 0, sizeof(struct mtd_info));
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memset((char *) this, 0, sizeof(struct nand_chip));
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/* Link the private data with the MTD structure */
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au1550_mtd->priv = this;
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2005-09-23 03:44:58 +02:00
|
|
|
/* disable interrupts */
|
|
|
|
au_writel(au_readl(MEM_STNDCTL) & ~(1<<8), MEM_STNDCTL);
|
2005-11-07 12:15:49 +01:00
|
|
|
|
2005-09-23 03:44:58 +02:00
|
|
|
/* disable NAND boot */
|
|
|
|
au_writel(au_readl(MEM_STNDCTL) & ~(1<<0), MEM_STNDCTL);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_MIPS_PB1550
|
|
|
|
/* set gpio206 high */
|
|
|
|
au_writel(au_readl(GPIO2_DIR) & ~(1<<6), GPIO2_DIR);
|
|
|
|
|
2005-11-07 12:15:49 +01:00
|
|
|
boot_swapboot = (au_readl(MEM_STSTAT) & (0x7<<1)) |
|
2005-04-17 00:20:36 +02:00
|
|
|
((bcsr->status >> 6) & 0x1);
|
|
|
|
switch (boot_swapboot) {
|
|
|
|
case 0:
|
|
|
|
case 2:
|
|
|
|
case 8:
|
|
|
|
case 0xC:
|
|
|
|
case 0xD:
|
|
|
|
/* x16 NAND Flash */
|
|
|
|
nand_width = 0;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
case 9:
|
|
|
|
case 3:
|
|
|
|
case 0xE:
|
|
|
|
case 0xF:
|
|
|
|
/* x8 NAND Flash */
|
|
|
|
nand_width = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printk("Pb1550 NAND: bad boot:swap\n");
|
|
|
|
retval = -EINVAL;
|
|
|
|
goto outmem;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-09-23 03:44:58 +02:00
|
|
|
/* Configure chip-select; normally done by boot code, e.g. YAMON */
|
|
|
|
#ifdef NAND_STCFG
|
|
|
|
if (NAND_CS == 0) {
|
|
|
|
au_writel(NAND_STCFG, MEM_STCFG0);
|
|
|
|
au_writel(NAND_STTIME, MEM_STTIME0);
|
|
|
|
au_writel(NAND_STADDR, MEM_STADDR0);
|
|
|
|
}
|
|
|
|
if (NAND_CS == 1) {
|
|
|
|
au_writel(NAND_STCFG, MEM_STCFG1);
|
|
|
|
au_writel(NAND_STTIME, MEM_STTIME1);
|
|
|
|
au_writel(NAND_STADDR, MEM_STADDR1);
|
|
|
|
}
|
|
|
|
if (NAND_CS == 2) {
|
|
|
|
au_writel(NAND_STCFG, MEM_STCFG2);
|
|
|
|
au_writel(NAND_STTIME, MEM_STTIME2);
|
|
|
|
au_writel(NAND_STADDR, MEM_STADDR2);
|
|
|
|
}
|
|
|
|
if (NAND_CS == 3) {
|
|
|
|
au_writel(NAND_STCFG, MEM_STCFG3);
|
|
|
|
au_writel(NAND_STTIME, MEM_STTIME3);
|
|
|
|
au_writel(NAND_STADDR, MEM_STADDR3);
|
|
|
|
}
|
|
|
|
#endif
|
2005-11-07 12:15:49 +01:00
|
|
|
|
2005-09-23 03:44:58 +02:00
|
|
|
/* Locate NAND chip-select in order to determine NAND phys address */
|
|
|
|
mem_staddr = 0x00000000;
|
|
|
|
if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
|
|
|
|
mem_staddr = au_readl(MEM_STADDR0);
|
|
|
|
else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
|
|
|
|
mem_staddr = au_readl(MEM_STADDR1);
|
|
|
|
else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
|
|
|
|
mem_staddr = au_readl(MEM_STADDR2);
|
|
|
|
else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
|
|
|
|
mem_staddr = au_readl(MEM_STADDR3);
|
|
|
|
|
|
|
|
if (mem_staddr == 0x00000000) {
|
|
|
|
printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
|
|
|
|
kfree(au1550_mtd);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
nand_phys = (mem_staddr << 4) & 0xFFFC0000;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-09-23 03:44:58 +02:00
|
|
|
p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
|
|
|
|
|
|
|
|
/* make controller and MTD agree */
|
|
|
|
if (NAND_CS == 0)
|
|
|
|
nand_width = au_readl(MEM_STCFG0) & (1<<22);
|
|
|
|
if (NAND_CS == 1)
|
|
|
|
nand_width = au_readl(MEM_STCFG1) & (1<<22);
|
|
|
|
if (NAND_CS == 2)
|
|
|
|
nand_width = au_readl(MEM_STCFG2) & (1<<22);
|
|
|
|
if (NAND_CS == 3)
|
|
|
|
nand_width = au_readl(MEM_STCFG3) & (1<<22);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
|
|
|
|
/* Set address of hardware control function */
|
|
|
|
this->hwcontrol = au1550_hwcontrol;
|
|
|
|
this->dev_ready = au1550_device_ready;
|
|
|
|
/* 30 us command delay time */
|
2005-11-07 12:15:49 +01:00
|
|
|
this->chip_delay = 30;
|
2005-04-17 00:20:36 +02:00
|
|
|
this->eccmode = NAND_ECC_SOFT;
|
|
|
|
|
|
|
|
this->options = NAND_NO_AUTOINCR;
|
|
|
|
|
|
|
|
if (!nand_width)
|
|
|
|
this->options |= NAND_BUSWIDTH_16;
|
|
|
|
|
|
|
|
this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
|
|
|
|
this->write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
|
|
|
|
this->write_word = au_write_word;
|
|
|
|
this->read_word = au_read_word;
|
|
|
|
this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
|
|
|
|
this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
|
|
|
|
this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
|
|
|
|
|
|
|
|
/* Scan to find existence of the device */
|
|
|
|
if (nand_scan (au1550_mtd, 1)) {
|
|
|
|
retval = -ENXIO;
|
|
|
|
goto outio;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Register the partitions */
|
2005-09-23 03:44:58 +02:00
|
|
|
add_mtd_partitions(au1550_mtd, partition_info, NB_OF(partition_info));
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
outio:
|
|
|
|
iounmap ((void *)p_nand);
|
2005-11-07 12:15:49 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
outmem:
|
|
|
|
kfree (au1550_mtd);
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2005-09-23 03:44:58 +02:00
|
|
|
module_init(au1xxx_nand_init);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Clean up routine
|
|
|
|
*/
|
|
|
|
#ifdef MODULE
|
|
|
|
static void __exit au1550_cleanup (void)
|
|
|
|
{
|
|
|
|
struct nand_chip *this = (struct nand_chip *) &au1550_mtd[1];
|
|
|
|
|
|
|
|
/* Release resources, unregister device */
|
|
|
|
nand_release (au1550_mtd);
|
|
|
|
|
|
|
|
/* Free the MTD device structure */
|
|
|
|
kfree (au1550_mtd);
|
|
|
|
|
|
|
|
/* Unmap */
|
|
|
|
iounmap ((void *)p_nand);
|
|
|
|
}
|
|
|
|
module_exit(au1550_cleanup);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Embedded Edge, LLC");
|
|
|
|
MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
|