2013-02-01 01:54:38 +01:00
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/*
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2009-11-13 23:54:14 +01:00
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* Copyright (c) 2006-2009 Simtec Electronics
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2009-07-31 00:23:26 +02:00
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/cpufreq.h>
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2009-07-31 00:23:42 +02:00
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#include <linux/seq_file.h>
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2009-07-31 00:23:26 +02:00
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#include <linux/io.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 09:04:11 +01:00
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#include <linux/slab.h>
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2009-07-31 00:23:26 +02:00
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu-freq-core.h>
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2013-02-04 02:00:11 +01:00
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#include "regs-mem.h"
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2009-07-31 00:23:26 +02:00
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#define print_ns(x) ((x) / 10), ((x) % 10)
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/**
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* s3c2410_print_timing - print bank timing data for debug purposes
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* @pfx: The prefix to put on the output
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* @timings: The timing inforamtion to print.
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*/
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static void s3c2410_print_timing(const char *pfx,
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struct s3c_iotimings *timings)
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{
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struct s3c2410_iobank_timing *bt;
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int bank;
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for (bank = 0; bank < MAX_BANKS; bank++) {
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bt = timings->bank[bank].io_2410;
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if (!bt)
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continue;
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printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, "
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"Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank,
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print_ns(bt->tacs),
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print_ns(bt->tcos),
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print_ns(bt->tacc),
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print_ns(bt->tcoh),
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print_ns(bt->tcah));
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}
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}
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/**
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* bank_reg - convert bank number to pointer to the control register.
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* @bank: The IO bank number.
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*/
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static inline void __iomem *bank_reg(unsigned int bank)
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{
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return S3C2410_BANKCON0 + (bank << 2);
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}
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/**
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* bank_is_io - test whether bank is used for IO
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* @bankcon: The bank control register.
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*
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* This is a simplistic test to see if any BANKCON[x] is not an IO
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* bank. It currently does not take into account whether BWSCON has
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* an illegal width-setting in it, or if the pin connected to nCS[x]
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* is actually being handled as a chip-select.
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*/
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static inline int bank_is_io(unsigned long bankcon)
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{
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return !(bankcon & S3C2410_BANKCON_SDRAM);
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}
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/**
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* to_div - convert cycle time to divisor
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* @cyc: The cycle time, in 10ths of nanoseconds.
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* @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
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*
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* Convert the given cycle time into the divisor to use to obtain it from
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* HCLK.
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*/
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static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns)
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{
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if (cyc == 0)
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return 0;
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return DIV_ROUND_UP(cyc, hclk_tns);
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}
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/**
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* calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
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* @cyc: The cycle time, in 10ths of nanoseconds.
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* @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
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* @v: Pointer to register to alter.
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* @shift: The shift to get to the control bits.
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*
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* Calculate the divisor, and turn it into the correct control bits to
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* set in the result, @v.
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*/
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static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns,
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unsigned long *v, int shift)
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{
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unsigned int div = to_div(cyc, hclk_tns);
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unsigned long val;
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s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n",
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__func__, cyc, hclk_tns, shift, div);
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switch (div) {
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case 0:
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val = 0;
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break;
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case 1:
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val = 1;
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break;
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case 2:
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val = 2;
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break;
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case 3:
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case 4:
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val = 3;
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break;
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default:
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return -1;
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}
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*v |= val << shift;
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return 0;
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}
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int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
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{
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/* Currently no support for Tacp calculations. */
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return 0;
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}
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/**
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* calc_tacc - calculate divisor control for tacc.
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* @cyc: The cycle time, in 10ths of nanoseconds.
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* @nwait_en: IS nWAIT enabled for this bank.
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* @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
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* @v: Pointer to register to alter.
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*
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* Calculate the divisor control for tACC, taking into account whether
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* the bank has nWAIT enabled. The result is used to modify the value
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* pointed to by @v.
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*/
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static int calc_tacc(unsigned int cyc, int nwait_en,
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unsigned long hclk_tns, unsigned long *v)
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{
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unsigned int div = to_div(cyc, hclk_tns);
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unsigned long val;
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s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n",
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__func__, cyc, nwait_en, hclk_tns, div);
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/* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */
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if (nwait_en && div < 4)
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div = 4;
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switch (div) {
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case 0:
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val = 0;
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break;
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case 1:
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case 2:
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case 3:
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case 4:
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val = div - 1;
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break;
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case 5:
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case 6:
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val = 4;
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break;
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case 7:
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case 8:
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val = 5;
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break;
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case 9:
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case 10:
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val = 6;
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break;
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case 11:
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case 12:
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case 13:
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case 14:
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val = 7;
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break;
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default:
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return -1;
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}
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*v |= val << 8;
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return 0;
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}
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/**
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* s3c2410_calc_bank - calculate bank timing infromation
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* @cfg: The configuration we need to calculate for.
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* @bt: The bank timing information.
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*
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* Given the cycle timine for a bank @bt, calculate the new BANKCON
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* setting for the @cfg timing. This updates the timing information
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* ready for the cpu frequency change.
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*/
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static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg,
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struct s3c2410_iobank_timing *bt)
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{
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unsigned long hclk = cfg->freq.hclk_tns;
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unsigned long res;
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int ret;
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res = bt->bankcon;
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res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16);
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/* tacp: 2,3,4,5 */
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/* tcah: 0,1,2,4 */
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/* tcoh: 0,1,2,4 */
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/* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */
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/* tcos: 0,1,2,4 */
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/* tacs: 0,1,2,4 */
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ret = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT);
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ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT);
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ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT);
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ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT);
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if (ret)
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return -EINVAL;
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ret |= calc_tacp(bt->tacp, hclk, &res);
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ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res);
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if (ret)
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return -EINVAL;
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bt->bankcon = res;
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return 0;
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}
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static unsigned int tacc_tab[] = {
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[0] = 1,
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[1] = 2,
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[2] = 3,
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[3] = 4,
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[4] = 6,
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[5] = 9,
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[6] = 10,
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[7] = 14,
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};
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/**
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* get_tacc - turn tACC value into cycle time
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* @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
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* @val: The bank timing register value, shifed down.
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*/
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static unsigned int get_tacc(unsigned long hclk_tns,
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unsigned long val)
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{
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val &= 7;
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return hclk_tns * tacc_tab[val];
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}
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/**
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* get_0124 - turn 0/1/2/4 divider into cycle time
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* @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
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* @val: The bank timing register value, shifed down.
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*/
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static unsigned int get_0124(unsigned long hclk_tns,
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unsigned long val)
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{
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val &= 3;
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return hclk_tns * ((val == 3) ? 4 : val);
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}
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/**
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* s3c2410_iotiming_getbank - turn BANKCON into cycle time information
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* @cfg: The frequency configuration
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* @bt: The bank timing to fill in (uses cached BANKCON)
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*
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* Given the BANKCON setting in @bt and the current frequency settings
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* in @cfg, update the cycle timing information.
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*/
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void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
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struct s3c2410_iobank_timing *bt)
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{
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unsigned long bankcon = bt->bankcon;
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unsigned long hclk = cfg->freq.hclk_tns;
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bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
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bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
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bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
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bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
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bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
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}
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2009-07-31 00:23:42 +02:00
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/**
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* s3c2410_iotiming_debugfs - debugfs show io bank timing information
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* @seq: The seq_file to write output to using seq_printf().
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* @cfg: The current configuration.
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* @iob: The IO bank information to decode.
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*/
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void s3c2410_iotiming_debugfs(struct seq_file *seq,
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struct s3c_cpufreq_config *cfg,
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union s3c_iobank *iob)
|
|
|
|
{
|
|
|
|
struct s3c2410_iobank_timing *bt = iob->io_2410;
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|
|
|
unsigned long bankcon = bt->bankcon;
|
|
|
|
unsigned long hclk = cfg->freq.hclk_tns;
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|
|
|
unsigned int tacs;
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|
|
|
unsigned int tcos;
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|
|
unsigned int tacc;
|
|
|
|
unsigned int tcoh;
|
|
|
|
unsigned int tcah;
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|
|
|
|
|
|
seq_printf(seq, "BANKCON=0x%08lx\n", bankcon);
|
|
|
|
|
|
|
|
tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
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|
|
|
tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
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|
|
|
tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
|
|
|
|
tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
|
|
|
|
tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
|
|
|
|
|
|
|
|
seq_printf(seq,
|
|
|
|
"\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
|
|
|
|
print_ns(bt->tacs),
|
|
|
|
print_ns(bt->tcos),
|
|
|
|
print_ns(bt->tacc),
|
|
|
|
print_ns(bt->tcoh),
|
|
|
|
print_ns(bt->tcah));
|
|
|
|
|
|
|
|
seq_printf(seq,
|
|
|
|
"\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
|
|
|
|
print_ns(tacs),
|
|
|
|
print_ns(tcos),
|
|
|
|
print_ns(tacc),
|
|
|
|
print_ns(tcoh),
|
|
|
|
print_ns(tcah));
|
|
|
|
}
|
|
|
|
|
2009-07-31 00:23:26 +02:00
|
|
|
/**
|
|
|
|
* s3c2410_iotiming_calc - Calculate bank timing for frequency change.
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|
|
|
* @cfg: The frequency configuration
|
|
|
|
* @iot: The IO timing information to fill out.
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|
|
|
*
|
|
|
|
* Calculate the new values for the banks in @iot based on the new
|
|
|
|
* frequency information in @cfg. This is then used by s3c2410_iotiming_set()
|
|
|
|
* to update the timing when necessary.
|
|
|
|
*/
|
|
|
|
int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
|
|
|
|
struct s3c_iotimings *iot)
|
|
|
|
{
|
|
|
|
struct s3c2410_iobank_timing *bt;
|
|
|
|
unsigned long bankcon;
|
|
|
|
int bank;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
for (bank = 0; bank < MAX_BANKS; bank++) {
|
|
|
|
bankcon = __raw_readl(bank_reg(bank));
|
|
|
|
bt = iot->bank[bank].io_2410;
|
|
|
|
|
|
|
|
if (!bt)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
bt->bankcon = bankcon;
|
|
|
|
|
|
|
|
ret = s3c2410_calc_bank(cfg, bt);
|
|
|
|
if (ret) {
|
|
|
|
printk(KERN_ERR "%s: cannot calculate bank %d io\n",
|
|
|
|
__func__, bank);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
s3c_freq_iodbg("%s: bank %d: con=%08lx\n",
|
|
|
|
__func__, bank, bt->bankcon);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* s3c2410_iotiming_set - set the IO timings from the given setup.
|
|
|
|
* @cfg: The frequency configuration
|
|
|
|
* @iot: The IO timing information to use.
|
|
|
|
*
|
|
|
|
* Set all the currently used IO bank timing information generated
|
|
|
|
* by s3c2410_iotiming_calc() once the core has validated that all
|
|
|
|
* the new values are within permitted bounds.
|
|
|
|
*/
|
|
|
|
void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
|
|
|
|
struct s3c_iotimings *iot)
|
|
|
|
{
|
|
|
|
struct s3c2410_iobank_timing *bt;
|
|
|
|
int bank;
|
|
|
|
|
|
|
|
/* set the io timings from the specifier */
|
|
|
|
|
|
|
|
for (bank = 0; bank < MAX_BANKS; bank++) {
|
|
|
|
bt = iot->bank[bank].io_2410;
|
|
|
|
if (!bt)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
__raw_writel(bt->bankcon, bank_reg(bank));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* s3c2410_iotiming_get - Get the timing information from current registers.
|
|
|
|
* @cfg: The frequency configuration
|
|
|
|
* @timings: The IO timing information to fill out.
|
|
|
|
*
|
|
|
|
* Calculate the @timings timing information from the current frequency
|
2016-05-21 13:51:23 +02:00
|
|
|
* information in @cfg, and the new frequency configuration
|
2009-07-31 00:23:26 +02:00
|
|
|
* through all the IO banks, reading the state and then updating @iot
|
|
|
|
* as necessary.
|
|
|
|
*
|
|
|
|
* This is used at the moment on initialisation to get the current
|
|
|
|
* configuration so that boards do not have to carry their own setup
|
|
|
|
* if the timings are correct on initialisation.
|
|
|
|
*/
|
|
|
|
|
|
|
|
int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
|
|
|
|
struct s3c_iotimings *timings)
|
|
|
|
{
|
|
|
|
struct s3c2410_iobank_timing *bt;
|
|
|
|
unsigned long bankcon;
|
|
|
|
unsigned long bwscon;
|
|
|
|
int bank;
|
|
|
|
|
|
|
|
bwscon = __raw_readl(S3C2410_BWSCON);
|
|
|
|
|
|
|
|
/* look through all banks to see what is currently set. */
|
|
|
|
|
|
|
|
for (bank = 0; bank < MAX_BANKS; bank++) {
|
|
|
|
bankcon = __raw_readl(bank_reg(bank));
|
|
|
|
|
|
|
|
if (!bank_is_io(bankcon))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
s3c_freq_iodbg("%s: bank %d: con %08lx\n",
|
|
|
|
__func__, bank, bankcon);
|
|
|
|
|
|
|
|
bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL);
|
|
|
|
if (!bt) {
|
|
|
|
printk(KERN_ERR "%s: no memory for bank\n", __func__);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* find out in nWait is enabled for bank. */
|
|
|
|
|
|
|
|
if (bank != 0) {
|
|
|
|
unsigned long tmp = S3C2410_BWSCON_GET(bwscon, bank);
|
|
|
|
if (tmp & S3C2410_BWSCON_WS)
|
|
|
|
bt->nwait_en = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
timings->bank[bank].io_2410 = bt;
|
|
|
|
bt->bankcon = bankcon;
|
|
|
|
|
|
|
|
s3c2410_iotiming_getbank(cfg, bt);
|
|
|
|
}
|
|
|
|
|
|
|
|
s3c2410_print_timing("get", timings);
|
|
|
|
return 0;
|
|
|
|
}
|