2013-08-06 20:10:08 +02:00
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/*
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* arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
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*
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* Created by: Nicolas Pitre, October 2012
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* Copyright: (C) 2012-2013 Linaro Limited
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*
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* Some portions of this file were originally written by Achin Gupta
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* Copyright: (C) 2012 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2013-11-25 17:16:25 +01:00
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#include <linux/delay.h>
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2013-08-06 20:10:08 +02:00
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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2013-10-29 13:18:37 +01:00
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#include <linux/of_irq.h>
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2013-08-06 20:10:08 +02:00
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#include <linux/errno.h>
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2013-07-24 13:05:01 +02:00
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#include <linux/irqchip/arm-gic.h>
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2013-08-06 20:10:08 +02:00
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#include <asm/mcpm.h>
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#include <asm/proc-fns.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/cp15.h>
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#include <linux/arm-cci.h>
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#include "spc.h"
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/* SCC conf registers */
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2013-11-25 17:16:25 +01:00
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#define RESET_CTRL 0x018
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#define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu)))
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#define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu)))
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2013-08-06 20:10:08 +02:00
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#define A15_CONF 0x400
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#define A7_CONF 0x500
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#define SYS_INFO 0x700
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#define SPC_BASE 0xb00
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2013-11-25 17:16:25 +01:00
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static void __iomem *scc;
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2013-08-06 20:10:08 +02:00
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#define TC2_CLUSTERS 2
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#define TC2_MAX_CPUS_PER_CLUSTER 3
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static unsigned int tc2_nr_cpus[TC2_CLUSTERS];
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2015-03-14 22:58:33 +01:00
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static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster)
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2013-08-06 20:10:08 +02:00
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{
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
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return -EINVAL;
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2015-03-14 22:58:33 +01:00
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ve_spc_set_resume_addr(cluster, cpu,
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virt_to_phys(mcpm_entry_point));
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ve_spc_cpu_wakeup_irq(cluster, cpu, true);
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2013-08-06 20:10:08 +02:00
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return 0;
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}
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2015-03-14 22:58:33 +01:00
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static int tc2_pm_cluster_powerup(unsigned int cluster)
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2013-08-06 20:10:08 +02:00
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{
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2015-03-14 22:58:33 +01:00
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pr_debug("%s: cluster %u\n", __func__, cluster);
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if (cluster >= TC2_CLUSTERS)
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return -EINVAL;
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ve_spc_powerdown(cluster, false);
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return 0;
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}
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2013-08-06 20:10:08 +02:00
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2015-03-14 22:58:33 +01:00
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static void tc2_pm_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
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{
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2013-08-06 20:10:08 +02:00
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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2015-03-14 22:58:33 +01:00
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ve_spc_cpu_wakeup_irq(cluster, cpu, true);
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ARM: vexpress: tc2: fix hotplug/idle/kexec race on cluster power down
On the TC2 testchip, when all CPUs in a cluster enter standbywfi
and commit a power down request, the power controller will wait
for standbywfil2 coming from L2 cache controller to shut the
cluster down.
By the time all CPUs in a cluster commit a power down request
and enter wfi, the power controller cannot backtrack, or put it
another way, a CPU must not be allowed to complete execution
independently of the power controller, the only way for it to
resume properly must be upon wake-up IRQ pending and subsequent
reset triggered from the power controller.
Current MCPM back-end for TC2 disables the GIC CPU IF only when
power down is committed through the tc2_pm_suspend() method, that
makes sense since a suspended CPU is still online and can receive
interrupts whereas a hotplugged CPU, since it is offline,
migrated all IRQs and shutdown the per-CPU peripherals, hence
their PPIs.
The flaw with this reasoning is the following. If all CPUs in
a clusters are entering a power down state either through CPU
idle or CPU hotplug, when the last man successfully completes
the MCPM power down sequence (and executes wfi), power controller
waits for L2 wfi signal to quiesce the cluster and shut it down.
If, when all CPUs are sitting in wfi, an online CPU hotplugs back
in one of the CPUs in the cluster being shutdown, that CPU
receives an IPI that causes wfi to complete (since tc2_pm_down()
method does not disable the GIC CPU IF in that case - CPU being
hotplugged out, not idle) and the power controller will never see
the stanbywfil2 signal coming from L2 that is required for
shutdown to happen and the system deadlocks.
Further to this issue, kexec hotplugs secondary CPUs out during
kernel reload/restart.
Because kexec may (deliberately) trash the old kernel text, it is
not OK for CPUs to follow the MCPM soft reboot path, since
instructions after the WFI may have been replaced by kexec.
If tc2_pm_down() does not disable the GIC cpu interface, there is a
race between CPU powerdown in the old kernel and the IPI from the
new kernel that triggers secondary boot, particularly if the
powerdown is slow (due to L2 cache cleaning for example). If the
new kernel wins the race, the affected CPU(s) will not really be
reset and may execute garbage after the WFI.
The only solution to this problem consists in disabling the GIC
CPU IF on a CPU committed to power down regardless of the power
down entry method (CPU hotplug or CPU idle). This way, CPU wake-up
is under power controller control, which prevents unexpected wfi
exit caused by a pending IRQ.
This patch moves the GIC CPU IF disable call in the TC2 MCPM
implementation from the tc2_pm_suspend() method to the
tc2_pm_down() method to fix the mentioned race condition(s).
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Tested-by: Dave Martin <Dave.Martin@arm.com> (for kexec)
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-09-27 17:54:42 +02:00
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/*
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* If the CPU is committed to power down, make sure
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* the power controller will be in charge of waking it
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* up upon IRQ, ie IRQ lines are cut from GIC CPU IF
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* to the CPU by disabling the GIC CPU IF to prevent wfi
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* from completing execution behind power controller back
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*/
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2015-07-31 10:44:12 +02:00
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gic_cpu_if_down(0);
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2015-03-14 22:58:33 +01:00
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}
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2013-08-06 20:10:08 +02:00
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2015-03-14 22:58:33 +01:00
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static void tc2_pm_cluster_powerdown_prepare(unsigned int cluster)
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{
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pr_debug("%s: cluster %u\n", __func__, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS);
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ve_spc_powerdown(cluster, true);
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ve_spc_global_wakeup_irq(true);
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}
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2013-08-06 20:10:08 +02:00
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2015-03-14 22:58:33 +01:00
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static void tc2_pm_cpu_cache_disable(void)
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{
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v7_exit_coherency_flush(louis);
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2013-08-06 20:10:08 +02:00
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}
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2015-03-14 22:58:33 +01:00
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static void tc2_pm_cluster_cache_disable(void)
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2012-12-10 06:22:06 +01:00
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{
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2015-03-14 22:58:33 +01:00
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
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/*
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* On the Cortex-A15 we need to disable
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* L2 prefetching before flushing the cache.
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*/
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asm volatile(
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"mcr p15, 1, %0, c15, c0, 3 \n\t"
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"isb \n\t"
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"dsb "
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: : "r" (0x400) );
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}
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v7_exit_coherency_flush(all);
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cci_disable_port_by_cpu(read_cpuid_mpidr());
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2012-12-10 06:22:06 +01:00
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}
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2013-11-25 17:16:25 +01:00
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static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster)
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{
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u32 mask = cluster ?
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RESET_A7_NCORERESET(cpu)
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: RESET_A15_NCORERESET(cpu);
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return !(readl_relaxed(scc + RESET_CTRL) & mask);
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}
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#define POLL_MSEC 10
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#define TIMEOUT_MSEC 1000
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2014-04-17 17:58:39 +02:00
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static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
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2013-11-25 17:16:25 +01:00
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{
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unsigned tries;
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) {
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2015-03-14 22:58:33 +01:00
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pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n",
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__func__, cpu, cluster,
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readl_relaxed(scc + RESET_CTRL));
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2013-11-25 17:16:25 +01:00
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/*
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2015-03-14 22:58:33 +01:00
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* We need the CPU to reach WFI, but the power
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* controller may put the cluster in reset and
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* power it off as soon as that happens, before
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* we have a chance to see STANDBYWFI.
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*
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* So we need to check for both conditions:
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2013-11-25 17:16:25 +01:00
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*/
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2015-03-14 22:58:33 +01:00
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if (tc2_core_in_reset(cpu, cluster) ||
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ve_spc_cpu_in_wfi(cpu, cluster))
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return 0; /* success: the CPU is halted */
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2013-11-25 17:16:25 +01:00
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/* Otherwise, wait and retry: */
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msleep(POLL_MSEC);
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}
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return -ETIMEDOUT; /* timeout */
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}
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2015-03-14 22:58:33 +01:00
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static void tc2_pm_cpu_suspend_prepare(unsigned int cpu, unsigned int cluster)
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2012-12-10 06:22:06 +01:00
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{
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ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
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}
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2015-03-14 22:58:33 +01:00
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static void tc2_pm_cpu_is_up(unsigned int cpu, unsigned int cluster)
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2013-08-06 20:10:08 +02:00
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{
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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ve_spc_cpu_wakeup_irq(cluster, cpu, false);
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ve_spc_set_resume_addr(cluster, cpu, 0);
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2015-03-14 22:58:33 +01:00
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}
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2013-08-06 20:10:08 +02:00
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2015-03-14 22:58:33 +01:00
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static void tc2_pm_cluster_is_up(unsigned int cluster)
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{
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pr_debug("%s: cluster %u\n", __func__, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS);
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ve_spc_powerdown(cluster, false);
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ve_spc_global_wakeup_irq(false);
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2013-08-06 20:10:08 +02:00
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}
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static const struct mcpm_platform_ops tc2_pm_power_ops = {
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2015-03-14 22:58:33 +01:00
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.cpu_powerup = tc2_pm_cpu_powerup,
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.cluster_powerup = tc2_pm_cluster_powerup,
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.cpu_suspend_prepare = tc2_pm_cpu_suspend_prepare,
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.cpu_powerdown_prepare = tc2_pm_cpu_powerdown_prepare,
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.cluster_powerdown_prepare = tc2_pm_cluster_powerdown_prepare,
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.cpu_cache_disable = tc2_pm_cpu_cache_disable,
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.cluster_cache_disable = tc2_pm_cluster_cache_disable,
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2014-04-17 17:58:39 +02:00
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.wait_for_powerdown = tc2_pm_wait_for_powerdown,
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2015-03-14 22:58:33 +01:00
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.cpu_is_up = tc2_pm_cpu_is_up,
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.cluster_is_up = tc2_pm_cluster_is_up,
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2013-08-06 20:10:08 +02:00
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};
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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*/
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static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
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{
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asm volatile (" \n"
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" cmp r0, #1 \n"
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" bxne lr \n"
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" b cci_enable_port_for_self ");
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}
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static int __init tc2_pm_init(void)
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{
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2015-03-14 22:58:33 +01:00
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unsigned int mpidr, cpu, cluster;
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2013-10-29 13:18:37 +01:00
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int ret, irq;
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2013-08-06 20:10:08 +02:00
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u32 a15_cluster_id, a7_cluster_id, sys_info;
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struct device_node *np;
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/*
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* The power management-related features are hidden behind
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* SCC registers. We need to extract runtime information like
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* cluster ids and number of CPUs really available in clusters.
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*/
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np = of_find_compatible_node(NULL, NULL,
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"arm,vexpress-scc,v2p-ca15_a7");
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scc = of_iomap(np, 0);
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if (!scc)
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return -ENODEV;
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a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf;
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a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf;
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if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS)
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return -EINVAL;
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sys_info = readl_relaxed(scc + SYS_INFO);
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tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf;
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tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf;
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2013-10-29 13:18:37 +01:00
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irq = irq_of_parse_and_map(np, 0);
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2013-08-06 20:10:08 +02:00
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/*
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* A subset of the SCC registers is also used to communicate
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* with the SPC (power controller). We need to be able to
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* drive it very early in the boot process to power up
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* processors, so we initialize the SPC driver here.
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*/
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2013-10-29 13:18:37 +01:00
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ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id, irq);
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2013-08-06 20:10:08 +02:00
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if (ret)
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return ret;
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if (!cci_probed())
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return -ENODEV;
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2015-03-14 22:58:33 +01:00
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
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pr_err("%s: boot CPU is out of bound!\n", __func__);
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2013-08-06 20:10:08 +02:00
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return -EINVAL;
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2015-03-14 22:58:33 +01:00
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}
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2013-08-06 20:10:08 +02:00
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ret = mcpm_platform_register(&tc2_pm_power_ops);
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if (!ret) {
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mcpm_sync_init(tc2_pm_power_up_setup);
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2014-06-24 19:34:38 +02:00
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/* test if we can (re)enable the CCI on our own */
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2015-03-14 22:58:33 +01:00
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BUG_ON(mcpm_loopback(tc2_pm_cluster_cache_disable) != 0);
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2013-08-06 20:10:08 +02:00
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pr_info("TC2 power management initialized\n");
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
early_initcall(tc2_pm_init);
|