2019-05-20 19:08:01 +02:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2018-03-08 10:48:46 +01:00
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/* Generic I/O port emulation.
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2009-05-14 00:56:35 +02:00
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*/
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#ifndef __ASM_GENERIC_IO_H
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#define __ASM_GENERIC_IO_H
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#include <asm/page.h> /* I/O is all done through memory accesses */
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2014-10-01 15:20:33 +02:00
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#include <linux/string.h> /* for memset() and memcpy() */
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2009-05-14 00:56:35 +02:00
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#include <linux/types.h>
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#ifdef CONFIG_GENERIC_IOMAP
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#include <asm-generic/iomap.h>
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#endif
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2019-02-22 13:59:59 +01:00
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#include <asm/mmiowb.h>
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2011-11-24 19:45:20 +01:00
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#include <asm-generic/pci_iomap.h>
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2018-04-05 15:09:09 +02:00
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#ifndef __io_br
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#define __io_br() barrier()
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#endif
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/* prevent prefetching of coherent DMA data ahead of a dma-complete */
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#ifndef __io_ar
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#ifdef rmb
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2019-02-22 19:04:52 +01:00
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#define __io_ar(v) rmb()
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2018-04-05 15:09:09 +02:00
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#else
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2019-02-22 19:04:52 +01:00
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#define __io_ar(v) barrier()
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2018-04-05 15:09:09 +02:00
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#endif
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#endif
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/* flush writes to coherent DMA data before possibly triggering a DMA read */
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#ifndef __io_bw
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#ifdef wmb
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#define __io_bw() wmb()
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#else
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#define __io_bw() barrier()
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#endif
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#endif
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/* serialize device access against a spin_unlock, usually handled there. */
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#ifndef __io_aw
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2019-02-22 13:59:59 +01:00
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#define __io_aw() mmiowb_set_pending()
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2018-04-05 15:09:09 +02:00
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#endif
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#ifndef __io_pbw
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#define __io_pbw() __io_bw()
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#endif
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#ifndef __io_paw
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#define __io_paw() __io_aw()
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#endif
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#ifndef __io_pbr
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#define __io_pbr() __io_br()
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#endif
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#ifndef __io_par
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2019-02-22 19:04:52 +01:00
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#define __io_par(v) __io_ar(v)
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2018-04-05 15:09:09 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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/*
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2014-10-01 15:20:33 +02:00
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* __raw_{read,write}{b,w,l,q}() access memory in native endianness.
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*
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* On some architectures memory mapped IO needs to be accessed differently.
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* On the simple architectures, we just read/write the memory location
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* directly.
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2009-05-14 00:56:35 +02:00
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*/
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2014-10-01 15:20:33 +02:00
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2010-10-18 09:09:39 +02:00
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#ifndef __raw_readb
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2014-10-01 15:20:33 +02:00
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#define __raw_readb __raw_readb
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2009-05-14 00:56:35 +02:00
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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2014-10-01 15:20:33 +02:00
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return *(const volatile u8 __force *)addr;
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2009-05-14 00:56:35 +02:00
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}
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2010-10-18 09:09:39 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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2010-10-18 09:09:39 +02:00
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#ifndef __raw_readw
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2014-10-01 15:20:33 +02:00
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#define __raw_readw __raw_readw
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2009-05-14 00:56:35 +02:00
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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2014-10-01 15:20:33 +02:00
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return *(const volatile u16 __force *)addr;
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2009-05-14 00:56:35 +02:00
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}
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2010-10-18 09:09:39 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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2010-10-18 09:09:39 +02:00
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#ifndef __raw_readl
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2014-10-01 15:20:33 +02:00
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#define __raw_readl __raw_readl
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2009-05-14 00:56:35 +02:00
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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2014-10-01 15:20:33 +02:00
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return *(const volatile u32 __force *)addr;
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2009-05-14 00:56:35 +02:00
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}
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2010-10-18 09:09:39 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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2014-10-01 15:20:33 +02:00
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#ifdef CONFIG_64BIT
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#ifndef __raw_readq
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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2013-01-07 14:17:23 +01:00
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{
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2014-10-01 15:20:33 +02:00
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return *(const volatile u64 __force *)addr;
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2013-01-07 14:17:23 +01:00
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}
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2014-10-01 15:20:33 +02:00
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#endif
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#endif /* CONFIG_64BIT */
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2009-05-14 00:56:35 +02:00
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2010-10-18 09:09:39 +02:00
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#ifndef __raw_writeb
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2014-10-01 15:20:33 +02:00
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2014-10-01 15:20:33 +02:00
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*(volatile u8 __force *)addr = value;
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2009-05-14 00:56:35 +02:00
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}
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2010-10-18 09:09:39 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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2010-10-18 09:09:39 +02:00
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#ifndef __raw_writew
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2014-10-01 15:20:33 +02:00
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 value, volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2014-10-01 15:20:33 +02:00
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*(volatile u16 __force *)addr = value;
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2009-05-14 00:56:35 +02:00
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}
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2010-10-18 09:09:39 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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2010-10-18 09:09:39 +02:00
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#ifndef __raw_writel
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2014-10-01 15:20:33 +02:00
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 value, volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2014-10-01 15:20:33 +02:00
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*(volatile u32 __force *)addr = value;
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2009-05-14 00:56:35 +02:00
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}
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2010-10-18 09:09:39 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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#ifdef CONFIG_64BIT
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2014-10-01 15:20:33 +02:00
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#ifndef __raw_writeq
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2014-10-01 15:20:33 +02:00
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*(volatile u64 __force *)addr = value;
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2009-05-14 00:56:35 +02:00
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}
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2012-11-29 12:50:30 +01:00
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#endif
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2014-10-01 15:20:33 +02:00
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#endif /* CONFIG_64BIT */
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2012-11-29 12:50:30 +01:00
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2014-10-01 15:20:33 +02:00
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/*
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* {read,write}{b,w,l,q}() access little endian memory and return result in
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* native endianness.
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*/
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2009-05-14 00:56:35 +02:00
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2014-10-01 15:20:33 +02:00
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#ifndef readb
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#define readb readb
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static inline u8 readb(const volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2018-04-05 15:09:10 +02:00
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u8 val;
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__io_br();
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val = __raw_readb(addr);
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2019-02-22 19:04:52 +01:00
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__io_ar(val);
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2018-04-05 15:09:10 +02:00
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return val;
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2009-05-14 00:56:35 +02:00
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}
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#endif
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2014-10-01 15:20:33 +02:00
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#ifndef readw
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#define readw readw
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static inline u16 readw(const volatile void __iomem *addr)
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{
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2018-04-05 15:09:10 +02:00
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u16 val;
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__io_br();
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val = __le16_to_cpu(__raw_readw(addr));
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2019-02-22 19:04:52 +01:00
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__io_ar(val);
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2018-04-05 15:09:10 +02:00
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return val;
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2014-10-01 15:20:33 +02:00
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}
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2011-02-22 12:06:43 +01:00
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#endif
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2014-10-01 15:20:33 +02:00
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#ifndef readl
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#define readl readl
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static inline u32 readl(const volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2018-04-05 15:09:10 +02:00
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u32 val;
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__io_br();
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val = __le32_to_cpu(__raw_readl(addr));
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2019-02-22 19:04:52 +01:00
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__io_ar(val);
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2018-04-05 15:09:10 +02:00
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return val;
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2009-05-14 00:56:35 +02:00
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}
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2014-10-01 15:20:33 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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2014-10-01 15:20:33 +02:00
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#ifdef CONFIG_64BIT
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#ifndef readq
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#define readq readq
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static inline u64 readq(const volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2018-04-05 15:09:10 +02:00
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u64 val;
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__io_br();
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val = __le64_to_cpu(__raw_readq(addr));
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2019-02-22 19:04:52 +01:00
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__io_ar(val);
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2018-04-05 15:09:10 +02:00
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return val;
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2009-05-14 00:56:35 +02:00
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}
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2014-10-01 15:20:33 +02:00
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#endif
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#endif /* CONFIG_64BIT */
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2009-05-14 00:56:35 +02:00
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2014-10-01 15:20:33 +02:00
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#ifndef writeb
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#define writeb writeb
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static inline void writeb(u8 value, volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2018-04-05 15:09:11 +02:00
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__io_bw();
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2014-10-01 15:20:33 +02:00
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__raw_writeb(value, addr);
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2018-04-05 15:09:11 +02:00
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__io_aw();
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2009-05-14 00:56:35 +02:00
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}
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2014-10-01 15:20:33 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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2014-10-01 15:20:33 +02:00
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#ifndef writew
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#define writew writew
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static inline void writew(u16 value, volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2018-04-05 15:09:11 +02:00
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__io_bw();
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2014-10-01 15:20:33 +02:00
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__raw_writew(cpu_to_le16(value), addr);
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2018-04-05 15:09:11 +02:00
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__io_aw();
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2009-05-14 00:56:35 +02:00
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}
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2014-10-01 15:20:33 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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2014-10-01 15:20:33 +02:00
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#ifndef writel
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#define writel writel
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static inline void writel(u32 value, volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2018-04-05 15:09:11 +02:00
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__io_bw();
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2014-10-01 15:20:33 +02:00
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__raw_writel(__cpu_to_le32(value), addr);
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2018-04-05 15:09:11 +02:00
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__io_aw();
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2009-05-14 00:56:35 +02:00
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}
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2014-10-01 15:20:33 +02:00
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#endif
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2009-05-14 00:56:35 +02:00
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2014-10-01 15:20:33 +02:00
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#ifdef CONFIG_64BIT
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#ifndef writeq
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#define writeq writeq
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static inline void writeq(u64 value, volatile void __iomem *addr)
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2009-05-14 00:56:35 +02:00
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{
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2018-04-05 15:09:11 +02:00
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__io_bw();
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2014-10-01 15:20:33 +02:00
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__raw_writeq(__cpu_to_le64(value), addr);
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2018-04-05 15:09:11 +02:00
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__io_aw();
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2009-05-14 00:56:35 +02:00
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}
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2014-10-01 15:20:33 +02:00
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#endif
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#endif /* CONFIG_64BIT */
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2009-05-14 00:56:35 +02:00
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2014-11-11 19:55:45 +01:00
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/*
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* {read,write}{b,w,l,q}_relaxed() are like the regular version, but
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* are not guaranteed to provide ordering against spinlocks or memory
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* accesses.
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*/
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#ifndef readb_relaxed
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2018-04-06 20:02:45 +02:00
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#define readb_relaxed readb_relaxed
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static inline u8 readb_relaxed(const volatile void __iomem *addr)
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{
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return __raw_readb(addr);
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}
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2014-11-11 19:55:45 +01:00
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#endif
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#ifndef readw_relaxed
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2018-04-06 20:02:45 +02:00
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#define readw_relaxed readw_relaxed
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static inline u16 readw_relaxed(const volatile void __iomem *addr)
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{
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return __le16_to_cpu(__raw_readw(addr));
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}
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2014-11-11 19:55:45 +01:00
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#endif
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#ifndef readl_relaxed
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2018-04-06 20:02:45 +02:00
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#define readl_relaxed readl_relaxed
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static inline u32 readl_relaxed(const volatile void __iomem *addr)
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{
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return __le32_to_cpu(__raw_readl(addr));
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}
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2014-11-11 19:55:45 +01:00
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#endif
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2016-04-26 12:38:20 +02:00
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#if defined(readq) && !defined(readq_relaxed)
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2018-04-06 20:02:45 +02:00
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#define readq_relaxed readq_relaxed
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static inline u64 readq_relaxed(const volatile void __iomem *addr)
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{
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return __le64_to_cpu(__raw_readq(addr));
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}
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2014-11-11 19:55:45 +01:00
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#endif
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2013-09-03 11:44:00 +02:00
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#ifndef writeb_relaxed
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2018-04-06 20:02:46 +02:00
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#define writeb_relaxed writeb_relaxed
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static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)
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{
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__raw_writeb(value, addr);
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}
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2013-09-03 11:44:00 +02:00
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#endif
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#ifndef writew_relaxed
|
2018-04-06 20:02:46 +02:00
|
|
|
#define writew_relaxed writew_relaxed
|
|
|
|
static inline void writew_relaxed(u16 value, volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
__raw_writew(cpu_to_le16(value), addr);
|
|
|
|
}
|
2013-09-03 11:44:00 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef writel_relaxed
|
2018-04-06 20:02:46 +02:00
|
|
|
#define writel_relaxed writel_relaxed
|
|
|
|
static inline void writel_relaxed(u32 value, volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
__raw_writel(__cpu_to_le32(value), addr);
|
|
|
|
}
|
2013-09-03 11:44:00 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2016-04-26 12:38:20 +02:00
|
|
|
#if defined(writeq) && !defined(writeq_relaxed)
|
2018-04-06 20:02:46 +02:00
|
|
|
#define writeq_relaxed writeq_relaxed
|
|
|
|
static inline void writeq_relaxed(u64 value, volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
__raw_writeq(__cpu_to_le64(value), addr);
|
|
|
|
}
|
2014-11-11 19:55:45 +01:00
|
|
|
#endif
|
|
|
|
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
/*
|
|
|
|
* {read,write}s{b,w,l,q}() repeatedly access the same memory address in
|
|
|
|
* native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
|
|
|
|
*/
|
|
|
|
#ifndef readsb
|
|
|
|
#define readsb readsb
|
|
|
|
static inline void readsb(const volatile void __iomem *addr, void *buffer,
|
|
|
|
unsigned int count)
|
2009-05-14 00:56:35 +02:00
|
|
|
{
|
|
|
|
if (count) {
|
|
|
|
u8 *buf = buffer;
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
|
2009-05-14 00:56:35 +02:00
|
|
|
do {
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
u8 x = __raw_readb(addr);
|
2009-05-14 00:56:35 +02:00
|
|
|
*buf++ = x;
|
|
|
|
} while (--count);
|
|
|
|
}
|
|
|
|
}
|
2010-10-18 09:09:39 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
#ifndef readsw
|
|
|
|
#define readsw readsw
|
|
|
|
static inline void readsw(const volatile void __iomem *addr, void *buffer,
|
|
|
|
unsigned int count)
|
2009-05-14 00:56:35 +02:00
|
|
|
{
|
|
|
|
if (count) {
|
|
|
|
u16 *buf = buffer;
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
|
2009-05-14 00:56:35 +02:00
|
|
|
do {
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
u16 x = __raw_readw(addr);
|
2009-05-14 00:56:35 +02:00
|
|
|
*buf++ = x;
|
|
|
|
} while (--count);
|
|
|
|
}
|
|
|
|
}
|
2010-10-18 09:09:39 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
#ifndef readsl
|
|
|
|
#define readsl readsl
|
|
|
|
static inline void readsl(const volatile void __iomem *addr, void *buffer,
|
|
|
|
unsigned int count)
|
2009-05-14 00:56:35 +02:00
|
|
|
{
|
|
|
|
if (count) {
|
|
|
|
u32 *buf = buffer;
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
|
2009-05-14 00:56:35 +02:00
|
|
|
do {
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
u32 x = __raw_readl(addr);
|
2009-05-14 00:56:35 +02:00
|
|
|
*buf++ = x;
|
|
|
|
} while (--count);
|
|
|
|
}
|
|
|
|
}
|
2010-10-18 09:09:39 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
#ifndef readsq
|
|
|
|
#define readsq readsq
|
|
|
|
static inline void readsq(const volatile void __iomem *addr, void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
if (count) {
|
|
|
|
u64 *buf = buffer;
|
|
|
|
|
|
|
|
do {
|
|
|
|
u64 x = __raw_readq(addr);
|
|
|
|
*buf++ = x;
|
|
|
|
} while (--count);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
|
|
|
|
#ifndef writesb
|
|
|
|
#define writesb writesb
|
|
|
|
static inline void writesb(volatile void __iomem *addr, const void *buffer,
|
|
|
|
unsigned int count)
|
2009-05-14 00:56:35 +02:00
|
|
|
{
|
|
|
|
if (count) {
|
|
|
|
const u8 *buf = buffer;
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
|
2009-05-14 00:56:35 +02:00
|
|
|
do {
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
__raw_writeb(*buf++, addr);
|
2009-05-14 00:56:35 +02:00
|
|
|
} while (--count);
|
|
|
|
}
|
|
|
|
}
|
2010-10-18 09:09:39 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
#ifndef writesw
|
|
|
|
#define writesw writesw
|
|
|
|
static inline void writesw(volatile void __iomem *addr, const void *buffer,
|
|
|
|
unsigned int count)
|
2009-05-14 00:56:35 +02:00
|
|
|
{
|
|
|
|
if (count) {
|
|
|
|
const u16 *buf = buffer;
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
|
2009-05-14 00:56:35 +02:00
|
|
|
do {
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
__raw_writew(*buf++, addr);
|
2009-05-14 00:56:35 +02:00
|
|
|
} while (--count);
|
|
|
|
}
|
|
|
|
}
|
2010-10-18 09:09:39 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
#ifndef writesl
|
|
|
|
#define writesl writesl
|
|
|
|
static inline void writesl(volatile void __iomem *addr, const void *buffer,
|
|
|
|
unsigned int count)
|
2009-05-14 00:56:35 +02:00
|
|
|
{
|
|
|
|
if (count) {
|
|
|
|
const u32 *buf = buffer;
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
|
2009-05-14 00:56:35 +02:00
|
|
|
do {
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
__raw_writel(*buf++, addr);
|
2009-05-14 00:56:35 +02:00
|
|
|
} while (--count);
|
|
|
|
}
|
|
|
|
}
|
2010-10-18 09:09:39 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
#ifndef writesq
|
|
|
|
#define writesq writesq
|
|
|
|
static inline void writesq(volatile void __iomem *addr, const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
if (count) {
|
|
|
|
const u64 *buf = buffer;
|
|
|
|
|
|
|
|
do {
|
|
|
|
__raw_writeq(*buf++, addr);
|
|
|
|
} while (--count);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_64BIT */
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2014-10-01 15:20:33 +02:00
|
|
|
#ifndef PCI_IOBASE
|
|
|
|
#define PCI_IOBASE ((void __iomem *)0)
|
|
|
|
#endif
|
|
|
|
|
2011-02-22 12:06:43 +01:00
|
|
|
#ifndef IO_SPACE_LIMIT
|
|
|
|
#define IO_SPACE_LIMIT 0xffff
|
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2018-03-14 19:15:50 +01:00
|
|
|
#include <linux/logic_pio.h>
|
|
|
|
|
2014-10-01 15:20:33 +02:00
|
|
|
/*
|
|
|
|
* {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be
|
|
|
|
* implemented on hardware that needs an additional delay for I/O accesses to
|
|
|
|
* take effect.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef inb
|
|
|
|
#define inb inb
|
|
|
|
static inline u8 inb(unsigned long addr)
|
|
|
|
{
|
2018-04-05 15:09:13 +02:00
|
|
|
u8 val;
|
|
|
|
|
|
|
|
__io_pbr();
|
|
|
|
val = __raw_readb(PCI_IOBASE + addr);
|
2019-02-22 19:04:52 +01:00
|
|
|
__io_par(val);
|
2018-04-05 15:09:13 +02:00
|
|
|
return val;
|
2014-10-01 15:20:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef inw
|
|
|
|
#define inw inw
|
|
|
|
static inline u16 inw(unsigned long addr)
|
|
|
|
{
|
2018-04-05 15:09:13 +02:00
|
|
|
u16 val;
|
|
|
|
|
|
|
|
__io_pbr();
|
|
|
|
val = __le16_to_cpu(__raw_readw(PCI_IOBASE + addr));
|
2019-02-22 19:04:52 +01:00
|
|
|
__io_par(val);
|
2018-04-05 15:09:13 +02:00
|
|
|
return val;
|
2014-10-01 15:20:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef inl
|
|
|
|
#define inl inl
|
|
|
|
static inline u32 inl(unsigned long addr)
|
|
|
|
{
|
2018-04-05 15:09:13 +02:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
__io_pbr();
|
|
|
|
val = __le32_to_cpu(__raw_readl(PCI_IOBASE + addr));
|
2019-02-22 19:04:52 +01:00
|
|
|
__io_par(val);
|
2018-04-05 15:09:13 +02:00
|
|
|
return val;
|
2014-10-01 15:20:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outb
|
|
|
|
#define outb outb
|
|
|
|
static inline void outb(u8 value, unsigned long addr)
|
|
|
|
{
|
2018-04-05 15:09:12 +02:00
|
|
|
__io_pbw();
|
|
|
|
__raw_writeb(value, PCI_IOBASE + addr);
|
|
|
|
__io_paw();
|
2014-10-01 15:20:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outw
|
|
|
|
#define outw outw
|
|
|
|
static inline void outw(u16 value, unsigned long addr)
|
|
|
|
{
|
2018-04-05 15:09:12 +02:00
|
|
|
__io_pbw();
|
|
|
|
__raw_writew(cpu_to_le16(value), PCI_IOBASE + addr);
|
|
|
|
__io_paw();
|
2014-10-01 15:20:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outl
|
|
|
|
#define outl outl
|
|
|
|
static inline void outl(u32 value, unsigned long addr)
|
|
|
|
{
|
2018-04-05 15:09:12 +02:00
|
|
|
__io_pbw();
|
|
|
|
__raw_writel(cpu_to_le32(value), PCI_IOBASE + addr);
|
|
|
|
__io_paw();
|
2014-10-01 15:20:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef inb_p
|
|
|
|
#define inb_p inb_p
|
|
|
|
static inline u8 inb_p(unsigned long addr)
|
|
|
|
{
|
|
|
|
return inb(addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef inw_p
|
|
|
|
#define inw_p inw_p
|
|
|
|
static inline u16 inw_p(unsigned long addr)
|
|
|
|
{
|
|
|
|
return inw(addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef inl_p
|
|
|
|
#define inl_p inl_p
|
|
|
|
static inline u32 inl_p(unsigned long addr)
|
|
|
|
{
|
|
|
|
return inl(addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outb_p
|
|
|
|
#define outb_p outb_p
|
|
|
|
static inline void outb_p(u8 value, unsigned long addr)
|
|
|
|
{
|
|
|
|
outb(value, addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outw_p
|
|
|
|
#define outw_p outw_p
|
|
|
|
static inline void outw_p(u16 value, unsigned long addr)
|
|
|
|
{
|
|
|
|
outw(value, addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outl_p
|
|
|
|
#define outl_p outl_p
|
|
|
|
static inline void outl_p(u32 value, unsigned long addr)
|
|
|
|
{
|
|
|
|
outl(value, addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
/*
|
|
|
|
* {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
|
|
|
|
* single I/O port multiple times.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef insb
|
|
|
|
#define insb insb
|
|
|
|
static inline void insb(unsigned long addr, void *buffer, unsigned int count)
|
|
|
|
{
|
|
|
|
readsb(PCI_IOBASE + addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef insw
|
|
|
|
#define insw insw
|
|
|
|
static inline void insw(unsigned long addr, void *buffer, unsigned int count)
|
|
|
|
{
|
|
|
|
readsw(PCI_IOBASE + addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef insl
|
|
|
|
#define insl insl
|
|
|
|
static inline void insl(unsigned long addr, void *buffer, unsigned int count)
|
|
|
|
{
|
|
|
|
readsl(PCI_IOBASE + addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outsb
|
|
|
|
#define outsb outsb
|
|
|
|
static inline void outsb(unsigned long addr, const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
writesb(PCI_IOBASE + addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outsw
|
|
|
|
#define outsw outsw
|
|
|
|
static inline void outsw(unsigned long addr, const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
writesw(PCI_IOBASE + addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outsl
|
|
|
|
#define outsl outsl
|
|
|
|
static inline void outsl(unsigned long addr, const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
writesl(PCI_IOBASE + addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef insb_p
|
|
|
|
#define insb_p insb_p
|
|
|
|
static inline void insb_p(unsigned long addr, void *buffer, unsigned int count)
|
|
|
|
{
|
|
|
|
insb(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef insw_p
|
|
|
|
#define insw_p insw_p
|
|
|
|
static inline void insw_p(unsigned long addr, void *buffer, unsigned int count)
|
|
|
|
{
|
|
|
|
insw(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef insl_p
|
|
|
|
#define insl_p insl_p
|
|
|
|
static inline void insl_p(unsigned long addr, void *buffer, unsigned int count)
|
|
|
|
{
|
|
|
|
insl(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outsb_p
|
|
|
|
#define outsb_p outsb_p
|
|
|
|
static inline void outsb_p(unsigned long addr, const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
outsb(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outsw_p
|
|
|
|
#define outsw_p outsw_p
|
|
|
|
static inline void outsw_p(unsigned long addr, const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
outsw(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef outsl_p
|
|
|
|
#define outsl_p outsl_p
|
|
|
|
static inline void outsl_p(unsigned long addr, const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
outsl(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-10-01 15:20:33 +02:00
|
|
|
#ifndef CONFIG_GENERIC_IOMAP
|
|
|
|
#ifndef ioread8
|
|
|
|
#define ioread8 ioread8
|
|
|
|
static inline u8 ioread8(const volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
return readb(addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef ioread16
|
|
|
|
#define ioread16 ioread16
|
|
|
|
static inline u16 ioread16(const volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
return readw(addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef ioread32
|
|
|
|
#define ioread32 ioread32
|
|
|
|
static inline u32 ioread32(const volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
return readl(addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-05-19 17:10:56 +02:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
#ifndef ioread64
|
|
|
|
#define ioread64 ioread64
|
|
|
|
static inline u64 ioread64(const volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
return readq(addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
|
2014-10-01 15:20:33 +02:00
|
|
|
#ifndef iowrite8
|
|
|
|
#define iowrite8 iowrite8
|
|
|
|
static inline void iowrite8(u8 value, volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
writeb(value, addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef iowrite16
|
|
|
|
#define iowrite16 iowrite16
|
|
|
|
static inline void iowrite16(u16 value, volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
writew(value, addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef iowrite32
|
|
|
|
#define iowrite32 iowrite32
|
|
|
|
static inline void iowrite32(u32 value, volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
writel(value, addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-05-19 17:10:56 +02:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
#ifndef iowrite64
|
|
|
|
#define iowrite64 iowrite64
|
|
|
|
static inline void iowrite64(u64 value, volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
writeq(value, addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
|
2014-10-01 15:20:33 +02:00
|
|
|
#ifndef ioread16be
|
|
|
|
#define ioread16be ioread16be
|
|
|
|
static inline u16 ioread16be(const volatile void __iomem *addr)
|
|
|
|
{
|
asm-generic/io.h: allow barriers in io{read,write}{16,32}be
While reviewing the addition of io{read,write}64be accessors, Arnd
-finds a potential problem:
"If an architecture overrides readq/writeq to have barriers but does
not override ioread64be/iowrite64be, this will lack the barriers and
behave differently from the little-endian version. I think the only
affected architecture is ARC, since ARM and ARM64 both override the
big-endian accessors to have the correct barriers, and all others
don't use barriers at all."
-suggests a fix for the same problem in existing code (16/32-bit
accessors); the fix leads "to a double-swap on architectures that
don't override the io{read,write}{16,32}be accessors, but it will
work correctly on all architectures without them having to override
these accessors."
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-05-19 17:10:43 +02:00
|
|
|
return swab16(readw(addr));
|
2014-10-01 15:20:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef ioread32be
|
|
|
|
#define ioread32be ioread32be
|
|
|
|
static inline u32 ioread32be(const volatile void __iomem *addr)
|
|
|
|
{
|
asm-generic/io.h: allow barriers in io{read,write}{16,32}be
While reviewing the addition of io{read,write}64be accessors, Arnd
-finds a potential problem:
"If an architecture overrides readq/writeq to have barriers but does
not override ioread64be/iowrite64be, this will lack the barriers and
behave differently from the little-endian version. I think the only
affected architecture is ARC, since ARM and ARM64 both override the
big-endian accessors to have the correct barriers, and all others
don't use barriers at all."
-suggests a fix for the same problem in existing code (16/32-bit
accessors); the fix leads "to a double-swap on architectures that
don't override the io{read,write}{16,32}be accessors, but it will
work correctly on all architectures without them having to override
these accessors."
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-05-19 17:10:43 +02:00
|
|
|
return swab32(readl(addr));
|
2014-10-01 15:20:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-05-19 17:10:56 +02:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
#ifndef ioread64be
|
|
|
|
#define ioread64be ioread64be
|
|
|
|
static inline u64 ioread64be(const volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
return swab64(readq(addr));
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
|
2014-10-01 15:20:33 +02:00
|
|
|
#ifndef iowrite16be
|
|
|
|
#define iowrite16be iowrite16be
|
|
|
|
static inline void iowrite16be(u16 value, void volatile __iomem *addr)
|
|
|
|
{
|
asm-generic/io.h: allow barriers in io{read,write}{16,32}be
While reviewing the addition of io{read,write}64be accessors, Arnd
-finds a potential problem:
"If an architecture overrides readq/writeq to have barriers but does
not override ioread64be/iowrite64be, this will lack the barriers and
behave differently from the little-endian version. I think the only
affected architecture is ARC, since ARM and ARM64 both override the
big-endian accessors to have the correct barriers, and all others
don't use barriers at all."
-suggests a fix for the same problem in existing code (16/32-bit
accessors); the fix leads "to a double-swap on architectures that
don't override the io{read,write}{16,32}be accessors, but it will
work correctly on all architectures without them having to override
these accessors."
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-05-19 17:10:43 +02:00
|
|
|
writew(swab16(value), addr);
|
2014-10-01 15:20:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef iowrite32be
|
|
|
|
#define iowrite32be iowrite32be
|
|
|
|
static inline void iowrite32be(u32 value, volatile void __iomem *addr)
|
|
|
|
{
|
asm-generic/io.h: allow barriers in io{read,write}{16,32}be
While reviewing the addition of io{read,write}64be accessors, Arnd
-finds a potential problem:
"If an architecture overrides readq/writeq to have barriers but does
not override ioread64be/iowrite64be, this will lack the barriers and
behave differently from the little-endian version. I think the only
affected architecture is ARC, since ARM and ARM64 both override the
big-endian accessors to have the correct barriers, and all others
don't use barriers at all."
-suggests a fix for the same problem in existing code (16/32-bit
accessors); the fix leads "to a double-swap on architectures that
don't override the io{read,write}{16,32}be accessors, but it will
work correctly on all architectures without them having to override
these accessors."
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-05-19 17:10:43 +02:00
|
|
|
writel(swab32(value), addr);
|
2014-10-01 15:20:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
|
2016-05-19 17:10:56 +02:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
#ifndef iowrite64be
|
|
|
|
#define iowrite64be iowrite64be
|
|
|
|
static inline void iowrite64be(u64 value, volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
writeq(swab64(value), addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
#ifndef ioread8_rep
|
|
|
|
#define ioread8_rep ioread8_rep
|
|
|
|
static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
readsb(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef ioread16_rep
|
|
|
|
#define ioread16_rep ioread16_rep
|
|
|
|
static inline void ioread16_rep(const volatile void __iomem *addr,
|
|
|
|
void *buffer, unsigned int count)
|
|
|
|
{
|
|
|
|
readsw(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef ioread32_rep
|
|
|
|
#define ioread32_rep ioread32_rep
|
|
|
|
static inline void ioread32_rep(const volatile void __iomem *addr,
|
|
|
|
void *buffer, unsigned int count)
|
|
|
|
{
|
|
|
|
readsl(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-05-19 17:10:56 +02:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
#ifndef ioread64_rep
|
|
|
|
#define ioread64_rep ioread64_rep
|
|
|
|
static inline void ioread64_rep(const volatile void __iomem *addr,
|
|
|
|
void *buffer, unsigned int count)
|
|
|
|
{
|
|
|
|
readsq(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
|
asm-generic/io.h: Implement generic {read,write}s*()
Currently driver writers need to use io{read,write}{8,16,32}_rep() when
accessing FIFO registers portably. This is bad for two reasons: it is
inconsistent with how other registers are accessed using the standard
{read,write}{b,w,l}() functions, which can lead to confusion. On some
architectures the io{read,write}*() functions also need to perform some
extra checks to determine whether an address is memory-mapped or refers
to I/O space. Drivers which can be expected to never use I/O can safely
use the {read,write}s{b,w,l,q}(), just like they use their non-string
variants and there's no need for these extra checks.
This patch implements generic versions of readsb(), readsw(), readsl(),
readsq(), writesb(), writesw(), writesl() and writesq(). Variants of
these string functions for I/O accesses (ins*() and outs*() as well as
ioread*_rep() and iowrite*_rep()) are now implemented in terms of the
new functions.
Going forward, {read,write}{,s}{b,w,l,q}() should be used consistently
by drivers for devices that will only ever be memory-mapped and hence
don't need to access I/O space, whereas io{read,write}{8,16,32}_rep()
should be used by drivers for devices that can be either memory-mapped
or I/O-mapped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-04 13:07:57 +02:00
|
|
|
#ifndef iowrite8_rep
|
|
|
|
#define iowrite8_rep iowrite8_rep
|
|
|
|
static inline void iowrite8_rep(volatile void __iomem *addr,
|
|
|
|
const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
writesb(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef iowrite16_rep
|
|
|
|
#define iowrite16_rep iowrite16_rep
|
|
|
|
static inline void iowrite16_rep(volatile void __iomem *addr,
|
|
|
|
const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
writesw(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef iowrite32_rep
|
|
|
|
#define iowrite32_rep iowrite32_rep
|
|
|
|
static inline void iowrite32_rep(volatile void __iomem *addr,
|
|
|
|
const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
writesl(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
2016-05-19 17:10:56 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
#ifndef iowrite64_rep
|
|
|
|
#define iowrite64_rep iowrite64_rep
|
|
|
|
static inline void iowrite64_rep(volatile void __iomem *addr,
|
|
|
|
const void *buffer,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
writesq(addr, buffer, count);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_64BIT */
|
2014-10-01 15:20:33 +02:00
|
|
|
#endif /* CONFIG_GENERIC_IOMAP */
|
|
|
|
|
2009-05-14 00:56:35 +02:00
|
|
|
#ifdef __KERNEL__
|
|
|
|
|
|
|
|
#include <linux/vmalloc.h>
|
2014-10-01 15:20:33 +02:00
|
|
|
#define __io_virt(x) ((void __force *)(x))
|
2009-05-14 00:56:35 +02:00
|
|
|
|
|
|
|
#ifndef CONFIG_GENERIC_IOMAP
|
|
|
|
struct pci_dev;
|
2012-11-29 12:50:30 +01:00
|
|
|
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
|
|
|
|
|
|
|
|
#ifndef pci_iounmap
|
2014-10-01 15:20:33 +02:00
|
|
|
#define pci_iounmap pci_iounmap
|
2009-05-14 00:56:35 +02:00
|
|
|
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
|
|
|
|
{
|
|
|
|
}
|
2012-11-29 12:50:30 +01:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
#endif /* CONFIG_GENERIC_IOMAP */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Change virtual addresses to physical addresses and vv.
|
|
|
|
* These are pretty trivial
|
|
|
|
*/
|
2012-11-29 12:50:30 +01:00
|
|
|
#ifndef virt_to_phys
|
2014-10-01 15:20:33 +02:00
|
|
|
#define virt_to_phys virt_to_phys
|
2009-05-14 00:56:35 +02:00
|
|
|
static inline unsigned long virt_to_phys(volatile void *address)
|
|
|
|
{
|
|
|
|
return __pa((unsigned long)address);
|
|
|
|
}
|
2014-10-01 15:20:33 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2014-10-01 15:20:33 +02:00
|
|
|
#ifndef phys_to_virt
|
|
|
|
#define phys_to_virt phys_to_virt
|
2009-05-14 00:56:35 +02:00
|
|
|
static inline void *phys_to_virt(unsigned long address)
|
|
|
|
{
|
|
|
|
return __va(address);
|
|
|
|
}
|
2012-11-29 12:50:30 +01:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2015-07-10 02:28:16 +02:00
|
|
|
/**
|
|
|
|
* DOC: ioremap() and ioremap_*() variants
|
|
|
|
*
|
|
|
|
* If you have an IOMMU your architecture is expected to have both ioremap()
|
|
|
|
* and iounmap() implemented otherwise the asm-generic helpers will provide a
|
|
|
|
* direct mapping.
|
|
|
|
*
|
|
|
|
* There are ioremap_*() call variants, if you have no IOMMU we naturally will
|
|
|
|
* default to direct mapping for all of them, you can override these defaults.
|
|
|
|
* If you have an IOMMU you are highly encouraged to provide your own
|
|
|
|
* ioremap variant implementation as there currently is no safe architecture
|
|
|
|
* agnostic default. To avoid possible improper behaviour default asm-generic
|
|
|
|
* ioremap_*() variants all return NULL when an IOMMU is available. If you've
|
|
|
|
* defined your own ioremap_*() variant you must then declare your own
|
|
|
|
* ioremap_*() variant as defined to itself to avoid the default NULL return.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifdef CONFIG_MMU
|
|
|
|
|
|
|
|
#ifndef ioremap_uc
|
|
|
|
#define ioremap_uc ioremap_uc
|
|
|
|
static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#else /* !CONFIG_MMU */
|
|
|
|
|
2009-05-14 00:56:35 +02:00
|
|
|
/*
|
|
|
|
* Change "struct page" to physical address.
|
2011-07-02 17:17:35 +02:00
|
|
|
*
|
|
|
|
* This implementation is for the no-MMU case only... if you have an MMU
|
|
|
|
* you'll need to provide your own definitions.
|
2009-05-14 00:56:35 +02:00
|
|
|
*/
|
2014-10-01 15:20:33 +02:00
|
|
|
|
|
|
|
#ifndef ioremap
|
|
|
|
#define ioremap ioremap
|
|
|
|
static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
|
2009-05-14 00:56:35 +02:00
|
|
|
{
|
2014-10-01 15:20:33 +02:00
|
|
|
return (void __iomem *)(unsigned long)offset;
|
2009-05-14 00:56:35 +02:00
|
|
|
}
|
2014-10-01 15:20:33 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2014-10-01 15:20:33 +02:00
|
|
|
#ifndef __ioremap
|
|
|
|
#define __ioremap __ioremap
|
|
|
|
static inline void __iomem *__ioremap(phys_addr_t offset, size_t size,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
return ioremap(offset, size);
|
|
|
|
}
|
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2017-11-22 11:57:46 +01:00
|
|
|
#ifndef iounmap
|
|
|
|
#define iounmap iounmap
|
|
|
|
|
|
|
|
static inline void iounmap(void __iomem *addr)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_MMU */
|
2009-05-14 00:56:35 +02:00
|
|
|
#ifndef ioremap_nocache
|
2017-11-22 11:57:46 +01:00
|
|
|
void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
|
2014-10-01 15:20:33 +02:00
|
|
|
#define ioremap_nocache ioremap_nocache
|
|
|
|
static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
|
|
|
|
{
|
|
|
|
return ioremap(offset, size);
|
|
|
|
}
|
2009-05-14 00:56:35 +02:00
|
|
|
#endif
|
|
|
|
|
x86/mm: Add ioremap_uc() helper to map memory uncacheable (not UC-)
ioremap_nocache() currently uses UC- by default. Our goal is to
eventually make UC the default. Linux maps UC- to PCD=1, PWT=0
page attributes on non-PAT systems. Linux maps UC to PCD=1,
PWT=1 page attributes on non-PAT systems. On non-PAT and PAT
systems a WC MTRR has different effects on pages with either of
these attributes. In order to help with a smooth transition its
best to enable use of UC (PCD,1, PWT=1) on a region as that
ensures a WC MTRR will have no effect on a region, this however
requires us to have an way to declare a region as UC and we
currently do not have a way to do this.
WC MTRR on non-PAT system with PCD=1, PWT=0 (UC-) yields WC.
WC MTRR on non-PAT system with PCD=1, PWT=1 (UC) yields UC.
WC MTRR on PAT system with PCD=1, PWT=0 (UC-) yields WC.
WC MTRR on PAT system with PCD=1, PWT=1 (UC) yields UC.
A flip of the default ioremap_nocache() behaviour from UC- to UC
can therefore regress a memory region from effective memory type
WC to UC if MTRRs are used. Use of MTRRs should be phased out
and in the best case only arch_phys_wc_add() use will remain,
even if this happens arch_phys_wc_add() will have an effect on
non-PAT systems and changes to default ioremap_nocache()
behaviour could regress drivers.
Now, ideally we'd use ioremap_nocache() on the regions in which
we'd need uncachable memory types and avoid any MTRRs on those
regions. There are however some restrictions on MTRRs use, such
as the requirement of having the base and size of variable sized
MTRRs to be powers of two, which could mean having to use a WC
MTRR over a large area which includes a region in which
write-combining effects are undesirable.
Add ioremap_uc() to help with the both phasing out of MTRR use
and also provide a way to blacklist small WC undesirable regions
in devices with mixed regions which are size-implicated to use
large WC MTRRs. Use of ioremap_uc() helps phase out MTRR use by
avoiding regressions with an eventual flip of default behaviour
or ioremap_nocache() from UC- to UC.
Drivers working with WC MTRRs can use the below table to review
and consider the use of ioremap*() and similar helpers to ensure
appropriate behaviour long term even if default
ioremap_nocache() behaviour changes from UC- to UC.
Although ioremap_uc() is being added we leave set_memory_uc() to
use UC- as only initial memory type setup is required to be able
to accommodate existing device drivers and phase out MTRR use.
It should also be clarified that set_memory_uc() cannot be used
with IO memory, even though its use will not return any errors,
it really has no effect.
----------------------------------------------------------------------
MTRR Non-PAT PAT Linux ioremap value Effective memory type
----------------------------------------------------------------------
Non-PAT | PAT
PAT
|PCD
||PWT
|||
WC 000 WB _PAGE_CACHE_MODE_WB WC | WC
WC 001 WC _PAGE_CACHE_MODE_WC WC* | WC
WC 010 UC- _PAGE_CACHE_MODE_UC_MINUS WC* | WC
WC 011 UC _PAGE_CACHE_MODE_UC UC | UC
----------------------------------------------------------------------
Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Antonino Daplas <adaplas@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Davidlohr Bueso <dbueso@suse.de>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mel Gorman <mgorman@suse.de>
Cc: Mike Travis <travis@sgi.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Suresh Siddha <sbsiddha@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Toshi Kani <toshi.kani@hp.com>
Cc: Ville Syrjälä <syrjala@sci.fi>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-fbdev@vger.kernel.org
Link: http://lkml.kernel.org/r/1430343851-967-2-git-send-email-mcgrof@do-not-panic.com
Link: http://lkml.kernel.org/r/1431332153-18566-9-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-05-11 10:15:53 +02:00
|
|
|
#ifndef ioremap_uc
|
|
|
|
#define ioremap_uc ioremap_uc
|
|
|
|
static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size)
|
|
|
|
{
|
|
|
|
return ioremap_nocache(offset, size);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2009-05-14 00:56:35 +02:00
|
|
|
#ifndef ioremap_wc
|
2014-10-01 15:20:33 +02:00
|
|
|
#define ioremap_wc ioremap_wc
|
|
|
|
static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size)
|
|
|
|
{
|
|
|
|
return ioremap_nocache(offset, size);
|
|
|
|
}
|
2009-05-14 00:56:35 +02:00
|
|
|
#endif
|
|
|
|
|
2015-06-04 18:55:15 +02:00
|
|
|
#ifndef ioremap_wt
|
|
|
|
#define ioremap_wt ioremap_wt
|
|
|
|
static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size)
|
|
|
|
{
|
|
|
|
return ioremap_nocache(offset, size);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-04-08 00:39:19 +02:00
|
|
|
#ifdef CONFIG_HAS_IOPORT_MAP
|
2009-05-14 00:56:35 +02:00
|
|
|
#ifndef CONFIG_GENERIC_IOMAP
|
2014-10-01 15:20:33 +02:00
|
|
|
#ifndef ioport_map
|
|
|
|
#define ioport_map ioport_map
|
2009-05-14 00:56:35 +02:00
|
|
|
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
|
|
|
{
|
2018-09-13 14:48:27 +02:00
|
|
|
port &= IO_SPACE_LIMIT;
|
|
|
|
return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
|
2009-05-14 00:56:35 +02:00
|
|
|
}
|
2014-10-01 15:20:33 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2014-10-01 15:20:33 +02:00
|
|
|
#ifndef ioport_unmap
|
|
|
|
#define ioport_unmap ioport_unmap
|
2009-05-14 00:56:35 +02:00
|
|
|
static inline void ioport_unmap(void __iomem *p)
|
|
|
|
{
|
|
|
|
}
|
2014-10-01 15:20:33 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
#else /* CONFIG_GENERIC_IOMAP */
|
|
|
|
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
|
|
|
|
extern void ioport_unmap(void __iomem *p);
|
|
|
|
#endif /* CONFIG_GENERIC_IOMAP */
|
2014-04-08 00:39:19 +02:00
|
|
|
#endif /* CONFIG_HAS_IOPORT_MAP */
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2017-06-30 19:09:33 +02:00
|
|
|
/*
|
|
|
|
* Convert a virtual cached pointer to an uncached pointer
|
|
|
|
*/
|
2013-05-21 16:08:22 +02:00
|
|
|
#ifndef xlate_dev_kmem_ptr
|
2014-10-01 15:20:33 +02:00
|
|
|
#define xlate_dev_kmem_ptr xlate_dev_kmem_ptr
|
|
|
|
static inline void *xlate_dev_kmem_ptr(void *addr)
|
|
|
|
{
|
|
|
|
return addr;
|
|
|
|
}
|
2013-05-21 16:08:22 +02:00
|
|
|
#endif
|
2014-10-01 15:20:33 +02:00
|
|
|
|
2013-05-21 16:08:22 +02:00
|
|
|
#ifndef xlate_dev_mem_ptr
|
2014-10-01 15:20:33 +02:00
|
|
|
#define xlate_dev_mem_ptr xlate_dev_mem_ptr
|
|
|
|
static inline void *xlate_dev_mem_ptr(phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return __va(addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef unxlate_dev_mem_ptr
|
|
|
|
#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
|
|
|
|
static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
|
|
|
|
{
|
|
|
|
}
|
2013-05-21 16:08:22 +02:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2012-11-23 17:13:05 +01:00
|
|
|
#ifdef CONFIG_VIRT_TO_BUS
|
2009-05-14 00:56:35 +02:00
|
|
|
#ifndef virt_to_bus
|
2014-10-01 15:20:33 +02:00
|
|
|
static inline unsigned long virt_to_bus(void *address)
|
2009-05-14 00:56:35 +02:00
|
|
|
{
|
2014-10-01 15:20:33 +02:00
|
|
|
return (unsigned long)address;
|
2009-05-14 00:56:35 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void *bus_to_virt(unsigned long address)
|
|
|
|
{
|
2014-10-01 15:20:33 +02:00
|
|
|
return (void *)address;
|
2009-05-14 00:56:35 +02:00
|
|
|
}
|
|
|
|
#endif
|
2012-11-23 17:13:05 +01:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
2012-11-29 12:50:30 +01:00
|
|
|
#ifndef memset_io
|
2014-10-01 15:20:33 +02:00
|
|
|
#define memset_io memset_io
|
2017-06-30 19:09:32 +02:00
|
|
|
/**
|
|
|
|
* memset_io Set a range of I/O memory to a constant value
|
|
|
|
* @addr: The beginning of the I/O-memory range to set
|
|
|
|
* @val: The value to set the memory to
|
|
|
|
* @count: The number of bytes to set
|
|
|
|
*
|
|
|
|
* Set a range of I/O memory to a given value.
|
|
|
|
*/
|
2014-10-01 15:20:33 +02:00
|
|
|
static inline void memset_io(volatile void __iomem *addr, int value,
|
|
|
|
size_t size)
|
|
|
|
{
|
|
|
|
memset(__io_virt(addr), value, size);
|
|
|
|
}
|
2012-11-29 12:50:30 +01:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef memcpy_fromio
|
2014-10-01 15:20:33 +02:00
|
|
|
#define memcpy_fromio memcpy_fromio
|
2017-06-30 19:09:32 +02:00
|
|
|
/**
|
|
|
|
* memcpy_fromio Copy a block of data from I/O memory
|
|
|
|
* @dst: The (RAM) destination for the copy
|
|
|
|
* @src: The (I/O memory) source for the data
|
|
|
|
* @count: The number of bytes to copy
|
|
|
|
*
|
|
|
|
* Copy a block of data from I/O memory.
|
|
|
|
*/
|
2014-10-01 15:20:33 +02:00
|
|
|
static inline void memcpy_fromio(void *buffer,
|
|
|
|
const volatile void __iomem *addr,
|
|
|
|
size_t size)
|
|
|
|
{
|
|
|
|
memcpy(buffer, __io_virt(addr), size);
|
|
|
|
}
|
2012-11-29 12:50:30 +01:00
|
|
|
#endif
|
2014-10-01 15:20:33 +02:00
|
|
|
|
2012-11-29 12:50:30 +01:00
|
|
|
#ifndef memcpy_toio
|
2014-10-01 15:20:33 +02:00
|
|
|
#define memcpy_toio memcpy_toio
|
2017-06-30 19:09:32 +02:00
|
|
|
/**
|
|
|
|
* memcpy_toio Copy a block of data into I/O memory
|
|
|
|
* @dst: The (I/O memory) destination for the copy
|
|
|
|
* @src: The (RAM) source for the data
|
|
|
|
* @count: The number of bytes to copy
|
|
|
|
*
|
|
|
|
* Copy a block of data to I/O memory.
|
|
|
|
*/
|
2014-10-01 15:20:33 +02:00
|
|
|
static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer,
|
|
|
|
size_t size)
|
|
|
|
{
|
|
|
|
memcpy(__io_virt(addr), buffer, size);
|
|
|
|
}
|
2012-11-29 12:50:30 +01:00
|
|
|
#endif
|
2009-05-14 00:56:35 +02:00
|
|
|
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
|
|
|
|
#endif /* __ASM_GENERIC_IO_H */
|