2005-04-17 00:20:36 +02:00
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/*
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* arch/v850/kernel/rte_me2_cb.c -- Midas labs RTE-V850E/ME2-CB board
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <linux/fs.h>
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#include <linux/major.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <asm/atomic.h>
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#include <asm/page.h>
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#include <asm/me2.h>
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#include <asm/rte_me2_cb.h>
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#include <asm/machdep.h>
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#include <asm/v850e_intc.h>
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#include <asm/v850e_cache.h>
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#include <asm/irq.h>
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#include "mach.h"
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extern unsigned long *_intv_start;
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extern unsigned long *_intv_end;
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/* LED access routines. */
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extern unsigned read_leds (int pos, char *buf, int len);
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extern unsigned write_leds (int pos, const char *buf, int len);
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/* SDRAM are almost contiguous (with a small hole in between;
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see mach_reserve_bootmem for details), so just use both as one big area. */
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#define RAM_START SDRAM_ADDR
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#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)
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void __init mach_get_physical_ram (unsigned long *ram_start,
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unsigned long *ram_len)
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{
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*ram_start = RAM_START;
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*ram_len = RAM_END - RAM_START;
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}
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void mach_gettimeofday (struct timespec *tv)
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{
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tv->tv_sec = 0;
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tv->tv_nsec = 0;
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}
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/* Called before configuring an on-chip UART. */
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void rte_me2_cb_uart_pre_configure (unsigned chan,
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unsigned cflags, unsigned baud)
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{
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/* The RTE-V850E/ME2-CB connects some general-purpose I/O
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pins on the CPU to the RTS/CTS lines of UARTB channel 0's
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serial connection.
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I/O pins P21 and P22 are RTS and CTS respectively. */
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if (chan == 0) {
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/* Put P21 & P22 in I/O port mode. */
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ME2_PORT2_PMC &= ~0x6;
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/* Make P21 and output, and P22 an input. */
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ME2_PORT2_PM = (ME2_PORT2_PM & ~0xC) | 0x4;
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}
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me2_uart_pre_configure (chan, cflags, baud);
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}
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void __init mach_init_irqs (void)
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{
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/* Initialize interrupts. */
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me2_init_irqs ();
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rte_me2_cb_init_irqs ();
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}
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#ifdef CONFIG_ROM_KERNEL
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/* Initialization for kernel in ROM. */
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static inline rom_kernel_init (void)
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{
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/* If the kernel is in ROM, we have to copy any initialized data
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from ROM into RAM. */
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extern unsigned long _data_load_start, _sdata, _edata;
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register unsigned long *src = &_data_load_start;
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register unsigned long *dst = &_sdata, *end = &_edata;
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while (dst != end)
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*dst++ = *src++;
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}
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#endif /* CONFIG_ROM_KERNEL */
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static void install_interrupt_vectors (void)
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{
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unsigned long *p1, *p2;
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ME2_IRAMM = 0x03; /* V850E/ME2 iRAM write mode */
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/* vector copy to iRAM */
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p1 = (unsigned long *)0; /* v85x vector start */
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p2 = (unsigned long *)&_intv_start;
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while (p2 < (unsigned long *)&_intv_end)
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*p1++ = *p2++;
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ME2_IRAMM = 0x00; /* V850E/ME2 iRAM read mode */
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}
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/* CompactFlash */
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static void cf_power_on (void)
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{
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/* CF card detected? */
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if (CB_CF_STS0 & 0x0030)
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return;
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CB_CF_REG0 = 0x0002; /* reest on */
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mdelay (10);
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CB_CF_REG0 = 0x0003; /* power on */
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mdelay (10);
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CB_CF_REG0 = 0x0001; /* reset off */
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mdelay (10);
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}
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static void cf_power_off (void)
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{
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CB_CF_REG0 = 0x0003; /* power on */
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mdelay (10);
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CB_CF_REG0 = 0x0002; /* reest on */
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mdelay (10);
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}
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void __init mach_early_init (void)
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{
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install_interrupt_vectors ();
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/* CS1 SDRAM instruction cache enable */
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v850e_cache_enable (0x04, 0x03, 0);
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rte_cb_early_init ();
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/* CompactFlash power on */
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cf_power_on ();
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#if defined (CONFIG_ROM_KERNEL)
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rom_kernel_init ();
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#endif
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}
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/* RTE-V850E/ME2-CB Programmable Interrupt Controller. */
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static struct cb_pic_irq_init cb_pic_irq_inits[] = {
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{ "CB_EXTTM0", IRQ_CB_EXTTM0, 1, 1, 6 },
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{ "CB_EXTSIO", IRQ_CB_EXTSIO, 1, 1, 6 },
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{ "CB_TOVER", IRQ_CB_TOVER, 1, 1, 6 },
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{ "CB_GINT0", IRQ_CB_GINT0, 1, 1, 6 },
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{ "CB_USB", IRQ_CB_USB, 1, 1, 6 },
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{ "CB_LANC", IRQ_CB_LANC, 1, 1, 6 },
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{ "CB_USB_VBUS_ON", IRQ_CB_USB_VBUS_ON, 1, 1, 6 },
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{ "CB_USB_VBUS_OFF", IRQ_CB_USB_VBUS_OFF, 1, 1, 6 },
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{ "CB_EXTTM1", IRQ_CB_EXTTM1, 1, 1, 6 },
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{ "CB_EXTTM2", IRQ_CB_EXTTM2, 1, 1, 6 },
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{ 0 }
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};
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2007-02-10 10:44:30 +01:00
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#define NUM_CB_PIC_IRQ_INITS (ARRAY_SIZE(cb_pic_irq_inits) - 1)
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2005-04-17 00:20:36 +02:00
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static struct hw_interrupt_type cb_pic_hw_itypes[NUM_CB_PIC_IRQ_INITS];
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static unsigned char cb_pic_active_irqs = 0;
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void __init rte_me2_cb_init_irqs (void)
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{
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cb_pic_init_irq_types (cb_pic_irq_inits, cb_pic_hw_itypes);
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/* Initalize on board PIC1 (not PIC0) enable */
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CB_PIC_INT0M = 0x0000;
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CB_PIC_INT1M = 0x0000;
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CB_PIC_INTR = 0x0000;
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CB_PIC_INTEN |= CB_PIC_INT1EN;
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ME2_PORT2_PMC |= 0x08; /* INTP23/SCK1 mode */
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ME2_PORT2_PFC &= ~0x08; /* INTP23 mode */
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ME2_INTR(2) &= ~0x08; /* INTP23 falling-edge detect */
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ME2_INTF(2) &= ~0x08; /* " */
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rte_cb_init_irqs (); /* gbus &c */
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}
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/* Enable interrupt handling for interrupt IRQ. */
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void cb_pic_enable_irq (unsigned irq)
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{
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CB_PIC_INT1M |= 1 << (irq - CB_PIC_BASE_IRQ);
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}
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void cb_pic_disable_irq (unsigned irq)
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{
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CB_PIC_INT1M &= ~(1 << (irq - CB_PIC_BASE_IRQ));
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}
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void cb_pic_shutdown_irq (unsigned irq)
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{
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cb_pic_disable_irq (irq);
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if (--cb_pic_active_irqs == 0)
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free_irq (IRQ_CB_PIC, 0);
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CB_PIC_INT1M &= ~(1 << (irq - CB_PIC_BASE_IRQ));
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}
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static irqreturn_t cb_pic_handle_irq (int irq, void *dev_id,
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struct pt_regs *regs)
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{
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irqreturn_t rval = IRQ_NONE;
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unsigned status = CB_PIC_INTR;
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unsigned enable = CB_PIC_INT1M;
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/* Only pay attention to enabled interrupts. */
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status &= enable;
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CB_PIC_INTEN &= ~CB_PIC_INT1EN;
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if (status) {
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unsigned mask = 1;
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irq = CB_PIC_BASE_IRQ;
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do {
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/* There's an active interrupt, find out which one,
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and call its handler. */
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while (! (status & mask)) {
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irq++;
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mask <<= 1;
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}
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status &= ~mask;
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CB_PIC_INTR = mask;
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/* Recursively call handle_irq to handle it. */
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handle_irq (irq, regs);
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rval = IRQ_HANDLED;
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} while (status);
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}
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CB_PIC_INTEN |= CB_PIC_INT1EN;
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return rval;
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}
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static void irq_nop (unsigned irq) { }
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static unsigned cb_pic_startup_irq (unsigned irq)
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{
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int rval;
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if (cb_pic_active_irqs == 0) {
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rval = request_irq (IRQ_CB_PIC, cb_pic_handle_irq,
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2006-07-02 04:29:28 +02:00
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IRQF_DISABLED, "cb_pic_handler", 0);
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2005-04-17 00:20:36 +02:00
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if (rval != 0)
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return rval;
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}
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cb_pic_active_irqs++;
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cb_pic_enable_irq (irq);
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return 0;
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}
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/* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
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INITS (which is terminated by an entry with the name field == 0). */
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void __init cb_pic_init_irq_types (struct cb_pic_irq_init *inits,
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struct hw_interrupt_type *hw_irq_types)
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{
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struct cb_pic_irq_init *init;
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for (init = inits; init->name; init++) {
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struct hw_interrupt_type *hwit = hw_irq_types++;
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hwit->typename = init->name;
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hwit->startup = cb_pic_startup_irq;
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hwit->shutdown = cb_pic_shutdown_irq;
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hwit->enable = cb_pic_enable_irq;
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hwit->disable = cb_pic_disable_irq;
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hwit->ack = irq_nop;
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hwit->end = irq_nop;
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/* Initialize kernel IRQ infrastructure for this interrupt. */
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init_irq_handlers(init->base, init->num, init->interval, hwit);
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}
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}
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