2005-04-17 00:20:36 +02:00
|
|
|
/*
|
2008-07-11 12:18:41 +02:00
|
|
|
* numaq_32.c - Low-level PCI access for NUMA-Q machines
|
2005-04-17 00:20:36 +02:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/pci.h>
|
|
|
|
#include <linux/init.h>
|
|
|
|
#include <linux/nodemask.h>
|
2009-02-17 13:58:15 +01:00
|
|
|
#include <asm/apic.h>
|
2008-06-09 03:31:54 +02:00
|
|
|
#include <asm/mpspec.h>
|
2008-12-27 14:02:28 +01:00
|
|
|
#include <asm/pci_x86.h>
|
2010-02-05 15:37:03 +01:00
|
|
|
#include <asm/numaq.h>
|
2008-02-04 16:48:03 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
#define BUS2QUAD(global) (mp_bus_id_to_node[global])
|
2008-03-11 20:55:42 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
|
2008-03-11 17:45:48 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
|
|
|
|
|
|
|
|
#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
|
|
|
|
(0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
|
|
|
|
|
2008-02-04 16:48:03 +01:00
|
|
|
static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
|
|
|
|
{
|
|
|
|
unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
|
|
|
|
if (xquad_portio)
|
|
|
|
writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
|
|
|
|
else
|
|
|
|
outl(val, 0xCF8);
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
|
|
|
|
unsigned int devfn, int reg, int len, u32 *value)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
2008-02-04 16:48:03 +01:00
|
|
|
void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
|
2005-04-17 00:20:36 +02:00
|
|
|
|
x86/PCI: config space accessor functions should not ignore the segment argument
Without this change, the majority of the raw PCI config space access
functions silently ignore a non-zero segment argument, which is
certainly wrong.
Apart from pci_direct_conf1, all other non-MMCFG access methods get
used only for non-extended accesses (i.e. assigned to raw_pci_ops
only). Consequently, with the way raw_pci_{read,write}() work, it would
be a coding error to call these functions with a non-zero segment (with
the current call flow this cannot happen afaict).
The access method 1 accessor, as it can be used for extended accesses
(on AMD systems) instead gets checks added for the passed in segment to
be zero. This would be the case when on such a system having multiple
PCI segments (don't know whether any exist in practice) MMCFG for some
reason is not usable, and method 1 gets selected for doing extended
accesses. Rather than accessing the wrong device's config space, the
function will now error out.
v2: Convert BUG_ON() to WARN_ON(), and extend description as per Ingo's
request.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Reviewed-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-22 09:13:05 +02:00
|
|
|
WARN_ON(seg);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2010-02-17 15:35:25 +01:00
|
|
|
raw_spin_lock_irqsave(&pci_config_lock, flags);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-02-04 16:48:03 +01:00
|
|
|
write_cf8(bus, devfn, reg);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
switch (len) {
|
|
|
|
case 1:
|
2008-02-04 16:48:03 +01:00
|
|
|
if (xquad_portio)
|
|
|
|
*value = readb(adr + (reg & 3));
|
|
|
|
else
|
|
|
|
*value = inb(0xCFC + (reg & 3));
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-04 16:48:03 +01:00
|
|
|
if (xquad_portio)
|
|
|
|
*value = readw(adr + (reg & 2));
|
|
|
|
else
|
|
|
|
*value = inw(0xCFC + (reg & 2));
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-04 16:48:03 +01:00
|
|
|
if (xquad_portio)
|
|
|
|
*value = readl(adr);
|
|
|
|
else
|
|
|
|
*value = inl(0xCFC);
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-02-17 15:35:25 +01:00
|
|
|
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
|
|
|
|
unsigned int devfn, int reg, int len, u32 value)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
2008-02-04 16:48:03 +01:00
|
|
|
void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
|
2005-04-17 00:20:36 +02:00
|
|
|
|
x86/PCI: config space accessor functions should not ignore the segment argument
Without this change, the majority of the raw PCI config space access
functions silently ignore a non-zero segment argument, which is
certainly wrong.
Apart from pci_direct_conf1, all other non-MMCFG access methods get
used only for non-extended accesses (i.e. assigned to raw_pci_ops
only). Consequently, with the way raw_pci_{read,write}() work, it would
be a coding error to call these functions with a non-zero segment (with
the current call flow this cannot happen afaict).
The access method 1 accessor, as it can be used for extended accesses
(on AMD systems) instead gets checks added for the passed in segment to
be zero. This would be the case when on such a system having multiple
PCI segments (don't know whether any exist in practice) MMCFG for some
reason is not usable, and method 1 gets selected for doing extended
accesses. Rather than accessing the wrong device's config space, the
function will now error out.
v2: Convert BUG_ON() to WARN_ON(), and extend description as per Ingo's
request.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Reviewed-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-22 09:13:05 +02:00
|
|
|
WARN_ON(seg);
|
2005-04-17 00:20:36 +02:00
|
|
|
if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2010-02-17 15:35:25 +01:00
|
|
|
raw_spin_lock_irqsave(&pci_config_lock, flags);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-02-04 16:48:03 +01:00
|
|
|
write_cf8(bus, devfn, reg);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
switch (len) {
|
|
|
|
case 1:
|
2008-02-04 16:48:03 +01:00
|
|
|
if (xquad_portio)
|
|
|
|
writeb(value, adr + (reg & 3));
|
|
|
|
else
|
|
|
|
outb((u8)value, 0xCFC + (reg & 3));
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-04 16:48:03 +01:00
|
|
|
if (xquad_portio)
|
|
|
|
writew(value, adr + (reg & 2));
|
|
|
|
else
|
|
|
|
outw((u16)value, 0xCFC + (reg & 2));
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-04 16:48:03 +01:00
|
|
|
if (xquad_portio)
|
|
|
|
writel(value, adr + reg);
|
|
|
|
else
|
|
|
|
outl((u32)value, 0xCFC);
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-02-17 15:35:25 +01:00
|
|
|
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#undef PCI_CONF1_MQ_ADDRESS
|
|
|
|
|
2011-09-15 09:58:51 +02:00
|
|
|
static const struct pci_raw_ops pci_direct_conf1_mq = {
|
2005-04-17 00:20:36 +02:00
|
|
|
.read = pci_conf1_mq_read,
|
|
|
|
.write = pci_conf1_mq_write
|
|
|
|
};
|
|
|
|
|
|
|
|
|
2012-12-21 23:02:53 +01:00
|
|
|
static void pci_fixup_i450nx(struct pci_dev *d)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* i450NX -- Find and scan all secondary buses on all PXB's.
|
|
|
|
*/
|
|
|
|
int pxb, reg;
|
|
|
|
u8 busno, suba, subb;
|
|
|
|
int quad = BUS2QUAD(d->bus->number);
|
|
|
|
|
2008-07-24 01:00:13 +02:00
|
|
|
dev_info(&d->dev, "searching for i450NX host bridges\n");
|
2005-04-17 00:20:36 +02:00
|
|
|
reg = 0xd0;
|
|
|
|
for(pxb=0; pxb<2; pxb++) {
|
|
|
|
pci_read_config_byte(d, reg++, &busno);
|
|
|
|
pci_read_config_byte(d, reg++, &suba);
|
|
|
|
pci_read_config_byte(d, reg++, &subb);
|
2008-07-24 01:00:13 +02:00
|
|
|
dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
|
|
|
|
pxb, busno, suba, subb);
|
2007-08-10 22:01:19 +02:00
|
|
|
if (busno) {
|
|
|
|
/* Bus A */
|
|
|
|
pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
|
|
|
|
}
|
|
|
|
if (suba < subb) {
|
|
|
|
/* Bus B */
|
|
|
|
pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
pcibios_last_bus = -1;
|
|
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
|
|
|
|
|
2008-07-11 12:18:41 +02:00
|
|
|
int __init pci_numaq_init(void)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
int quad;
|
|
|
|
|
|
|
|
raw_pci_ops = &pci_direct_conf1_mq;
|
|
|
|
|
2013-01-03 23:28:34 +01:00
|
|
|
pcibios_scan_root(0);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (num_online_nodes() > 1)
|
|
|
|
for_each_online_node(quad) {
|
|
|
|
if (quad == 0)
|
|
|
|
continue;
|
|
|
|
printk("Scanning PCI bus %d for quad %d\n",
|
|
|
|
QUADLOCAL2BUS(quad,0), quad);
|
2007-08-10 22:01:19 +02:00
|
|
|
pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|