2005-04-17 00:20:36 +02:00
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/*
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* ALSA modem driver for Intel ICH (i8x0) chipsets
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*
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* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
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*
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* This is modified (by Sasha Khapyorsky <sashak@smlink.com>) version
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* of ALSA ICH sound driver intel8x0.c .
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <sound/driver.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/moduleparam.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/ac97_codec.h>
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#include <sound/info.h>
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#include <sound/initval.h>
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MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
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MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7013; NVidia MCP/2/2S/3 modems");
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MODULE_LICENSE("GPL");
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MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
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"{Intel,82901AB-ICH0},"
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"{Intel,82801BA-ICH2},"
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"{Intel,82801CA-ICH3},"
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"{Intel,82801DB-ICH4},"
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"{Intel,ICH5},"
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"{Intel,ICH6},"
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"{Intel,ICH7},"
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"{Intel,MX440},"
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"{SiS,7013},"
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"{NVidia,NForce Modem},"
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"{NVidia,NForce2 Modem},"
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"{NVidia,NForce2s Modem},"
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"{NVidia,NForce3 Modem},"
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"{AMD,AMD768}}");
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2005-10-04 08:46:51 +02:00
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static int index = -2; /* Exclude the first card */
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static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
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static int ac97_clock = 0;
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2005-04-17 00:20:36 +02:00
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2005-10-04 08:46:51 +02:00
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module_param(index, int, 0444);
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2005-04-17 00:20:36 +02:00
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MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
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2005-10-04 08:46:51 +02:00
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module_param(id, charp, 0444);
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2005-04-17 00:20:36 +02:00
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MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
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2005-10-04 08:46:51 +02:00
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module_param(ac97_clock, int, 0444);
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2005-04-17 00:20:36 +02:00
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MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
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/*
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* Direct registers
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*/
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enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
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#define ICHREG(x) ICH_REG_##x
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#define DEFINE_REGSET(name,base) \
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enum { \
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ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
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ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
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ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
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ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
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ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
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ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
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ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
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};
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/* busmaster blocks */
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DEFINE_REGSET(OFF, 0); /* offset */
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/* values for each busmaster block */
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/* LVI */
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#define ICH_REG_LVI_MASK 0x1f
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/* SR */
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#define ICH_FIFOE 0x10 /* FIFO error */
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#define ICH_BCIS 0x08 /* buffer completion interrupt status */
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#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
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#define ICH_CELV 0x02 /* current equals last valid */
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#define ICH_DCH 0x01 /* DMA controller halted */
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/* PIV */
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#define ICH_REG_PIV_MASK 0x1f /* mask */
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/* CR */
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#define ICH_IOCE 0x10 /* interrupt on completion enable */
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#define ICH_FEIE 0x08 /* fifo error interrupt enable */
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#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
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#define ICH_RESETREGS 0x02 /* reset busmaster registers */
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#define ICH_STARTBM 0x01 /* start busmaster operation */
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/* global block */
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#define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
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#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
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#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
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#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
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#define ICH_ACLINK 0x00000008 /* AClink shut off */
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#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
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#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
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#define ICH_GIE 0x00000001 /* GPI interrupt enable */
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#define ICH_REG_GLOB_STA 0x40 /* dword - global status */
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#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
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#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
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#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
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#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
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#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
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#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
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#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
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#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
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#define ICH_MD3 0x00020000 /* modem power down semaphore */
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#define ICH_AD3 0x00010000 /* audio power down semaphore */
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#define ICH_RCS 0x00008000 /* read completion status */
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#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
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#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
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#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
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#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
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#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
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#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
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#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
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#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
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#define ICH_POINT 0x00000040 /* playback interrupt */
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#define ICH_PIINT 0x00000020 /* capture interrupt */
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#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
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#define ICH_MOINT 0x00000004 /* modem playback interrupt */
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#define ICH_MIINT 0x00000002 /* modem capture interrupt */
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#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
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#define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
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#define ICH_CAS 0x01 /* codec access semaphore */
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#define ICH_MAX_FRAGS 32 /* max hw frags */
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/*
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*
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*/
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enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
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enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
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#define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
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typedef struct {
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unsigned int ichd; /* ich device number */
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unsigned long reg_offset; /* offset to bmaddr */
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u32 *bdbar; /* CPU address (32bit) */
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unsigned int bdbar_addr; /* PCI bus address (32bit) */
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snd_pcm_substream_t *substream;
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unsigned int physbuf; /* physical address (32bit) */
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unsigned int size;
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unsigned int fragsize;
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unsigned int fragsize1;
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unsigned int position;
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int frags;
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int lvi;
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int lvi_frag;
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int civ;
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int ack;
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int ack_reload;
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unsigned int ack_bit;
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unsigned int roff_sr;
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unsigned int roff_picb;
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unsigned int int_sta_mask; /* interrupt status mask */
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unsigned int ali_slot; /* ALI DMA slot */
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ac97_t *ac97;
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} ichdev_t;
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typedef struct _snd_intel8x0m intel8x0_t;
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struct _snd_intel8x0m {
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unsigned int device_type;
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int irq;
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unsigned int mmio;
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unsigned long addr;
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void __iomem *remap_addr;
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unsigned int bm_mmio;
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unsigned long bmaddr;
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void __iomem *remap_bmaddr;
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struct pci_dev *pci;
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snd_card_t *card;
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int pcm_devs;
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snd_pcm_t *pcm[2];
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ichdev_t ichd[2];
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unsigned int in_ac97_init: 1;
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ac97_bus_t *ac97_bus;
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ac97_t *ac97;
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spinlock_t reg_lock;
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struct snd_dma_buffer bdbars;
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u32 bdbars_count;
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u32 int_sta_reg; /* interrupt status register */
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u32 int_sta_mask; /* interrupt status mask */
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unsigned int pcm_pos_shift;
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};
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static struct pci_device_id snd_intel8x0m_ids[] = {
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{ 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
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{ 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
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{ 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
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{ 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
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{ 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */
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{ 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */
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{ 0x8086, 0x266d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH6 */
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{ 0x8086, 0x27dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH7 */
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{ 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
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{ 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
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{ 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7013 */
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{ 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
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{ 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
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{ 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */
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{ 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
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#if 0
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{ 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
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{ 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
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#endif
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
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/*
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* Lowlevel I/O - busmaster
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*/
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static u8 igetbyte(intel8x0_t *chip, u32 offset)
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{
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if (chip->bm_mmio)
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return readb(chip->remap_bmaddr + offset);
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else
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return inb(chip->bmaddr + offset);
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}
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static u16 igetword(intel8x0_t *chip, u32 offset)
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{
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if (chip->bm_mmio)
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return readw(chip->remap_bmaddr + offset);
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else
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return inw(chip->bmaddr + offset);
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}
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static u32 igetdword(intel8x0_t *chip, u32 offset)
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{
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if (chip->bm_mmio)
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return readl(chip->remap_bmaddr + offset);
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else
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return inl(chip->bmaddr + offset);
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}
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static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
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{
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if (chip->bm_mmio)
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writeb(val, chip->remap_bmaddr + offset);
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else
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outb(val, chip->bmaddr + offset);
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}
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static void iputword(intel8x0_t *chip, u32 offset, u16 val)
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{
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if (chip->bm_mmio)
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writew(val, chip->remap_bmaddr + offset);
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else
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outw(val, chip->bmaddr + offset);
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}
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static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
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{
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if (chip->bm_mmio)
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writel(val, chip->remap_bmaddr + offset);
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else
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outl(val, chip->bmaddr + offset);
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}
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/*
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* Lowlevel I/O - AC'97 registers
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*/
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static u16 iagetword(intel8x0_t *chip, u32 offset)
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{
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if (chip->mmio)
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return readw(chip->remap_addr + offset);
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else
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return inw(chip->addr + offset);
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}
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static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
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{
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if (chip->mmio)
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writew(val, chip->remap_addr + offset);
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else
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outw(val, chip->addr + offset);
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|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Basic I/O
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* access to AC97 codec via normal i/o (for ICH and SIS7013)
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* return the GLOB_STA bit for the corresponding codec */
|
|
|
|
static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
|
|
|
|
{
|
|
|
|
static unsigned int codec_bit[3] = {
|
|
|
|
ICH_PCR, ICH_SCR, ICH_TCR
|
|
|
|
};
|
|
|
|
snd_assert(codec < 3, return ICH_PCR);
|
|
|
|
return codec_bit[codec];
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0m_codec_semaphore(intel8x0_t *chip, unsigned int codec)
|
|
|
|
{
|
|
|
|
int time;
|
|
|
|
|
|
|
|
if (codec > 1)
|
|
|
|
return -EIO;
|
|
|
|
codec = get_ich_codec_bit(chip, codec);
|
|
|
|
|
|
|
|
/* codec ready ? */
|
|
|
|
if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
/* Anyone holding a semaphore for 1 msec should be shot... */
|
|
|
|
time = 100;
|
|
|
|
do {
|
|
|
|
if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
|
|
|
|
return 0;
|
|
|
|
udelay(10);
|
|
|
|
} while (time--);
|
|
|
|
|
|
|
|
/* access to some forbidden (non existant) ac97 registers will not
|
|
|
|
* reset the semaphore. So even if you don't get the semaphore, still
|
|
|
|
* continue the access. We don't need the semaphore anyway. */
|
|
|
|
snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
|
|
|
|
igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
|
|
|
|
iagetword(chip, 0); /* clear semaphore flag */
|
|
|
|
/* I don't care about the semaphore */
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void snd_intel8x0_codec_write(ac97_t *ac97,
|
|
|
|
unsigned short reg,
|
|
|
|
unsigned short val)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = ac97->private_data;
|
|
|
|
|
|
|
|
if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
|
|
|
|
if (! chip->in_ac97_init)
|
|
|
|
snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
|
|
|
|
}
|
|
|
|
iaputword(chip, reg + ac97->num * 0x80, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
|
|
|
|
unsigned short reg)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = ac97->private_data;
|
|
|
|
unsigned short res;
|
|
|
|
unsigned int tmp;
|
|
|
|
|
|
|
|
if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
|
|
|
|
if (! chip->in_ac97_init)
|
|
|
|
snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
|
|
|
|
res = 0xffff;
|
|
|
|
} else {
|
|
|
|
res = iagetword(chip, reg + ac97->num * 0x80);
|
|
|
|
if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
|
|
|
|
/* reset RCS and preserve other R/WC bits */
|
|
|
|
iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
|
|
|
|
if (! chip->in_ac97_init)
|
|
|
|
snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
|
|
|
|
res = 0xffff;
|
|
|
|
}
|
|
|
|
}
|
2005-04-07 20:21:21 +02:00
|
|
|
if (reg == AC97_GPIO_STATUS)
|
|
|
|
iagetword(chip, 0); /* clear semaphore */
|
2005-04-17 00:20:36 +02:00
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DMA I/O
|
|
|
|
*/
|
|
|
|
static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
|
|
|
|
{
|
|
|
|
int idx;
|
|
|
|
u32 *bdbar = ichdev->bdbar;
|
|
|
|
unsigned long port = ichdev->reg_offset;
|
|
|
|
|
|
|
|
iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
|
|
|
|
if (ichdev->size == ichdev->fragsize) {
|
|
|
|
ichdev->ack_reload = ichdev->ack = 2;
|
|
|
|
ichdev->fragsize1 = ichdev->fragsize >> 1;
|
|
|
|
for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
|
|
|
|
bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
|
|
|
|
bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
|
|
|
|
ichdev->fragsize1 >> chip->pcm_pos_shift);
|
|
|
|
bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
|
|
|
|
bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
|
|
|
|
ichdev->fragsize1 >> chip->pcm_pos_shift);
|
|
|
|
}
|
|
|
|
ichdev->frags = 2;
|
|
|
|
} else {
|
|
|
|
ichdev->ack_reload = ichdev->ack = 1;
|
|
|
|
ichdev->fragsize1 = ichdev->fragsize;
|
|
|
|
for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
|
|
|
|
bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
|
|
|
|
bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
|
|
|
|
ichdev->fragsize >> chip->pcm_pos_shift);
|
|
|
|
// printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
|
|
|
|
}
|
|
|
|
ichdev->frags = ichdev->size / ichdev->fragsize;
|
|
|
|
}
|
|
|
|
iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
|
|
|
|
ichdev->civ = 0;
|
|
|
|
iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
|
|
|
|
ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
|
|
|
|
ichdev->position = 0;
|
|
|
|
#if 0
|
|
|
|
printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
|
|
|
|
ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
|
|
|
|
#endif
|
|
|
|
/* clear interrupts */
|
|
|
|
iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Interrupt handler
|
|
|
|
*/
|
|
|
|
|
|
|
|
static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
|
|
|
|
{
|
|
|
|
unsigned long port = ichdev->reg_offset;
|
|
|
|
int civ, i, step;
|
|
|
|
int ack = 0;
|
|
|
|
|
|
|
|
civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
|
|
|
|
if (civ == ichdev->civ) {
|
|
|
|
// snd_printd("civ same %d\n", civ);
|
|
|
|
step = 1;
|
|
|
|
ichdev->civ++;
|
|
|
|
ichdev->civ &= ICH_REG_LVI_MASK;
|
|
|
|
} else {
|
|
|
|
step = civ - ichdev->civ;
|
|
|
|
if (step < 0)
|
|
|
|
step += ICH_REG_LVI_MASK + 1;
|
|
|
|
// if (step != 1)
|
|
|
|
// snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
|
|
|
|
ichdev->civ = civ;
|
|
|
|
}
|
|
|
|
|
|
|
|
ichdev->position += step * ichdev->fragsize1;
|
|
|
|
ichdev->position %= ichdev->size;
|
|
|
|
ichdev->lvi += step;
|
|
|
|
ichdev->lvi &= ICH_REG_LVI_MASK;
|
|
|
|
iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
|
|
|
|
for (i = 0; i < step; i++) {
|
|
|
|
ichdev->lvi_frag++;
|
|
|
|
ichdev->lvi_frag %= ichdev->frags;
|
|
|
|
ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
|
|
|
|
// printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
|
|
|
|
if (--ichdev->ack == 0) {
|
|
|
|
ichdev->ack = ichdev->ack_reload;
|
|
|
|
ack = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (ack && ichdev->substream) {
|
|
|
|
spin_unlock(&chip->reg_lock);
|
|
|
|
snd_pcm_period_elapsed(ichdev->substream);
|
|
|
|
spin_lock(&chip->reg_lock);
|
|
|
|
}
|
|
|
|
iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = dev_id;
|
|
|
|
ichdev_t *ichdev;
|
|
|
|
unsigned int status;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
spin_lock(&chip->reg_lock);
|
|
|
|
status = igetdword(chip, chip->int_sta_reg);
|
|
|
|
if (status == 0xffffffff) { /* we are not yet resumed */
|
|
|
|
spin_unlock(&chip->reg_lock);
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
if ((status & chip->int_sta_mask) == 0) {
|
|
|
|
if (status)
|
|
|
|
iputdword(chip, chip->int_sta_reg, status);
|
|
|
|
spin_unlock(&chip->reg_lock);
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < chip->bdbars_count; i++) {
|
|
|
|
ichdev = &chip->ichd[i];
|
|
|
|
if (status & ichdev->int_sta_mask)
|
|
|
|
snd_intel8x0_update(chip, ichdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ack them */
|
|
|
|
iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
|
|
|
|
spin_unlock(&chip->reg_lock);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PCM part
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = snd_pcm_substream_chip(substream);
|
|
|
|
ichdev_t *ichdev = get_ichdev(substream);
|
|
|
|
unsigned char val = 0;
|
|
|
|
unsigned long port = ichdev->reg_offset;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
|
|
val = ICH_IOCE | ICH_STARTBM;
|
|
|
|
break;
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
|
|
val = ICH_IOCE;
|
|
|
|
break;
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
|
|
val = ICH_IOCE | ICH_STARTBM;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
iputbyte(chip, port + ICH_REG_OFF_CR, val);
|
|
|
|
if (cmd == SNDRV_PCM_TRIGGER_STOP) {
|
|
|
|
/* wait until DMA stopped */
|
|
|
|
while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
|
|
|
|
/* reset whole DMA things */
|
|
|
|
iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
|
|
|
|
snd_pcm_hw_params_t * hw_params)
|
|
|
|
{
|
|
|
|
return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
|
|
|
|
{
|
|
|
|
return snd_pcm_lib_free_pages(substream);
|
|
|
|
}
|
|
|
|
|
|
|
|
static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = snd_pcm_substream_chip(substream);
|
|
|
|
ichdev_t *ichdev = get_ichdev(substream);
|
|
|
|
size_t ptr1, ptr;
|
|
|
|
|
|
|
|
ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
|
|
|
|
if (ptr1 != 0)
|
|
|
|
ptr = ichdev->fragsize1 - ptr1;
|
|
|
|
else
|
|
|
|
ptr = 0;
|
|
|
|
ptr += ichdev->position;
|
|
|
|
if (ptr >= ichdev->size)
|
|
|
|
return 0;
|
|
|
|
return bytes_to_frames(substream->runtime, ptr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t * substream)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = snd_pcm_substream_chip(substream);
|
|
|
|
snd_pcm_runtime_t *runtime = substream->runtime;
|
|
|
|
ichdev_t *ichdev = get_ichdev(substream);
|
|
|
|
|
|
|
|
ichdev->physbuf = runtime->dma_addr;
|
|
|
|
ichdev->size = snd_pcm_lib_buffer_bytes(substream);
|
|
|
|
ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
|
|
|
|
snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
|
|
|
|
snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
|
|
|
|
snd_intel8x0_setup_periods(chip, ichdev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static snd_pcm_hardware_t snd_intel8x0m_stream =
|
|
|
|
{
|
|
|
|
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
|
|
|
|
SNDRV_PCM_INFO_BLOCK_TRANSFER |
|
|
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
|
|
|
SNDRV_PCM_INFO_PAUSE |
|
|
|
|
SNDRV_PCM_INFO_RESUME),
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
|
|
|
|
.rate_min = 8000,
|
|
|
|
.rate_max = 16000,
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 1,
|
|
|
|
.buffer_bytes_max = 64 * 1024,
|
|
|
|
.period_bytes_min = 32,
|
|
|
|
.period_bytes_max = 64 * 1024,
|
|
|
|
.periods_min = 1,
|
|
|
|
.periods_max = 1024,
|
|
|
|
.fifo_size = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static int snd_intel8x0m_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
|
|
|
|
{
|
|
|
|
static unsigned int rates[] = { 8000, 9600, 12000, 16000 };
|
|
|
|
static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
|
|
|
|
.count = ARRAY_SIZE(rates),
|
|
|
|
.list = rates,
|
|
|
|
.mask = 0,
|
|
|
|
};
|
|
|
|
snd_pcm_runtime_t *runtime = substream->runtime;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
ichdev->substream = substream;
|
|
|
|
runtime->hw = snd_intel8x0m_stream;
|
|
|
|
err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
|
|
|
|
if ( err < 0 )
|
|
|
|
return err;
|
|
|
|
runtime->private_data = ichdev;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0m_playback_open(snd_pcm_substream_t * substream)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = snd_pcm_substream_chip(substream);
|
|
|
|
|
|
|
|
return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0m_playback_close(snd_pcm_substream_t * substream)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = snd_pcm_substream_chip(substream);
|
|
|
|
|
|
|
|
chip->ichd[ICHD_MDMOUT].substream = NULL;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0m_capture_open(snd_pcm_substream_t * substream)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = snd_pcm_substream_chip(substream);
|
|
|
|
|
|
|
|
return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0m_capture_close(snd_pcm_substream_t * substream)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = snd_pcm_substream_chip(substream);
|
|
|
|
|
|
|
|
chip->ichd[ICHD_MDMIN].substream = NULL;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static snd_pcm_ops_t snd_intel8x0m_playback_ops = {
|
|
|
|
.open = snd_intel8x0m_playback_open,
|
|
|
|
.close = snd_intel8x0m_playback_close,
|
|
|
|
.ioctl = snd_pcm_lib_ioctl,
|
|
|
|
.hw_params = snd_intel8x0_hw_params,
|
|
|
|
.hw_free = snd_intel8x0_hw_free,
|
|
|
|
.prepare = snd_intel8x0m_pcm_prepare,
|
2005-05-29 15:10:07 +02:00
|
|
|
.trigger = snd_intel8x0_pcm_trigger,
|
2005-04-17 00:20:36 +02:00
|
|
|
.pointer = snd_intel8x0_pcm_pointer,
|
|
|
|
};
|
|
|
|
|
|
|
|
static snd_pcm_ops_t snd_intel8x0m_capture_ops = {
|
|
|
|
.open = snd_intel8x0m_capture_open,
|
|
|
|
.close = snd_intel8x0m_capture_close,
|
|
|
|
.ioctl = snd_pcm_lib_ioctl,
|
|
|
|
.hw_params = snd_intel8x0_hw_params,
|
|
|
|
.hw_free = snd_intel8x0_hw_free,
|
|
|
|
.prepare = snd_intel8x0m_pcm_prepare,
|
2005-05-29 15:10:07 +02:00
|
|
|
.trigger = snd_intel8x0_pcm_trigger,
|
2005-04-17 00:20:36 +02:00
|
|
|
.pointer = snd_intel8x0_pcm_pointer,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
struct ich_pcm_table {
|
|
|
|
char *suffix;
|
|
|
|
snd_pcm_ops_t *playback_ops;
|
|
|
|
snd_pcm_ops_t *capture_ops;
|
|
|
|
size_t prealloc_size;
|
|
|
|
size_t prealloc_max_size;
|
|
|
|
int ac97_idx;
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
|
|
|
|
{
|
|
|
|
snd_pcm_t *pcm;
|
|
|
|
int err;
|
|
|
|
char name[32];
|
|
|
|
|
|
|
|
if (rec->suffix)
|
|
|
|
sprintf(name, "Intel ICH - %s", rec->suffix);
|
|
|
|
else
|
|
|
|
strcpy(name, "Intel ICH");
|
|
|
|
err = snd_pcm_new(chip->card, name, device,
|
|
|
|
rec->playback_ops ? 1 : 0,
|
|
|
|
rec->capture_ops ? 1 : 0, &pcm);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
if (rec->playback_ops)
|
|
|
|
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
|
|
|
|
if (rec->capture_ops)
|
|
|
|
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
|
|
|
|
|
|
|
|
pcm->private_data = chip;
|
|
|
|
pcm->info_flags = 0;
|
2005-09-29 11:48:17 +02:00
|
|
|
pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
|
2005-04-17 00:20:36 +02:00
|
|
|
if (rec->suffix)
|
|
|
|
sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
|
|
|
|
else
|
|
|
|
strcpy(pcm->name, chip->card->shortname);
|
|
|
|
chip->pcm[device] = pcm;
|
|
|
|
|
|
|
|
snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
|
|
|
|
snd_dma_pci_data(chip->pci),
|
|
|
|
rec->prealloc_size,
|
|
|
|
rec->prealloc_max_size);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ich_pcm_table intel_pcms[] __devinitdata = {
|
|
|
|
{
|
|
|
|
.suffix = "Modem",
|
|
|
|
.playback_ops = &snd_intel8x0m_playback_ops,
|
|
|
|
.capture_ops = &snd_intel8x0m_capture_ops,
|
|
|
|
.prealloc_size = 32 * 1024,
|
|
|
|
.prealloc_max_size = 64 * 1024,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
|
|
|
|
{
|
|
|
|
int i, tblsize, device, err;
|
|
|
|
struct ich_pcm_table *tbl, *rec;
|
|
|
|
|
|
|
|
#if 1
|
|
|
|
tbl = intel_pcms;
|
|
|
|
tblsize = 1;
|
|
|
|
#else
|
|
|
|
switch (chip->device_type) {
|
|
|
|
case DEVICE_NFORCE:
|
|
|
|
tbl = nforce_pcms;
|
|
|
|
tblsize = ARRAY_SIZE(nforce_pcms);
|
|
|
|
break;
|
|
|
|
case DEVICE_ALI:
|
|
|
|
tbl = ali_pcms;
|
|
|
|
tblsize = ARRAY_SIZE(ali_pcms);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
tbl = intel_pcms;
|
|
|
|
tblsize = 2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
device = 0;
|
|
|
|
for (i = 0; i < tblsize; i++) {
|
|
|
|
rec = tbl + i;
|
|
|
|
if (i > 0 && rec->ac97_idx) {
|
|
|
|
/* activate PCM only when associated AC'97 codec */
|
|
|
|
if (! chip->ichd[rec->ac97_idx].ac97)
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
err = snd_intel8x0_pcm1(chip, device, rec);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
device++;
|
|
|
|
}
|
|
|
|
|
|
|
|
chip->pcm_devs = device;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Mixer part
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = bus->private_data;
|
|
|
|
chip->ac97_bus = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = ac97->private_data;
|
|
|
|
chip->ac97 = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock)
|
|
|
|
{
|
|
|
|
ac97_bus_t *pbus;
|
|
|
|
ac97_template_t ac97;
|
|
|
|
ac97_t *x97;
|
|
|
|
int err;
|
|
|
|
unsigned int glob_sta = 0;
|
|
|
|
static ac97_bus_ops_t ops = {
|
|
|
|
.write = snd_intel8x0_codec_write,
|
|
|
|
.read = snd_intel8x0_codec_read,
|
|
|
|
};
|
|
|
|
|
|
|
|
chip->in_ac97_init = 1;
|
|
|
|
|
|
|
|
memset(&ac97, 0, sizeof(ac97));
|
|
|
|
ac97.private_data = chip;
|
|
|
|
ac97.private_free = snd_intel8x0_mixer_free_ac97;
|
|
|
|
ac97.scaps = AC97_SCAP_SKIP_AUDIO;
|
|
|
|
|
|
|
|
glob_sta = igetdword(chip, ICHREG(GLOB_STA));
|
|
|
|
|
|
|
|
if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
|
|
|
|
goto __err;
|
|
|
|
pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
|
|
|
|
if (ac97_clock >= 8000 && ac97_clock <= 48000)
|
|
|
|
pbus->clock = ac97_clock;
|
|
|
|
chip->ac97_bus = pbus;
|
|
|
|
|
|
|
|
ac97.pci = chip->pci;
|
|
|
|
ac97.num = glob_sta & ICH_SCR ? 1 : 0;
|
|
|
|
if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
|
|
|
|
snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
|
|
|
|
if (ac97.num == 0)
|
|
|
|
goto __err;
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
chip->ac97 = x97;
|
|
|
|
if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
|
|
|
|
chip->ichd[ICHD_MDMIN].ac97 = x97;
|
|
|
|
chip->ichd[ICHD_MDMOUT].ac97 = x97;
|
|
|
|
}
|
|
|
|
|
|
|
|
chip->in_ac97_init = 0;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
__err:
|
|
|
|
/* clear the cold-reset bit for the next chance */
|
|
|
|
if (chip->device_type != DEVICE_ALI)
|
|
|
|
iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define do_delay(chip) do {\
|
|
|
|
set_current_state(TASK_UNINTERRUPTIBLE);\
|
|
|
|
schedule_timeout(1);\
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
static int snd_intel8x0m_ich_chip_init(intel8x0_t *chip, int probing)
|
|
|
|
{
|
|
|
|
unsigned long end_time;
|
|
|
|
unsigned int cnt, status, nstatus;
|
|
|
|
|
|
|
|
/* put logic to right state */
|
|
|
|
/* first clear status bits */
|
|
|
|
status = ICH_RCS | ICH_MIINT | ICH_MOINT;
|
|
|
|
cnt = igetdword(chip, ICHREG(GLOB_STA));
|
|
|
|
iputdword(chip, ICHREG(GLOB_STA), cnt & status);
|
|
|
|
|
|
|
|
/* ACLink on, 2 channels */
|
|
|
|
cnt = igetdword(chip, ICHREG(GLOB_CNT));
|
|
|
|
cnt &= ~(ICH_ACLINK);
|
|
|
|
/* finish cold or do warm reset */
|
|
|
|
cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
|
|
|
|
iputdword(chip, ICHREG(GLOB_CNT), cnt);
|
|
|
|
end_time = (jiffies + (HZ / 4)) + 1;
|
|
|
|
do {
|
|
|
|
if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
|
|
|
|
goto __ok;
|
|
|
|
do_delay(chip);
|
|
|
|
} while (time_after_eq(end_time, jiffies));
|
|
|
|
snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
__ok:
|
|
|
|
if (probing) {
|
|
|
|
/* wait for any codec ready status.
|
|
|
|
* Once it becomes ready it should remain ready
|
|
|
|
* as long as we do not disable the ac97 link.
|
|
|
|
*/
|
|
|
|
end_time = jiffies + HZ;
|
|
|
|
do {
|
|
|
|
status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
|
|
|
|
if (status)
|
|
|
|
break;
|
|
|
|
do_delay(chip);
|
|
|
|
} while (time_after_eq(end_time, jiffies));
|
|
|
|
if (! status) {
|
|
|
|
/* no codec is found */
|
|
|
|
snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* up to two codecs (modem cannot be tertiary with ICH4) */
|
|
|
|
nstatus = ICH_PCR | ICH_SCR;
|
|
|
|
|
|
|
|
/* wait for other codecs ready status. */
|
|
|
|
end_time = jiffies + HZ / 4;
|
|
|
|
while (status != nstatus && time_after_eq(end_time, jiffies)) {
|
|
|
|
do_delay(chip);
|
|
|
|
status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
|
|
|
|
}
|
|
|
|
|
|
|
|
} else {
|
|
|
|
/* resume phase */
|
|
|
|
status = 0;
|
|
|
|
if (chip->ac97)
|
|
|
|
status |= get_ich_codec_bit(chip, chip->ac97->num);
|
|
|
|
/* wait until all the probed codecs are ready */
|
|
|
|
end_time = jiffies + HZ;
|
|
|
|
do {
|
|
|
|
nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
|
|
|
|
if (status == nstatus)
|
|
|
|
break;
|
|
|
|
do_delay(chip);
|
|
|
|
} while (time_after_eq(end_time, jiffies));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (chip->device_type == DEVICE_SIS) {
|
|
|
|
/* unmute the output on SIS7012 */
|
|
|
|
iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
|
|
|
|
return err;
|
|
|
|
iagetword(chip, 0); /* clear semaphore flag */
|
|
|
|
|
|
|
|
/* disable interrupts */
|
|
|
|
for (i = 0; i < chip->bdbars_count; i++)
|
|
|
|
iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
|
|
|
|
/* reset channels */
|
|
|
|
for (i = 0; i < chip->bdbars_count; i++)
|
|
|
|
iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
|
|
|
|
/* initialize Buffer Descriptor Lists */
|
|
|
|
for (i = 0; i < chip->bdbars_count; i++)
|
|
|
|
iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0_free(intel8x0_t *chip)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
if (chip->irq < 0)
|
|
|
|
goto __hw_end;
|
|
|
|
/* disable interrupts */
|
|
|
|
for (i = 0; i < chip->bdbars_count; i++)
|
|
|
|
iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
|
|
|
|
/* reset channels */
|
|
|
|
for (i = 0; i < chip->bdbars_count; i++)
|
|
|
|
iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
|
|
|
|
/* --- */
|
|
|
|
synchronize_irq(chip->irq);
|
|
|
|
__hw_end:
|
|
|
|
if (chip->bdbars.area)
|
|
|
|
snd_dma_free_pages(&chip->bdbars);
|
|
|
|
if (chip->remap_addr)
|
|
|
|
iounmap(chip->remap_addr);
|
|
|
|
if (chip->remap_bmaddr)
|
|
|
|
iounmap(chip->remap_bmaddr);
|
|
|
|
if (chip->irq >= 0)
|
|
|
|
free_irq(chip->irq, (void *)chip);
|
|
|
|
pci_release_regions(chip->pci);
|
|
|
|
pci_disable_device(chip->pci);
|
|
|
|
kfree(chip);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
/*
|
|
|
|
* power management
|
|
|
|
*/
|
|
|
|
static int intel8x0m_suspend(snd_card_t *card, pm_message_t state)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = card->pm_private_data;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < chip->pcm_devs; i++)
|
|
|
|
snd_pcm_suspend_all(chip->pcm[i]);
|
|
|
|
if (chip->ac97)
|
|
|
|
snd_ac97_suspend(chip->ac97);
|
|
|
|
pci_disable_device(chip->pci);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int intel8x0m_resume(snd_card_t *card)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = card->pm_private_data;
|
|
|
|
pci_enable_device(chip->pci);
|
|
|
|
pci_set_master(chip->pci);
|
|
|
|
snd_intel8x0_chip_init(chip, 0);
|
|
|
|
if (chip->ac97)
|
|
|
|
snd_ac97_resume(chip->ac97);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
|
|
|
|
static void snd_intel8x0m_proc_read(snd_info_entry_t * entry,
|
|
|
|
snd_info_buffer_t * buffer)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = entry->private_data;
|
|
|
|
unsigned int tmp;
|
|
|
|
|
|
|
|
snd_iprintf(buffer, "Intel8x0m\n\n");
|
|
|
|
if (chip->device_type == DEVICE_ALI)
|
|
|
|
return;
|
|
|
|
tmp = igetdword(chip, ICHREG(GLOB_STA));
|
|
|
|
snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
|
|
|
|
snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
|
|
|
|
snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
|
|
|
|
tmp & ICH_PCR ? " primary" : "",
|
|
|
|
tmp & ICH_SCR ? " secondary" : "",
|
|
|
|
tmp & ICH_TCR ? " tertiary" : "",
|
|
|
|
(tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __devinit snd_intel8x0m_proc_init(intel8x0_t * chip)
|
|
|
|
{
|
|
|
|
snd_info_entry_t *entry;
|
|
|
|
|
|
|
|
if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
|
|
|
|
snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0m_proc_read);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int snd_intel8x0_dev_free(snd_device_t *device)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip = device->device_data;
|
|
|
|
return snd_intel8x0_free(chip);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct ich_reg_info {
|
|
|
|
unsigned int int_sta_mask;
|
|
|
|
unsigned int offset;
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __devinit snd_intel8x0m_create(snd_card_t * card,
|
|
|
|
struct pci_dev *pci,
|
|
|
|
unsigned long device_type,
|
|
|
|
intel8x0_t ** r_intel8x0)
|
|
|
|
{
|
|
|
|
intel8x0_t *chip;
|
|
|
|
int err;
|
|
|
|
unsigned int i;
|
|
|
|
unsigned int int_sta_masks;
|
|
|
|
ichdev_t *ichdev;
|
|
|
|
static snd_device_ops_t ops = {
|
|
|
|
.dev_free = snd_intel8x0_dev_free,
|
|
|
|
};
|
|
|
|
static struct ich_reg_info intel_regs[2] = {
|
|
|
|
{ ICH_MIINT, 0 },
|
|
|
|
{ ICH_MOINT, 0x10 },
|
|
|
|
};
|
|
|
|
struct ich_reg_info *tbl;
|
|
|
|
|
|
|
|
*r_intel8x0 = NULL;
|
|
|
|
|
|
|
|
if ((err = pci_enable_device(pci)) < 0)
|
|
|
|
return err;
|
|
|
|
|
[ALSA] Replace with kzalloc() - pci stuff
AD1889 driver,ATIIXP driver,ATIIXP-modem driver,AZT3328 driver
BT87x driver,CMIPCI driver,CS4281 driver,ENS1370/1+ driver
ES1938 driver,ES1968 driver,FM801 driver,Intel8x0 driver
Intel8x0-modem driver,Maestro3 driver,SonicVibes driver,VIA82xx driver
VIA82xx-modem driver,AC97 Codec,AK4531 codec,au88x0 driver
CA0106 driver,CS46xx driver,EMU10K1/EMU10K2 driver,HDA Codec driver
HDA generic driver,HDA Intel driver,ICE1712 driver,ICE1724 driver
KORG1212 driver,MIXART driver,NM256 driver,Trident driver,YMFPCI driver
Replace kcalloc(1,..) with kzalloc().
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2005-09-09 14:21:46 +02:00
|
|
|
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (chip == NULL) {
|
|
|
|
pci_disable_device(pci);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
spin_lock_init(&chip->reg_lock);
|
|
|
|
chip->device_type = device_type;
|
|
|
|
chip->card = card;
|
|
|
|
chip->pci = pci;
|
|
|
|
chip->irq = -1;
|
|
|
|
|
|
|
|
if ((err = pci_request_regions(pci, card->shortname)) < 0) {
|
|
|
|
kfree(chip);
|
|
|
|
pci_disable_device(pci);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (device_type == DEVICE_ALI) {
|
|
|
|
/* ALI5455 has no ac97 region */
|
|
|
|
chip->bmaddr = pci_resource_start(pci, 0);
|
|
|
|
goto port_inited;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
|
|
|
|
chip->mmio = 1;
|
|
|
|
chip->addr = pci_resource_start(pci, 2);
|
|
|
|
chip->remap_addr = ioremap_nocache(chip->addr,
|
|
|
|
pci_resource_len(pci, 2));
|
|
|
|
if (chip->remap_addr == NULL) {
|
|
|
|
snd_printk("AC'97 space ioremap problem\n");
|
|
|
|
snd_intel8x0_free(chip);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
chip->addr = pci_resource_start(pci, 0);
|
|
|
|
}
|
|
|
|
if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
|
|
|
|
chip->bm_mmio = 1;
|
|
|
|
chip->bmaddr = pci_resource_start(pci, 3);
|
|
|
|
chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
|
|
|
|
pci_resource_len(pci, 3));
|
|
|
|
if (chip->remap_bmaddr == NULL) {
|
|
|
|
snd_printk("Controller space ioremap problem\n");
|
|
|
|
snd_intel8x0_free(chip);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
chip->bmaddr = pci_resource_start(pci, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
port_inited:
|
|
|
|
if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
|
|
|
|
snd_printk("unable to grab IRQ %d\n", pci->irq);
|
|
|
|
snd_intel8x0_free(chip);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
chip->irq = pci->irq;
|
|
|
|
pci_set_master(pci);
|
|
|
|
synchronize_irq(chip->irq);
|
|
|
|
|
|
|
|
/* initialize offsets */
|
|
|
|
chip->bdbars_count = 2;
|
|
|
|
tbl = intel_regs;
|
|
|
|
|
|
|
|
for (i = 0; i < chip->bdbars_count; i++) {
|
|
|
|
ichdev = &chip->ichd[i];
|
|
|
|
ichdev->ichd = i;
|
|
|
|
ichdev->reg_offset = tbl[i].offset;
|
|
|
|
ichdev->int_sta_mask = tbl[i].int_sta_mask;
|
|
|
|
if (device_type == DEVICE_SIS) {
|
|
|
|
/* SiS 7013 swaps the registers */
|
|
|
|
ichdev->roff_sr = ICH_REG_OFF_PICB;
|
|
|
|
ichdev->roff_picb = ICH_REG_OFF_SR;
|
|
|
|
} else {
|
|
|
|
ichdev->roff_sr = ICH_REG_OFF_SR;
|
|
|
|
ichdev->roff_picb = ICH_REG_OFF_PICB;
|
|
|
|
}
|
|
|
|
if (device_type == DEVICE_ALI)
|
|
|
|
ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
|
|
|
|
}
|
|
|
|
/* SIS7013 handles the pcm data in bytes, others are in words */
|
|
|
|
chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
|
|
|
|
|
|
|
|
/* allocate buffer descriptor lists */
|
|
|
|
/* the start of each lists must be aligned to 8 bytes */
|
|
|
|
if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
|
|
|
|
chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
|
|
|
|
&chip->bdbars) < 0) {
|
|
|
|
snd_intel8x0_free(chip);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
/* tables must be aligned to 8 bytes here, but the kernel pages
|
|
|
|
are much bigger, so we don't care (on i386) */
|
|
|
|
int_sta_masks = 0;
|
|
|
|
for (i = 0; i < chip->bdbars_count; i++) {
|
|
|
|
ichdev = &chip->ichd[i];
|
|
|
|
ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
|
|
|
|
ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
|
|
|
|
int_sta_masks |= ichdev->int_sta_mask;
|
|
|
|
}
|
|
|
|
chip->int_sta_reg = ICH_REG_GLOB_STA;
|
|
|
|
chip->int_sta_mask = int_sta_masks;
|
|
|
|
|
|
|
|
if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
|
|
|
|
snd_intel8x0_free(chip);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
snd_card_set_pm_callback(card, intel8x0m_suspend, intel8x0m_resume, chip);
|
|
|
|
|
|
|
|
if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
|
|
|
|
snd_intel8x0_free(chip);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
snd_card_set_dev(card, &pci->dev);
|
|
|
|
|
|
|
|
*r_intel8x0 = chip;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct shortname_table {
|
|
|
|
unsigned int id;
|
|
|
|
const char *s;
|
|
|
|
} shortnames[] __devinitdata = {
|
[ALSA] Remove superfluous PCI ID definitions
CS46xx driver,EMU10K1/EMU10K2 driver,PCM Midlevel,Trident driver
YMFPCI driver,BT87x driver,CMIPCI driver,CS4281 driver
ENS1370/1+ driver,ES1938 driver,ES1968 driver,Intel8x0 driver
Intel8x0-modem driver,Maestro3 driver,RME32 driver,RME96 driver
SonicVibes driver,VIA82xx driver,ALI5451 driver,ICE1712 driver
ICE1724 driver,NM256 driver,RME HDSP driver,RME9652 driver
Remove superfluous PCI ID definitions.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2005-09-07 14:08:11 +02:00
|
|
|
{ PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
|
2005-04-17 00:20:36 +02:00
|
|
|
{ PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
|
|
|
|
{ PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
|
[ALSA] Remove superfluous PCI ID definitions
CS46xx driver,EMU10K1/EMU10K2 driver,PCM Midlevel,Trident driver
YMFPCI driver,BT87x driver,CMIPCI driver,CS4281 driver
ENS1370/1+ driver,ES1938 driver,ES1968 driver,Intel8x0 driver
Intel8x0-modem driver,Maestro3 driver,RME32 driver,RME96 driver
SonicVibes driver,VIA82xx driver,ALI5451 driver,ICE1712 driver
ICE1724 driver,NM256 driver,RME HDSP driver,RME9652 driver
Remove superfluous PCI ID definitions.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2005-09-07 14:08:11 +02:00
|
|
|
{ PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
|
|
|
|
{ PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
|
|
|
|
{ PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
|
2005-04-17 00:20:36 +02:00
|
|
|
{ 0x7446, "AMD AMD768" },
|
|
|
|
{ PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
|
[ALSA] Remove superfluous PCI ID definitions
CS46xx driver,EMU10K1/EMU10K2 driver,PCM Midlevel,Trident driver
YMFPCI driver,BT87x driver,CMIPCI driver,CS4281 driver
ENS1370/1+ driver,ES1938 driver,ES1968 driver,Intel8x0 driver
Intel8x0-modem driver,Maestro3 driver,RME32 driver,RME96 driver
SonicVibes driver,VIA82xx driver,ALI5451 driver,ICE1712 driver
ICE1724 driver,NM256 driver,RME HDSP driver,RME9652 driver
Remove superfluous PCI ID definitions.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2005-09-07 14:08:11 +02:00
|
|
|
{ PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
|
2005-04-17 00:20:36 +02:00
|
|
|
{ PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
|
|
|
|
{ PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
|
|
|
|
{ PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
|
|
|
|
#if 0
|
|
|
|
{ 0x5455, "ALi M5455" },
|
|
|
|
{ 0x746d, "AMD AMD8111" },
|
|
|
|
#endif
|
|
|
|
{ 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
|
|
|
|
const struct pci_device_id *pci_id)
|
|
|
|
{
|
|
|
|
snd_card_t *card;
|
|
|
|
intel8x0_t *chip;
|
|
|
|
int err;
|
|
|
|
struct shortname_table *name;
|
|
|
|
|
2005-10-04 08:46:51 +02:00
|
|
|
card = snd_card_new(index, id, THIS_MODULE, 0);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (card == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
strcpy(card->driver, "ICH-MODEM");
|
|
|
|
strcpy(card->shortname, "Intel ICH");
|
|
|
|
for (name = shortnames; name->id; name++) {
|
|
|
|
if (pci->device == name->id) {
|
|
|
|
strcpy(card->shortname, name->s);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
strcat(card->shortname," Modem");
|
|
|
|
|
|
|
|
if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
|
|
|
|
snd_card_free(card);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2005-10-04 08:46:51 +02:00
|
|
|
if ((err = snd_intel8x0_mixer(chip, ac97_clock)) < 0) {
|
2005-04-17 00:20:36 +02:00
|
|
|
snd_card_free(card);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
if ((err = snd_intel8x0_pcm(chip)) < 0) {
|
|
|
|
snd_card_free(card);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
snd_intel8x0m_proc_init(chip);
|
|
|
|
|
|
|
|
sprintf(card->longname, "%s at 0x%lx, irq %i",
|
|
|
|
card->shortname, chip->addr, chip->irq);
|
|
|
|
|
|
|
|
if ((err = snd_card_register(card)) < 0) {
|
|
|
|
snd_card_free(card);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
pci_set_drvdata(pci, card);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
|
|
|
|
{
|
|
|
|
snd_card_free(pci_get_drvdata(pci));
|
|
|
|
pci_set_drvdata(pci, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_driver driver = {
|
|
|
|
.name = "Intel ICH Modem",
|
[ALSA] set owner field in struct pci_driver
AD1889 driver,ALS4000 driver,ATIIXP driver,ATIIXP-modem driver
AZT3328 driver,BT87x driver,CMIPCI driver,CS4281 driver
ENS1370/1+ driver,ES1938 driver,ES1968 driver,FM801 driver
Intel8x0 driver,Intel8x0-modem driver,Maestro3 driver,RME32 driver
RME96 driver,SonicVibes driver,VIA82xx driver,VIA82xx-modem driver
ALI5451 driver,au88x0 driver,CS46xx driver,EMU10K1/EMU10K2 driver
HDA Intel driver,ICE1712 driver,ICE1724 driver,KORG1212 driver
MIXART driver,NM256 driver,RME HDSP driver,RME9652 driver
Trident driver,Digigram VX222 driver,YMFPCI driver
Set the module owner field in each driver's struct pci_driver to get
the driver symlink in the sysfs device directory.
Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
2005-09-12 08:20:54 +02:00
|
|
|
.owner = THIS_MODULE,
|
2005-04-17 00:20:36 +02:00
|
|
|
.id_table = snd_intel8x0m_ids,
|
|
|
|
.probe = snd_intel8x0m_probe,
|
|
|
|
.remove = __devexit_p(snd_intel8x0m_remove),
|
|
|
|
SND_PCI_PM_CALLBACKS
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static int __init alsa_card_intel8x0m_init(void)
|
|
|
|
{
|
[ALSA] Replace pci_module_init() with pci_register_driver()
Documentation,ALS4000 driver,ATIIXP driver,ATIIXP-modem driver
AZT3328 driver,BT87x driver,CMIPCI driver,CS4281 driver
ENS1370/1+ driver,ES1938 driver,ES1968 driver,FM801 driver
Intel8x0 driver,Intel8x0-modem driver,Maestro3 driver,RME32 driver
RME96 driver,SonicVibes driver,VIA82xx driver,VIA82xx-modem driver
ALI5451 driver,au88x0 driver,CA0106 driver,CS46xx driver
EMU10K1/EMU10K2 driver,HDA Intel driver,ICE1712 driver,ICE1724 driver
KORG1212 driver,MIXART driver,NM256 driver,RME HDSP driver
RME9652 driver,Trident driver,Digigram VX222 driver,YMFPCI driver
Replace the obsolete pci_module_init() with pci_register_driver().
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2005-04-11 16:58:24 +02:00
|
|
|
return pci_register_driver(&driver);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit alsa_card_intel8x0m_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(alsa_card_intel8x0m_init)
|
|
|
|
module_exit(alsa_card_intel8x0m_exit)
|