2011-02-16 13:39:16 +01:00
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/*
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* Freescale MXS I2C bus driver
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*
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2012-10-12 12:55:16 +02:00
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* Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
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2011-02-16 13:39:16 +01:00
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*
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* based on a (non-working) driver which was:
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*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/completion.h>
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#include <linux/platform_device.h>
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#include <linux/jiffies.h>
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#include <linux/io.h>
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2012-05-06 16:59:45 +02:00
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#include <linux/pinctrl/consumer.h>
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2011-08-31 20:37:50 +02:00
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#include <linux/stmp_device.h>
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2012-05-12 07:43:32 +02:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_i2c.h>
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2012-08-24 05:44:31 +02:00
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/fsl/mxs-dma.h>
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2011-02-16 13:39:16 +01:00
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#define DRIVER_NAME "mxs-i2c"
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#define MXS_I2C_CTRL0 (0x00)
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#define MXS_I2C_CTRL0_SET (0x04)
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#define MXS_I2C_CTRL0_SFTRST 0x80000000
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#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
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#define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
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#define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
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#define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
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#define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
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#define MXS_I2C_CTRL0_DIRECTION 0x00010000
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#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
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2012-07-09 18:22:53 +02:00
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#define MXS_I2C_TIMING0 (0x10)
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#define MXS_I2C_TIMING1 (0x20)
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#define MXS_I2C_TIMING2 (0x30)
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2011-02-16 13:39:16 +01:00
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#define MXS_I2C_CTRL1 (0x40)
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#define MXS_I2C_CTRL1_SET (0x44)
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#define MXS_I2C_CTRL1_CLR (0x48)
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#define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
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#define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
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#define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
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#define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
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#define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
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#define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
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#define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
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#define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
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#define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
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MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
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MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
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MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
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MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
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MXS_I2C_CTRL1_SLAVE_IRQ)
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#define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
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MXS_I2C_CTRL0_PRE_SEND_START | \
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MXS_I2C_CTRL0_MASTER_MODE | \
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MXS_I2C_CTRL0_DIRECTION | \
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MXS_I2C_CTRL0_XFER_COUNT(1))
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#define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
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MXS_I2C_CTRL0_MASTER_MODE | \
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MXS_I2C_CTRL0_DIRECTION)
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#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
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MXS_I2C_CTRL0_MASTER_MODE)
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2012-07-09 18:22:53 +02:00
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struct mxs_i2c_speed_config {
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uint32_t timing0;
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uint32_t timing1;
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uint32_t timing2;
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};
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/*
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* Timing values for the default 24MHz clock supplied into the i2c block.
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*
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* The bus can operate at 95kHz or at 400kHz with the following timing
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* register configurations. The 100kHz mode isn't present because it's
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* values are not stated in the i.MX233/i.MX28 datasheet. The 95kHz mode
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* shall be close enough replacement. Therefore when the bus is configured
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* for 100kHz operation, 95kHz timing settings are actually loaded.
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*
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* For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
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*/
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static const struct mxs_i2c_speed_config mxs_i2c_95kHz_config = {
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.timing0 = 0x00780030,
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.timing1 = 0x00800030,
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.timing2 = 0x00300030,
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};
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static const struct mxs_i2c_speed_config mxs_i2c_400kHz_config = {
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.timing0 = 0x000f0007,
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.timing1 = 0x001f000f,
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.timing2 = 0x00300030,
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};
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2011-02-16 13:39:16 +01:00
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/**
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* struct mxs_i2c_dev - per device, private MXS-I2C data
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*
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* @dev: driver model device node
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* @regs: IO registers pointer
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* @cmd_complete: completion object for transaction wait
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* @cmd_err: error code for last transaction
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* @adapter: i2c subsystem adapter node
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*/
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struct mxs_i2c_dev {
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struct device *dev;
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void __iomem *regs;
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struct completion cmd_complete;
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u32 cmd_err;
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struct i2c_adapter adapter;
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2012-07-09 18:22:53 +02:00
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const struct mxs_i2c_speed_config *speed;
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2012-08-24 05:44:31 +02:00
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/* DMA support components */
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int dma_channel;
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struct dma_chan *dmach;
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struct mxs_dma_data dma_data;
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uint32_t pio_data[2];
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uint32_t addr_data;
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struct scatterlist sg_io[2];
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bool dma_read;
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2011-02-16 13:39:16 +01:00
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};
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static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
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{
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2011-08-31 20:37:50 +02:00
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stmp_reset_block(i2c->regs);
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2012-07-09 18:22:53 +02:00
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writel(i2c->speed->timing0, i2c->regs + MXS_I2C_TIMING0);
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writel(i2c->speed->timing1, i2c->regs + MXS_I2C_TIMING1);
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writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2);
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2011-02-16 13:39:16 +01:00
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writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
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}
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2012-08-24 05:44:31 +02:00
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static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
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{
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if (i2c->dma_read) {
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dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
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dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
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} else {
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dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
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}
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}
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static void mxs_i2c_dma_irq_callback(void *param)
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{
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struct mxs_i2c_dev *i2c = param;
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complete(&i2c->cmd_complete);
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mxs_i2c_dma_finish(i2c);
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}
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static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msg, uint32_t flags)
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{
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struct dma_async_tx_descriptor *desc;
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struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
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if (msg->flags & I2C_M_RD) {
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i2c->dma_read = 1;
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i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
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/*
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* SELECT command.
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*/
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/* Queue the PIO register write transfer. */
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i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
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desc = dmaengine_prep_slave_sg(i2c->dmach,
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(struct scatterlist *)&i2c->pio_data[0],
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1, DMA_TRANS_NONE, 0);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get PIO reg. write descriptor.\n");
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goto select_init_pio_fail;
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}
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/* Queue the DMA data transfer. */
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sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
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dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
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desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get DMA data write descriptor.\n");
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goto select_init_dma_fail;
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}
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/*
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* READ command.
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*/
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/* Queue the PIO register write transfer. */
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i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
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MXS_I2C_CTRL0_XFER_COUNT(msg->len);
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desc = dmaengine_prep_slave_sg(i2c->dmach,
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(struct scatterlist *)&i2c->pio_data[1],
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1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get PIO reg. write descriptor.\n");
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goto select_init_dma_fail;
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}
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/* Queue the DMA data transfer. */
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sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
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dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
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desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get DMA data write descriptor.\n");
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goto read_init_dma_fail;
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}
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} else {
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i2c->dma_read = 0;
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i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
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/*
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* WRITE command.
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*/
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/* Queue the PIO register write transfer. */
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i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
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MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
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desc = dmaengine_prep_slave_sg(i2c->dmach,
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(struct scatterlist *)&i2c->pio_data[0],
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1, DMA_TRANS_NONE, 0);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get PIO reg. write descriptor.\n");
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goto write_init_pio_fail;
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}
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/* Queue the DMA data transfer. */
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sg_init_table(i2c->sg_io, 2);
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sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
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sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
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dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
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desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get DMA data write descriptor.\n");
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goto write_init_dma_fail;
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}
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}
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/*
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* The last descriptor must have this callback,
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* to finish the DMA transaction.
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*/
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desc->callback = mxs_i2c_dma_irq_callback;
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desc->callback_param = i2c;
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/* Start the transfer. */
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dmaengine_submit(desc);
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dma_async_issue_pending(i2c->dmach);
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return 0;
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/* Read failpath. */
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read_init_dma_fail:
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dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
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select_init_dma_fail:
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dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
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select_init_pio_fail:
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2012-11-18 06:25:07 +01:00
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dmaengine_terminate_all(i2c->dmach);
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2012-08-24 05:44:31 +02:00
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return -EINVAL;
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/* Write failpath. */
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write_init_dma_fail:
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dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
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write_init_pio_fail:
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2012-11-18 06:25:07 +01:00
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dmaengine_terminate_all(i2c->dmach);
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2012-08-24 05:44:31 +02:00
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return -EINVAL;
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}
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2011-02-16 13:39:16 +01:00
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/*
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* Low level master read/write transaction.
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*/
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static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
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int stop)
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{
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struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
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int ret;
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int flags;
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2012-08-24 05:44:31 +02:00
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flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
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|
|
2011-02-16 13:39:16 +01:00
|
|
|
dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
|
|
|
|
msg->addr, msg->len, msg->flags, stop);
|
|
|
|
|
|
|
|
if (msg->len == 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2012-01-13 12:14:26 +01:00
|
|
|
init_completion(&i2c->cmd_complete);
|
2012-04-05 16:15:24 +02:00
|
|
|
i2c->cmd_err = 0;
|
2012-01-13 12:14:26 +01:00
|
|
|
|
2012-10-12 12:55:16 +02:00
|
|
|
ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2011-02-16 13:39:16 +01:00
|
|
|
|
|
|
|
ret = wait_for_completion_timeout(&i2c->cmd_complete,
|
|
|
|
msecs_to_jiffies(1000));
|
|
|
|
if (ret == 0)
|
|
|
|
goto timeout;
|
|
|
|
|
|
|
|
if (i2c->cmd_err == -ENXIO)
|
|
|
|
mxs_i2c_reset(i2c);
|
|
|
|
|
|
|
|
dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
|
|
|
|
|
|
|
|
return i2c->cmd_err;
|
|
|
|
|
|
|
|
timeout:
|
|
|
|
dev_dbg(i2c->dev, "Timeout!\n");
|
2012-10-12 12:55:16 +02:00
|
|
|
mxs_i2c_dma_finish(i2c);
|
2011-02-16 13:39:16 +01:00
|
|
|
mxs_i2c_reset(i2c);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
|
|
|
|
int num)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
for (i = 0; i < num; i++) {
|
|
|
|
err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return num;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 mxs_i2c_func(struct i2c_adapter *adap)
|
|
|
|
{
|
2012-11-18 06:25:08 +01:00
|
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
2011-02-16 13:39:16 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct mxs_i2c_dev *i2c = dev_id;
|
|
|
|
u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
|
|
|
|
|
|
|
|
if (!stat)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
|
|
|
|
i2c->cmd_err = -ENXIO;
|
|
|
|
else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
|
|
|
|
MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
|
|
|
|
MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
|
|
|
|
/* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
|
|
|
|
i2c->cmd_err = -EIO;
|
|
|
|
|
|
|
|
writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
|
2012-01-13 12:14:26 +01:00
|
|
|
|
2011-02-16 13:39:16 +01:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct i2c_algorithm mxs_i2c_algo = {
|
|
|
|
.master_xfer = mxs_i2c_xfer,
|
|
|
|
.functionality = mxs_i2c_func,
|
|
|
|
};
|
|
|
|
|
2012-08-24 05:44:31 +02:00
|
|
|
static bool mxs_i2c_dma_filter(struct dma_chan *chan, void *param)
|
|
|
|
{
|
|
|
|
struct mxs_i2c_dev *i2c = param;
|
|
|
|
|
|
|
|
if (!mxs_dma_is_apbx(chan))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (chan->chan_id != i2c->dma_channel)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
chan->private = &i2c->dma_data;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-07-09 18:22:53 +02:00
|
|
|
static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
|
|
|
|
{
|
|
|
|
uint32_t speed;
|
|
|
|
struct device *dev = i2c->dev;
|
|
|
|
struct device_node *node = dev->of_node;
|
|
|
|
int ret;
|
|
|
|
|
2012-08-24 05:44:31 +02:00
|
|
|
/*
|
|
|
|
* TODO: This is a temporary solution and should be changed
|
|
|
|
* to use generic DMA binding later when the helpers get in.
|
|
|
|
*/
|
|
|
|
ret = of_property_read_u32(node, "fsl,i2c-dma-channel",
|
|
|
|
&i2c->dma_channel);
|
|
|
|
if (ret) {
|
2012-10-12 12:55:16 +02:00
|
|
|
dev_err(dev, "Failed to get DMA channel!\n");
|
|
|
|
return -ENODEV;
|
2012-08-24 05:44:31 +02:00
|
|
|
}
|
|
|
|
|
2012-07-09 18:22:53 +02:00
|
|
|
ret = of_property_read_u32(node, "clock-frequency", &speed);
|
|
|
|
if (ret)
|
|
|
|
dev_warn(dev, "No I2C speed selected, using 100kHz\n");
|
|
|
|
else if (speed == 400000)
|
|
|
|
i2c->speed = &mxs_i2c_400kHz_config;
|
|
|
|
else if (speed != 100000)
|
|
|
|
dev_warn(dev, "Unsupported I2C speed selected, using 100kHz\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-27 21:59:38 +01:00
|
|
|
static int mxs_i2c_probe(struct platform_device *pdev)
|
2011-02-16 13:39:16 +01:00
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct mxs_i2c_dev *i2c;
|
|
|
|
struct i2c_adapter *adap;
|
2012-05-06 16:59:45 +02:00
|
|
|
struct pinctrl *pinctrl;
|
2011-02-16 13:39:16 +01:00
|
|
|
struct resource *res;
|
|
|
|
resource_size_t res_size;
|
2012-08-24 05:44:31 +02:00
|
|
|
int err, irq, dmairq;
|
|
|
|
dma_cap_mask_t mask;
|
2011-02-16 13:39:16 +01:00
|
|
|
|
2012-05-06 16:59:45 +02:00
|
|
|
pinctrl = devm_pinctrl_get_select_default(dev);
|
|
|
|
if (IS_ERR(pinctrl))
|
|
|
|
return PTR_ERR(pinctrl);
|
|
|
|
|
2011-02-16 13:39:16 +01:00
|
|
|
i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
|
|
|
|
if (!i2c)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2012-08-24 05:44:31 +02:00
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
dmairq = platform_get_irq(pdev, 1);
|
|
|
|
|
|
|
|
if (!res || irq < 0 || dmairq < 0)
|
2011-02-16 13:39:16 +01:00
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
res_size = resource_size(res);
|
|
|
|
if (!devm_request_mem_region(dev, res->start, res_size, res->name))
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
|
|
|
|
if (!i2c->regs)
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
i2c->dev = dev;
|
2012-09-08 17:28:06 +02:00
|
|
|
i2c->speed = &mxs_i2c_95kHz_config;
|
2012-07-09 18:22:53 +02:00
|
|
|
|
2012-09-08 17:28:06 +02:00
|
|
|
if (dev->of_node) {
|
|
|
|
err = mxs_i2c_get_ofdata(i2c);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
2012-07-09 18:22:53 +02:00
|
|
|
|
2012-08-24 05:44:31 +02:00
|
|
|
/* Setup the DMA */
|
2012-10-12 12:55:16 +02:00
|
|
|
dma_cap_zero(mask);
|
|
|
|
dma_cap_set(DMA_SLAVE, mask);
|
|
|
|
i2c->dma_data.chan_irq = dmairq;
|
|
|
|
i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c);
|
|
|
|
if (!i2c->dmach) {
|
|
|
|
dev_err(dev, "Failed to request dma\n");
|
|
|
|
return -ENODEV;
|
2012-08-24 05:44:31 +02:00
|
|
|
}
|
|
|
|
|
2011-02-16 13:39:16 +01:00
|
|
|
platform_set_drvdata(pdev, i2c);
|
|
|
|
|
|
|
|
/* Do reset to enforce correct startup after pinmuxing */
|
|
|
|
mxs_i2c_reset(i2c);
|
|
|
|
|
|
|
|
adap = &i2c->adapter;
|
|
|
|
strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
|
|
|
|
adap->owner = THIS_MODULE;
|
|
|
|
adap->algo = &mxs_i2c_algo;
|
|
|
|
adap->dev.parent = dev;
|
|
|
|
adap->nr = pdev->id;
|
2012-05-12 07:43:32 +02:00
|
|
|
adap->dev.of_node = pdev->dev.of_node;
|
2011-02-16 13:39:16 +01:00
|
|
|
i2c_set_adapdata(adap, i2c);
|
|
|
|
err = i2c_add_numbered_adapter(adap);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "Failed to add adapter (%d)\n", err);
|
|
|
|
writel(MXS_I2C_CTRL0_SFTRST,
|
|
|
|
i2c->regs + MXS_I2C_CTRL0_SET);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2012-05-12 07:43:32 +02:00
|
|
|
of_i2c_register_devices(adap);
|
|
|
|
|
2011-02-16 13:39:16 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-27 21:59:38 +01:00
|
|
|
static int mxs_i2c_remove(struct platform_device *pdev)
|
2011-02-16 13:39:16 +01:00
|
|
|
{
|
|
|
|
struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = i2c_del_adapter(&i2c->adapter);
|
|
|
|
if (ret)
|
|
|
|
return -EBUSY;
|
|
|
|
|
2012-08-24 05:44:31 +02:00
|
|
|
if (i2c->dmach)
|
|
|
|
dma_release_channel(i2c->dmach);
|
|
|
|
|
2011-02-16 13:39:16 +01:00
|
|
|
writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-12 07:43:32 +02:00
|
|
|
static const struct of_device_id mxs_i2c_dt_ids[] = {
|
|
|
|
{ .compatible = "fsl,imx28-i2c", },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
|
|
|
|
|
2011-02-16 13:39:16 +01:00
|
|
|
static struct platform_driver mxs_i2c_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.owner = THIS_MODULE,
|
2012-05-12 07:43:32 +02:00
|
|
|
.of_match_table = mxs_i2c_dt_ids,
|
2011-02-16 13:39:16 +01:00
|
|
|
},
|
2012-11-27 21:59:38 +01:00
|
|
|
.remove = mxs_i2c_remove,
|
2011-02-16 13:39:16 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __init mxs_i2c_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
|
|
|
|
}
|
|
|
|
subsys_initcall(mxs_i2c_init);
|
|
|
|
|
|
|
|
static void __exit mxs_i2c_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&mxs_i2c_driver);
|
|
|
|
}
|
|
|
|
module_exit(mxs_i2c_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
|
|
|
|
MODULE_DESCRIPTION("MXS I2C Bus Driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|