2008-10-23 07:26:29 +02:00
|
|
|
#ifndef _ASM_X86_PERCPU_H
|
|
|
|
|
#define _ASM_X86_PERCPU_H
|
2008-01-30 13:32:53 +01:00
|
|
|
|
2009-01-13 12:41:35 +01:00
|
|
|
#ifdef CONFIG_X86_64
|
2009-01-13 12:41:35 +01:00
|
|
|
#define __percpu_seg gs
|
|
|
|
|
#define __percpu_mov_op movq
|
2009-01-13 12:41:35 +01:00
|
|
|
#else
|
2009-01-13 12:41:35 +01:00
|
|
|
#define __percpu_seg fs
|
|
|
|
|
#define __percpu_mov_op movl
|
2007-10-11 11:20:03 +02:00
|
|
|
#endif
|
2008-01-30 13:32:53 +01:00
|
|
|
|
|
|
|
|
#ifdef __ASSEMBLY__
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* PER_CPU finds an address of a per-cpu variable.
|
|
|
|
|
*
|
|
|
|
|
* Args:
|
|
|
|
|
* var - variable name
|
|
|
|
|
* reg - 32bit register
|
|
|
|
|
*
|
|
|
|
|
* The resulting address is stored in the "reg" argument.
|
|
|
|
|
*
|
|
|
|
|
* Example:
|
|
|
|
|
* PER_CPU(cpu_gdt_descr, %ebx)
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_SMP
|
2009-01-13 12:41:35 +01:00
|
|
|
#define PER_CPU(var, reg) \
|
2009-10-29 14:34:15 +01:00
|
|
|
__percpu_mov_op %__percpu_seg:this_cpu_off, reg; \
|
|
|
|
|
lea var(reg), reg
|
|
|
|
|
#define PER_CPU_VAR(var) %__percpu_seg:var
|
2008-01-30 13:32:53 +01:00
|
|
|
#else /* ! SMP */
|
2009-10-29 14:34:15 +01:00
|
|
|
#define PER_CPU(var, reg) __percpu_mov_op $var, reg
|
|
|
|
|
#define PER_CPU_VAR(var) var
|
2008-01-30 13:32:53 +01:00
|
|
|
#endif /* SMP */
|
|
|
|
|
|
2009-02-08 15:58:39 +01:00
|
|
|
#ifdef CONFIG_X86_64_SMP
|
|
|
|
|
#define INIT_PER_CPU_VAR(var) init_per_cpu__##var
|
|
|
|
|
#else
|
2009-10-29 14:34:15 +01:00
|
|
|
#define INIT_PER_CPU_VAR(var) var
|
2009-02-08 15:58:39 +01:00
|
|
|
#endif
|
|
|
|
|
|
2008-01-30 13:32:53 +01:00
|
|
|
#else /* ...!ASSEMBLY */
|
|
|
|
|
|
2009-06-22 04:56:24 +02:00
|
|
|
#include <linux/kernel.h>
|
2009-01-13 12:41:35 +01:00
|
|
|
#include <linux/stringify.h>
|
2008-01-30 13:32:53 +01:00
|
|
|
|
2009-01-13 12:41:35 +01:00
|
|
|
#ifdef CONFIG_SMP
|
2011-03-27 03:57:18 +02:00
|
|
|
#define __percpu_prefix "%%"__stringify(__percpu_seg)":"
|
percpu: add optimized generic percpu accessors
It is an optimization and a cleanup, and adds the following new
generic percpu methods:
percpu_read()
percpu_write()
percpu_add()
percpu_sub()
percpu_and()
percpu_or()
percpu_xor()
and implements support for them on x86. (other architectures will fall
back to a default implementation)
The advantage is that for example to read a local percpu variable,
instead of this sequence:
return __get_cpu_var(var);
ffffffff8102ca2b: 48 8b 14 fd 80 09 74 mov -0x7e8bf680(,%rdi,8),%rdx
ffffffff8102ca32: 81
ffffffff8102ca33: 48 c7 c0 d8 59 00 00 mov $0x59d8,%rax
ffffffff8102ca3a: 48 8b 04 10 mov (%rax,%rdx,1),%rax
We can get a single instruction by using the optimized variants:
return percpu_read(var);
ffffffff8102ca3f: 65 48 8b 05 91 8f fd mov %gs:0x7efd8f91(%rip),%rax
I also cleaned up the x86-specific APIs and made the x86 code use
these new generic percpu primitives.
tj: * fixed generic percpu_sub() definition as Roel Kluin pointed out
* added percpu_and() for completeness's sake
* made generic percpu ops atomic against preemption
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Tejun Heo <tj@kernel.org>
2009-01-15 14:15:53 +01:00
|
|
|
#define __my_cpu_offset percpu_read(this_cpu_off)
|
2010-09-09 18:17:26 +02:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Compared to the generic __my_cpu_offset version, the following
|
|
|
|
|
* saves one instruction and avoids clobbering a temp register.
|
|
|
|
|
*/
|
|
|
|
|
#define __this_cpu_ptr(ptr) \
|
|
|
|
|
({ \
|
|
|
|
|
unsigned long tcp_ptr__; \
|
|
|
|
|
__verify_pcpu_ptr(ptr); \
|
|
|
|
|
asm volatile("add " __percpu_arg(1) ", %0" \
|
|
|
|
|
: "=r" (tcp_ptr__) \
|
|
|
|
|
: "m" (this_cpu_off), "0" (ptr)); \
|
|
|
|
|
(typeof(*(ptr)) __kernel __force *)tcp_ptr__; \
|
|
|
|
|
})
|
2009-01-13 12:41:35 +01:00
|
|
|
#else
|
2011-03-27 03:57:18 +02:00
|
|
|
#define __percpu_prefix ""
|
2009-01-13 12:41:35 +01:00
|
|
|
#endif
|
2008-01-30 13:32:53 +01:00
|
|
|
|
2011-03-27 03:57:18 +02:00
|
|
|
#define __percpu_arg(x) __percpu_prefix "%P" #x
|
|
|
|
|
|
2009-02-08 15:58:39 +01:00
|
|
|
/*
|
|
|
|
|
* Initialized pointers to per-cpu variables needed for the boot
|
|
|
|
|
* processor need to use these macros to get the proper address
|
|
|
|
|
* offset from __per_cpu_load on SMP.
|
|
|
|
|
*
|
|
|
|
|
* There also must be an entry in vmlinux_64.lds.S
|
|
|
|
|
*/
|
|
|
|
|
#define DECLARE_INIT_PER_CPU(var) \
|
2009-10-29 14:34:15 +01:00
|
|
|
extern typeof(var) init_per_cpu_var(var)
|
2009-02-08 15:58:39 +01:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_X86_64_SMP
|
|
|
|
|
#define init_per_cpu_var(var) init_per_cpu__##var
|
|
|
|
|
#else
|
2009-10-29 14:34:15 +01:00
|
|
|
#define init_per_cpu_var(var) var
|
2009-02-08 15:58:39 +01:00
|
|
|
#endif
|
|
|
|
|
|
2008-01-30 13:32:53 +01:00
|
|
|
/* For arch-specific code, we can use direct single-insn ops (they
|
|
|
|
|
* don't give an lvalue though). */
|
|
|
|
|
extern void __bad_percpu_size(void);
|
|
|
|
|
|
2008-03-23 09:03:06 +01:00
|
|
|
#define percpu_to_op(op, var, val) \
|
|
|
|
|
do { \
|
2009-10-29 14:34:12 +01:00
|
|
|
typedef typeof(var) pto_T__; \
|
2008-03-23 09:03:06 +01:00
|
|
|
if (0) { \
|
2009-10-29 14:34:12 +01:00
|
|
|
pto_T__ pto_tmp__; \
|
|
|
|
|
pto_tmp__ = (val); \
|
2010-06-10 13:10:36 +02:00
|
|
|
(void)pto_tmp__; \
|
2008-03-23 09:03:06 +01:00
|
|
|
} \
|
|
|
|
|
switch (sizeof(var)) { \
|
|
|
|
|
case 1: \
|
2009-01-18 16:38:59 +01:00
|
|
|
asm(op "b %1,"__percpu_arg(0) \
|
2008-03-23 09:03:06 +01:00
|
|
|
: "+m" (var) \
|
2009-10-29 14:34:12 +01:00
|
|
|
: "qi" ((pto_T__)(val))); \
|
2008-03-23 09:03:06 +01:00
|
|
|
break; \
|
|
|
|
|
case 2: \
|
2009-01-18 16:38:59 +01:00
|
|
|
asm(op "w %1,"__percpu_arg(0) \
|
2008-03-23 09:03:06 +01:00
|
|
|
: "+m" (var) \
|
2009-10-29 14:34:12 +01:00
|
|
|
: "ri" ((pto_T__)(val))); \
|
2008-03-23 09:03:06 +01:00
|
|
|
break; \
|
|
|
|
|
case 4: \
|
2009-01-18 16:38:59 +01:00
|
|
|
asm(op "l %1,"__percpu_arg(0) \
|
2008-03-23 09:03:06 +01:00
|
|
|
: "+m" (var) \
|
2009-10-29 14:34:12 +01:00
|
|
|
: "ri" ((pto_T__)(val))); \
|
2008-03-23 09:03:06 +01:00
|
|
|
break; \
|
2009-01-13 12:41:35 +01:00
|
|
|
case 8: \
|
2009-01-18 16:38:59 +01:00
|
|
|
asm(op "q %1,"__percpu_arg(0) \
|
2009-01-13 12:41:35 +01:00
|
|
|
: "+m" (var) \
|
2009-10-29 14:34:12 +01:00
|
|
|
: "re" ((pto_T__)(val))); \
|
2009-01-13 12:41:35 +01:00
|
|
|
break; \
|
2008-03-23 09:03:06 +01:00
|
|
|
default: __bad_percpu_size(); \
|
|
|
|
|
} \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2010-01-05 07:34:50 +01:00
|
|
|
/*
|
|
|
|
|
* Generate a percpu add to memory instruction and optimize code
|
2010-04-19 20:51:16 +02:00
|
|
|
* if one is added or subtracted.
|
2010-01-05 07:34:50 +01:00
|
|
|
*/
|
|
|
|
|
#define percpu_add_op(var, val) \
|
|
|
|
|
do { \
|
|
|
|
|
typedef typeof(var) pao_T__; \
|
|
|
|
|
const int pao_ID__ = (__builtin_constant_p(val) && \
|
|
|
|
|
((val) == 1 || (val) == -1)) ? (val) : 0; \
|
|
|
|
|
if (0) { \
|
|
|
|
|
pao_T__ pao_tmp__; \
|
|
|
|
|
pao_tmp__ = (val); \
|
2010-06-10 13:10:36 +02:00
|
|
|
(void)pao_tmp__; \
|
2010-01-05 07:34:50 +01:00
|
|
|
} \
|
|
|
|
|
switch (sizeof(var)) { \
|
|
|
|
|
case 1: \
|
|
|
|
|
if (pao_ID__ == 1) \
|
|
|
|
|
asm("incb "__percpu_arg(0) : "+m" (var)); \
|
|
|
|
|
else if (pao_ID__ == -1) \
|
|
|
|
|
asm("decb "__percpu_arg(0) : "+m" (var)); \
|
|
|
|
|
else \
|
|
|
|
|
asm("addb %1, "__percpu_arg(0) \
|
|
|
|
|
: "+m" (var) \
|
|
|
|
|
: "qi" ((pao_T__)(val))); \
|
|
|
|
|
break; \
|
|
|
|
|
case 2: \
|
|
|
|
|
if (pao_ID__ == 1) \
|
|
|
|
|
asm("incw "__percpu_arg(0) : "+m" (var)); \
|
|
|
|
|
else if (pao_ID__ == -1) \
|
|
|
|
|
asm("decw "__percpu_arg(0) : "+m" (var)); \
|
|
|
|
|
else \
|
|
|
|
|
asm("addw %1, "__percpu_arg(0) \
|
|
|
|
|
: "+m" (var) \
|
|
|
|
|
: "ri" ((pao_T__)(val))); \
|
|
|
|
|
break; \
|
|
|
|
|
case 4: \
|
|
|
|
|
if (pao_ID__ == 1) \
|
|
|
|
|
asm("incl "__percpu_arg(0) : "+m" (var)); \
|
|
|
|
|
else if (pao_ID__ == -1) \
|
|
|
|
|
asm("decl "__percpu_arg(0) : "+m" (var)); \
|
|
|
|
|
else \
|
|
|
|
|
asm("addl %1, "__percpu_arg(0) \
|
|
|
|
|
: "+m" (var) \
|
|
|
|
|
: "ri" ((pao_T__)(val))); \
|
|
|
|
|
break; \
|
|
|
|
|
case 8: \
|
|
|
|
|
if (pao_ID__ == 1) \
|
|
|
|
|
asm("incq "__percpu_arg(0) : "+m" (var)); \
|
|
|
|
|
else if (pao_ID__ == -1) \
|
|
|
|
|
asm("decq "__percpu_arg(0) : "+m" (var)); \
|
|
|
|
|
else \
|
|
|
|
|
asm("addq %1, "__percpu_arg(0) \
|
|
|
|
|
: "+m" (var) \
|
|
|
|
|
: "re" ((pao_T__)(val))); \
|
|
|
|
|
break; \
|
|
|
|
|
default: __bad_percpu_size(); \
|
|
|
|
|
} \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2009-08-03 07:08:48 +02:00
|
|
|
#define percpu_from_op(op, var, constraint) \
|
2008-03-23 09:03:06 +01:00
|
|
|
({ \
|
2009-10-29 14:34:12 +01:00
|
|
|
typeof(var) pfo_ret__; \
|
2008-03-23 09:03:06 +01:00
|
|
|
switch (sizeof(var)) { \
|
|
|
|
|
case 1: \
|
2009-01-18 16:38:59 +01:00
|
|
|
asm(op "b "__percpu_arg(1)",%0" \
|
2009-10-29 14:34:12 +01:00
|
|
|
: "=q" (pfo_ret__) \
|
2009-08-03 07:08:48 +02:00
|
|
|
: constraint); \
|
2008-03-23 09:03:06 +01:00
|
|
|
break; \
|
|
|
|
|
case 2: \
|
2009-01-18 16:38:59 +01:00
|
|
|
asm(op "w "__percpu_arg(1)",%0" \
|
2009-10-29 14:34:12 +01:00
|
|
|
: "=r" (pfo_ret__) \
|
2009-08-03 07:08:48 +02:00
|
|
|
: constraint); \
|
2008-03-23 09:03:06 +01:00
|
|
|
break; \
|
|
|
|
|
case 4: \
|
2009-01-18 16:38:59 +01:00
|
|
|
asm(op "l "__percpu_arg(1)",%0" \
|
2009-10-29 14:34:12 +01:00
|
|
|
: "=r" (pfo_ret__) \
|
2009-08-03 07:08:48 +02:00
|
|
|
: constraint); \
|
2009-01-13 12:41:35 +01:00
|
|
|
break; \
|
|
|
|
|
case 8: \
|
2009-01-18 16:38:59 +01:00
|
|
|
asm(op "q "__percpu_arg(1)",%0" \
|
2009-10-29 14:34:12 +01:00
|
|
|
: "=r" (pfo_ret__) \
|
2009-08-03 07:08:48 +02:00
|
|
|
: constraint); \
|
2008-03-23 09:03:06 +01:00
|
|
|
break; \
|
|
|
|
|
default: __bad_percpu_size(); \
|
|
|
|
|
} \
|
2009-10-29 14:34:12 +01:00
|
|
|
pfo_ret__; \
|
2008-03-23 09:03:06 +01:00
|
|
|
})
|
2008-01-30 13:32:53 +01:00
|
|
|
|
2010-04-21 16:21:51 +02:00
|
|
|
#define percpu_unary_op(op, var) \
|
|
|
|
|
({ \
|
|
|
|
|
switch (sizeof(var)) { \
|
|
|
|
|
case 1: \
|
|
|
|
|
asm(op "b "__percpu_arg(0) \
|
|
|
|
|
: "+m" (var)); \
|
|
|
|
|
break; \
|
|
|
|
|
case 2: \
|
|
|
|
|
asm(op "w "__percpu_arg(0) \
|
|
|
|
|
: "+m" (var)); \
|
|
|
|
|
break; \
|
|
|
|
|
case 4: \
|
|
|
|
|
asm(op "l "__percpu_arg(0) \
|
|
|
|
|
: "+m" (var)); \
|
|
|
|
|
break; \
|
|
|
|
|
case 8: \
|
|
|
|
|
asm(op "q "__percpu_arg(0) \
|
|
|
|
|
: "+m" (var)); \
|
|
|
|
|
break; \
|
|
|
|
|
default: __bad_percpu_size(); \
|
|
|
|
|
} \
|
|
|
|
|
})
|
|
|
|
|
|
2010-12-17 15:47:04 +01:00
|
|
|
/*
|
|
|
|
|
* Add return operation
|
|
|
|
|
*/
|
|
|
|
|
#define percpu_add_return_op(var, val) \
|
|
|
|
|
({ \
|
|
|
|
|
typeof(var) paro_ret__ = val; \
|
|
|
|
|
switch (sizeof(var)) { \
|
|
|
|
|
case 1: \
|
|
|
|
|
asm("xaddb %0, "__percpu_arg(1) \
|
|
|
|
|
: "+q" (paro_ret__), "+m" (var) \
|
|
|
|
|
: : "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
case 2: \
|
|
|
|
|
asm("xaddw %0, "__percpu_arg(1) \
|
|
|
|
|
: "+r" (paro_ret__), "+m" (var) \
|
|
|
|
|
: : "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
case 4: \
|
|
|
|
|
asm("xaddl %0, "__percpu_arg(1) \
|
|
|
|
|
: "+r" (paro_ret__), "+m" (var) \
|
|
|
|
|
: : "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
case 8: \
|
|
|
|
|
asm("xaddq %0, "__percpu_arg(1) \
|
|
|
|
|
: "+re" (paro_ret__), "+m" (var) \
|
|
|
|
|
: : "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
default: __bad_percpu_size(); \
|
|
|
|
|
} \
|
|
|
|
|
paro_ret__ += val; \
|
|
|
|
|
paro_ret__; \
|
|
|
|
|
})
|
|
|
|
|
|
2010-12-14 17:28:44 +01:00
|
|
|
/*
|
2010-12-14 17:28:47 +01:00
|
|
|
* xchg is implemented using cmpxchg without a lock prefix. xchg is
|
|
|
|
|
* expensive due to the implied lock prefix. The processor cannot prefetch
|
|
|
|
|
* cachelines if xchg is used.
|
2010-12-14 17:28:44 +01:00
|
|
|
*/
|
|
|
|
|
#define percpu_xchg_op(var, nval) \
|
|
|
|
|
({ \
|
|
|
|
|
typeof(var) pxo_ret__; \
|
|
|
|
|
typeof(var) pxo_new__ = (nval); \
|
|
|
|
|
switch (sizeof(var)) { \
|
|
|
|
|
case 1: \
|
percpu, x86: Fix percpu_xchg_op()
These recent percpu commits:
2485b6464cf8: x86,percpu: Move out of place 64 bit ops into X86_64 section
8270137a0d50: cpuops: Use cmpxchg for xchg to avoid lock semantics
Caused this 'perf top' crash:
Kernel panic - not syncing: Fatal exception in interrupt
Pid: 0, comm: swapper Tainted: G D
2.6.38-rc2-00181-gef71723 #413 Call Trace: <IRQ> [<ffffffff810465b5>]
? panic
? kmsg_dump
? kmsg_dump
? oops_end
? no_context
? __bad_area_nosemaphore
? perf_output_begin
? bad_area_nosemaphore
? do_page_fault
? __task_pid_nr_ns
? perf_event_tid
? __perf_event_header__init_id
? validate_chain
? perf_output_sample
? trace_hardirqs_off
? page_fault
? irq_work_run
? update_process_times
? tick_sched_timer
? tick_sched_timer
? __run_hrtimer
? hrtimer_interrupt
? account_system_vtime
? smp_apic_timer_interrupt
? apic_timer_interrupt
...
Looking at assembly code, I found:
list = this_cpu_xchg(irq_work_list, NULL);
gives this wrong code : (gcc-4.1.2 cross compiler)
ffffffff810bc45e:
mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne ffffffff810bc45e <irq_work_run+0x3e>
test %rax,%rax
je ffffffff810bc4aa <irq_work_run+0x8a>
Tell gcc we dirty eax/rax register in percpu_xchg_op()
Compiler must use another register to store pxo_new__
We also dont need to reload percpu value after a jump,
since a 'failed' cmpxchg already updated eax/rax
Wrong generated code was :
xor %rax,%rax /* load 0 into %rax */
1: mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne 1b
test %rax,%rax
After patch :
xor %rdx,%rdx /* load 0 into %rdx */
mov %gs:0xead0,%rax
1: cmpxchg %rdx,%gs:0xead0
jne 1b:
test %rax,%rax
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Christoph Lameter <cl@linux-foundation.org>
Cc: Tejun Heo <tj@kernel.org>
LKML-Reference: <1295973114.3588.312.camel@edumazet-laptop>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-01-25 17:31:54 +01:00
|
|
|
asm("\n\tmov "__percpu_arg(1)",%%al" \
|
|
|
|
|
"\n1:\tcmpxchgb %2, "__percpu_arg(1) \
|
2010-12-14 17:28:47 +01:00
|
|
|
"\n\tjnz 1b" \
|
percpu, x86: Fix percpu_xchg_op()
These recent percpu commits:
2485b6464cf8: x86,percpu: Move out of place 64 bit ops into X86_64 section
8270137a0d50: cpuops: Use cmpxchg for xchg to avoid lock semantics
Caused this 'perf top' crash:
Kernel panic - not syncing: Fatal exception in interrupt
Pid: 0, comm: swapper Tainted: G D
2.6.38-rc2-00181-gef71723 #413 Call Trace: <IRQ> [<ffffffff810465b5>]
? panic
? kmsg_dump
? kmsg_dump
? oops_end
? no_context
? __bad_area_nosemaphore
? perf_output_begin
? bad_area_nosemaphore
? do_page_fault
? __task_pid_nr_ns
? perf_event_tid
? __perf_event_header__init_id
? validate_chain
? perf_output_sample
? trace_hardirqs_off
? page_fault
? irq_work_run
? update_process_times
? tick_sched_timer
? tick_sched_timer
? __run_hrtimer
? hrtimer_interrupt
? account_system_vtime
? smp_apic_timer_interrupt
? apic_timer_interrupt
...
Looking at assembly code, I found:
list = this_cpu_xchg(irq_work_list, NULL);
gives this wrong code : (gcc-4.1.2 cross compiler)
ffffffff810bc45e:
mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne ffffffff810bc45e <irq_work_run+0x3e>
test %rax,%rax
je ffffffff810bc4aa <irq_work_run+0x8a>
Tell gcc we dirty eax/rax register in percpu_xchg_op()
Compiler must use another register to store pxo_new__
We also dont need to reload percpu value after a jump,
since a 'failed' cmpxchg already updated eax/rax
Wrong generated code was :
xor %rax,%rax /* load 0 into %rax */
1: mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne 1b
test %rax,%rax
After patch :
xor %rdx,%rdx /* load 0 into %rdx */
mov %gs:0xead0,%rax
1: cmpxchg %rdx,%gs:0xead0
jne 1b:
test %rax,%rax
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Christoph Lameter <cl@linux-foundation.org>
Cc: Tejun Heo <tj@kernel.org>
LKML-Reference: <1295973114.3588.312.camel@edumazet-laptop>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-01-25 17:31:54 +01:00
|
|
|
: "=&a" (pxo_ret__), "+m" (var) \
|
2010-12-14 17:28:44 +01:00
|
|
|
: "q" (pxo_new__) \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
case 2: \
|
percpu, x86: Fix percpu_xchg_op()
These recent percpu commits:
2485b6464cf8: x86,percpu: Move out of place 64 bit ops into X86_64 section
8270137a0d50: cpuops: Use cmpxchg for xchg to avoid lock semantics
Caused this 'perf top' crash:
Kernel panic - not syncing: Fatal exception in interrupt
Pid: 0, comm: swapper Tainted: G D
2.6.38-rc2-00181-gef71723 #413 Call Trace: <IRQ> [<ffffffff810465b5>]
? panic
? kmsg_dump
? kmsg_dump
? oops_end
? no_context
? __bad_area_nosemaphore
? perf_output_begin
? bad_area_nosemaphore
? do_page_fault
? __task_pid_nr_ns
? perf_event_tid
? __perf_event_header__init_id
? validate_chain
? perf_output_sample
? trace_hardirqs_off
? page_fault
? irq_work_run
? update_process_times
? tick_sched_timer
? tick_sched_timer
? __run_hrtimer
? hrtimer_interrupt
? account_system_vtime
? smp_apic_timer_interrupt
? apic_timer_interrupt
...
Looking at assembly code, I found:
list = this_cpu_xchg(irq_work_list, NULL);
gives this wrong code : (gcc-4.1.2 cross compiler)
ffffffff810bc45e:
mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne ffffffff810bc45e <irq_work_run+0x3e>
test %rax,%rax
je ffffffff810bc4aa <irq_work_run+0x8a>
Tell gcc we dirty eax/rax register in percpu_xchg_op()
Compiler must use another register to store pxo_new__
We also dont need to reload percpu value after a jump,
since a 'failed' cmpxchg already updated eax/rax
Wrong generated code was :
xor %rax,%rax /* load 0 into %rax */
1: mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne 1b
test %rax,%rax
After patch :
xor %rdx,%rdx /* load 0 into %rdx */
mov %gs:0xead0,%rax
1: cmpxchg %rdx,%gs:0xead0
jne 1b:
test %rax,%rax
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Christoph Lameter <cl@linux-foundation.org>
Cc: Tejun Heo <tj@kernel.org>
LKML-Reference: <1295973114.3588.312.camel@edumazet-laptop>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-01-25 17:31:54 +01:00
|
|
|
asm("\n\tmov "__percpu_arg(1)",%%ax" \
|
|
|
|
|
"\n1:\tcmpxchgw %2, "__percpu_arg(1) \
|
2010-12-14 17:28:47 +01:00
|
|
|
"\n\tjnz 1b" \
|
percpu, x86: Fix percpu_xchg_op()
These recent percpu commits:
2485b6464cf8: x86,percpu: Move out of place 64 bit ops into X86_64 section
8270137a0d50: cpuops: Use cmpxchg for xchg to avoid lock semantics
Caused this 'perf top' crash:
Kernel panic - not syncing: Fatal exception in interrupt
Pid: 0, comm: swapper Tainted: G D
2.6.38-rc2-00181-gef71723 #413 Call Trace: <IRQ> [<ffffffff810465b5>]
? panic
? kmsg_dump
? kmsg_dump
? oops_end
? no_context
? __bad_area_nosemaphore
? perf_output_begin
? bad_area_nosemaphore
? do_page_fault
? __task_pid_nr_ns
? perf_event_tid
? __perf_event_header__init_id
? validate_chain
? perf_output_sample
? trace_hardirqs_off
? page_fault
? irq_work_run
? update_process_times
? tick_sched_timer
? tick_sched_timer
? __run_hrtimer
? hrtimer_interrupt
? account_system_vtime
? smp_apic_timer_interrupt
? apic_timer_interrupt
...
Looking at assembly code, I found:
list = this_cpu_xchg(irq_work_list, NULL);
gives this wrong code : (gcc-4.1.2 cross compiler)
ffffffff810bc45e:
mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne ffffffff810bc45e <irq_work_run+0x3e>
test %rax,%rax
je ffffffff810bc4aa <irq_work_run+0x8a>
Tell gcc we dirty eax/rax register in percpu_xchg_op()
Compiler must use another register to store pxo_new__
We also dont need to reload percpu value after a jump,
since a 'failed' cmpxchg already updated eax/rax
Wrong generated code was :
xor %rax,%rax /* load 0 into %rax */
1: mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne 1b
test %rax,%rax
After patch :
xor %rdx,%rdx /* load 0 into %rdx */
mov %gs:0xead0,%rax
1: cmpxchg %rdx,%gs:0xead0
jne 1b:
test %rax,%rax
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Christoph Lameter <cl@linux-foundation.org>
Cc: Tejun Heo <tj@kernel.org>
LKML-Reference: <1295973114.3588.312.camel@edumazet-laptop>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-01-25 17:31:54 +01:00
|
|
|
: "=&a" (pxo_ret__), "+m" (var) \
|
2010-12-14 17:28:44 +01:00
|
|
|
: "r" (pxo_new__) \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
case 4: \
|
percpu, x86: Fix percpu_xchg_op()
These recent percpu commits:
2485b6464cf8: x86,percpu: Move out of place 64 bit ops into X86_64 section
8270137a0d50: cpuops: Use cmpxchg for xchg to avoid lock semantics
Caused this 'perf top' crash:
Kernel panic - not syncing: Fatal exception in interrupt
Pid: 0, comm: swapper Tainted: G D
2.6.38-rc2-00181-gef71723 #413 Call Trace: <IRQ> [<ffffffff810465b5>]
? panic
? kmsg_dump
? kmsg_dump
? oops_end
? no_context
? __bad_area_nosemaphore
? perf_output_begin
? bad_area_nosemaphore
? do_page_fault
? __task_pid_nr_ns
? perf_event_tid
? __perf_event_header__init_id
? validate_chain
? perf_output_sample
? trace_hardirqs_off
? page_fault
? irq_work_run
? update_process_times
? tick_sched_timer
? tick_sched_timer
? __run_hrtimer
? hrtimer_interrupt
? account_system_vtime
? smp_apic_timer_interrupt
? apic_timer_interrupt
...
Looking at assembly code, I found:
list = this_cpu_xchg(irq_work_list, NULL);
gives this wrong code : (gcc-4.1.2 cross compiler)
ffffffff810bc45e:
mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne ffffffff810bc45e <irq_work_run+0x3e>
test %rax,%rax
je ffffffff810bc4aa <irq_work_run+0x8a>
Tell gcc we dirty eax/rax register in percpu_xchg_op()
Compiler must use another register to store pxo_new__
We also dont need to reload percpu value after a jump,
since a 'failed' cmpxchg already updated eax/rax
Wrong generated code was :
xor %rax,%rax /* load 0 into %rax */
1: mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne 1b
test %rax,%rax
After patch :
xor %rdx,%rdx /* load 0 into %rdx */
mov %gs:0xead0,%rax
1: cmpxchg %rdx,%gs:0xead0
jne 1b:
test %rax,%rax
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Christoph Lameter <cl@linux-foundation.org>
Cc: Tejun Heo <tj@kernel.org>
LKML-Reference: <1295973114.3588.312.camel@edumazet-laptop>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-01-25 17:31:54 +01:00
|
|
|
asm("\n\tmov "__percpu_arg(1)",%%eax" \
|
|
|
|
|
"\n1:\tcmpxchgl %2, "__percpu_arg(1) \
|
2010-12-14 17:28:47 +01:00
|
|
|
"\n\tjnz 1b" \
|
percpu, x86: Fix percpu_xchg_op()
These recent percpu commits:
2485b6464cf8: x86,percpu: Move out of place 64 bit ops into X86_64 section
8270137a0d50: cpuops: Use cmpxchg for xchg to avoid lock semantics
Caused this 'perf top' crash:
Kernel panic - not syncing: Fatal exception in interrupt
Pid: 0, comm: swapper Tainted: G D
2.6.38-rc2-00181-gef71723 #413 Call Trace: <IRQ> [<ffffffff810465b5>]
? panic
? kmsg_dump
? kmsg_dump
? oops_end
? no_context
? __bad_area_nosemaphore
? perf_output_begin
? bad_area_nosemaphore
? do_page_fault
? __task_pid_nr_ns
? perf_event_tid
? __perf_event_header__init_id
? validate_chain
? perf_output_sample
? trace_hardirqs_off
? page_fault
? irq_work_run
? update_process_times
? tick_sched_timer
? tick_sched_timer
? __run_hrtimer
? hrtimer_interrupt
? account_system_vtime
? smp_apic_timer_interrupt
? apic_timer_interrupt
...
Looking at assembly code, I found:
list = this_cpu_xchg(irq_work_list, NULL);
gives this wrong code : (gcc-4.1.2 cross compiler)
ffffffff810bc45e:
mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne ffffffff810bc45e <irq_work_run+0x3e>
test %rax,%rax
je ffffffff810bc4aa <irq_work_run+0x8a>
Tell gcc we dirty eax/rax register in percpu_xchg_op()
Compiler must use another register to store pxo_new__
We also dont need to reload percpu value after a jump,
since a 'failed' cmpxchg already updated eax/rax
Wrong generated code was :
xor %rax,%rax /* load 0 into %rax */
1: mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne 1b
test %rax,%rax
After patch :
xor %rdx,%rdx /* load 0 into %rdx */
mov %gs:0xead0,%rax
1: cmpxchg %rdx,%gs:0xead0
jne 1b:
test %rax,%rax
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Christoph Lameter <cl@linux-foundation.org>
Cc: Tejun Heo <tj@kernel.org>
LKML-Reference: <1295973114.3588.312.camel@edumazet-laptop>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-01-25 17:31:54 +01:00
|
|
|
: "=&a" (pxo_ret__), "+m" (var) \
|
2010-12-14 17:28:44 +01:00
|
|
|
: "r" (pxo_new__) \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
case 8: \
|
percpu, x86: Fix percpu_xchg_op()
These recent percpu commits:
2485b6464cf8: x86,percpu: Move out of place 64 bit ops into X86_64 section
8270137a0d50: cpuops: Use cmpxchg for xchg to avoid lock semantics
Caused this 'perf top' crash:
Kernel panic - not syncing: Fatal exception in interrupt
Pid: 0, comm: swapper Tainted: G D
2.6.38-rc2-00181-gef71723 #413 Call Trace: <IRQ> [<ffffffff810465b5>]
? panic
? kmsg_dump
? kmsg_dump
? oops_end
? no_context
? __bad_area_nosemaphore
? perf_output_begin
? bad_area_nosemaphore
? do_page_fault
? __task_pid_nr_ns
? perf_event_tid
? __perf_event_header__init_id
? validate_chain
? perf_output_sample
? trace_hardirqs_off
? page_fault
? irq_work_run
? update_process_times
? tick_sched_timer
? tick_sched_timer
? __run_hrtimer
? hrtimer_interrupt
? account_system_vtime
? smp_apic_timer_interrupt
? apic_timer_interrupt
...
Looking at assembly code, I found:
list = this_cpu_xchg(irq_work_list, NULL);
gives this wrong code : (gcc-4.1.2 cross compiler)
ffffffff810bc45e:
mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne ffffffff810bc45e <irq_work_run+0x3e>
test %rax,%rax
je ffffffff810bc4aa <irq_work_run+0x8a>
Tell gcc we dirty eax/rax register in percpu_xchg_op()
Compiler must use another register to store pxo_new__
We also dont need to reload percpu value after a jump,
since a 'failed' cmpxchg already updated eax/rax
Wrong generated code was :
xor %rax,%rax /* load 0 into %rax */
1: mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne 1b
test %rax,%rax
After patch :
xor %rdx,%rdx /* load 0 into %rdx */
mov %gs:0xead0,%rax
1: cmpxchg %rdx,%gs:0xead0
jne 1b:
test %rax,%rax
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Christoph Lameter <cl@linux-foundation.org>
Cc: Tejun Heo <tj@kernel.org>
LKML-Reference: <1295973114.3588.312.camel@edumazet-laptop>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-01-25 17:31:54 +01:00
|
|
|
asm("\n\tmov "__percpu_arg(1)",%%rax" \
|
|
|
|
|
"\n1:\tcmpxchgq %2, "__percpu_arg(1) \
|
2010-12-14 17:28:47 +01:00
|
|
|
"\n\tjnz 1b" \
|
percpu, x86: Fix percpu_xchg_op()
These recent percpu commits:
2485b6464cf8: x86,percpu: Move out of place 64 bit ops into X86_64 section
8270137a0d50: cpuops: Use cmpxchg for xchg to avoid lock semantics
Caused this 'perf top' crash:
Kernel panic - not syncing: Fatal exception in interrupt
Pid: 0, comm: swapper Tainted: G D
2.6.38-rc2-00181-gef71723 #413 Call Trace: <IRQ> [<ffffffff810465b5>]
? panic
? kmsg_dump
? kmsg_dump
? oops_end
? no_context
? __bad_area_nosemaphore
? perf_output_begin
? bad_area_nosemaphore
? do_page_fault
? __task_pid_nr_ns
? perf_event_tid
? __perf_event_header__init_id
? validate_chain
? perf_output_sample
? trace_hardirqs_off
? page_fault
? irq_work_run
? update_process_times
? tick_sched_timer
? tick_sched_timer
? __run_hrtimer
? hrtimer_interrupt
? account_system_vtime
? smp_apic_timer_interrupt
? apic_timer_interrupt
...
Looking at assembly code, I found:
list = this_cpu_xchg(irq_work_list, NULL);
gives this wrong code : (gcc-4.1.2 cross compiler)
ffffffff810bc45e:
mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne ffffffff810bc45e <irq_work_run+0x3e>
test %rax,%rax
je ffffffff810bc4aa <irq_work_run+0x8a>
Tell gcc we dirty eax/rax register in percpu_xchg_op()
Compiler must use another register to store pxo_new__
We also dont need to reload percpu value after a jump,
since a 'failed' cmpxchg already updated eax/rax
Wrong generated code was :
xor %rax,%rax /* load 0 into %rax */
1: mov %gs:0xead0,%rax
cmpxchg %rax,%gs:0xead0
jne 1b
test %rax,%rax
After patch :
xor %rdx,%rdx /* load 0 into %rdx */
mov %gs:0xead0,%rax
1: cmpxchg %rdx,%gs:0xead0
jne 1b:
test %rax,%rax
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Christoph Lameter <cl@linux-foundation.org>
Cc: Tejun Heo <tj@kernel.org>
LKML-Reference: <1295973114.3588.312.camel@edumazet-laptop>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-01-25 17:31:54 +01:00
|
|
|
: "=&a" (pxo_ret__), "+m" (var) \
|
2010-12-14 17:28:44 +01:00
|
|
|
: "r" (pxo_new__) \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
default: __bad_percpu_size(); \
|
|
|
|
|
} \
|
|
|
|
|
pxo_ret__; \
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* cmpxchg has no such implied lock semantics as a result it is much
|
|
|
|
|
* more efficient for cpu local operations.
|
|
|
|
|
*/
|
|
|
|
|
#define percpu_cmpxchg_op(var, oval, nval) \
|
|
|
|
|
({ \
|
|
|
|
|
typeof(var) pco_ret__; \
|
|
|
|
|
typeof(var) pco_old__ = (oval); \
|
|
|
|
|
typeof(var) pco_new__ = (nval); \
|
|
|
|
|
switch (sizeof(var)) { \
|
|
|
|
|
case 1: \
|
|
|
|
|
asm("cmpxchgb %2, "__percpu_arg(1) \
|
|
|
|
|
: "=a" (pco_ret__), "+m" (var) \
|
|
|
|
|
: "q" (pco_new__), "0" (pco_old__) \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
case 2: \
|
|
|
|
|
asm("cmpxchgw %2, "__percpu_arg(1) \
|
|
|
|
|
: "=a" (pco_ret__), "+m" (var) \
|
|
|
|
|
: "r" (pco_new__), "0" (pco_old__) \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
case 4: \
|
|
|
|
|
asm("cmpxchgl %2, "__percpu_arg(1) \
|
|
|
|
|
: "=a" (pco_ret__), "+m" (var) \
|
|
|
|
|
: "r" (pco_new__), "0" (pco_old__) \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
case 8: \
|
|
|
|
|
asm("cmpxchgq %2, "__percpu_arg(1) \
|
|
|
|
|
: "=a" (pco_ret__), "+m" (var) \
|
|
|
|
|
: "r" (pco_new__), "0" (pco_old__) \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
break; \
|
|
|
|
|
default: __bad_percpu_size(); \
|
|
|
|
|
} \
|
|
|
|
|
pco_ret__; \
|
|
|
|
|
})
|
|
|
|
|
|
2009-08-03 07:08:48 +02:00
|
|
|
/*
|
|
|
|
|
* percpu_read() makes gcc load the percpu variable every time it is
|
|
|
|
|
* accessed while percpu_read_stable() allows the value to be cached.
|
|
|
|
|
* percpu_read_stable() is more efficient and can be used if its value
|
|
|
|
|
* is guaranteed to be valid across cpus. The current users include
|
|
|
|
|
* get_current() and get_thread_info() both of which are actually
|
|
|
|
|
* per-thread variables implemented as per-cpu variables and thus
|
|
|
|
|
* stable for the duration of the respective task.
|
|
|
|
|
*/
|
2009-10-29 14:34:15 +01:00
|
|
|
#define percpu_read(var) percpu_from_op("mov", var, "m" (var))
|
|
|
|
|
#define percpu_read_stable(var) percpu_from_op("mov", var, "p" (&(var)))
|
|
|
|
|
#define percpu_write(var, val) percpu_to_op("mov", var, val)
|
2010-01-05 07:34:50 +01:00
|
|
|
#define percpu_add(var, val) percpu_add_op(var, val)
|
|
|
|
|
#define percpu_sub(var, val) percpu_add_op(var, -(val))
|
2009-10-29 14:34:15 +01:00
|
|
|
#define percpu_and(var, val) percpu_to_op("and", var, val)
|
|
|
|
|
#define percpu_or(var, val) percpu_to_op("or", var, val)
|
|
|
|
|
#define percpu_xor(var, val) percpu_to_op("xor", var, val)
|
2010-04-21 16:21:51 +02:00
|
|
|
#define percpu_inc(var) percpu_unary_op("inc", var)
|
2009-01-13 12:41:35 +01:00
|
|
|
|
2009-10-03 12:48:22 +02:00
|
|
|
#define __this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
|
|
|
|
|
#define __this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
|
|
|
|
|
#define __this_cpu_read_4(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
|
|
|
|
|
|
|
|
|
|
#define __this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val)
|
|
|
|
|
#define __this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val)
|
|
|
|
|
#define __this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val)
|
2010-01-05 07:34:50 +01:00
|
|
|
#define __this_cpu_add_1(pcp, val) percpu_add_op((pcp), val)
|
|
|
|
|
#define __this_cpu_add_2(pcp, val) percpu_add_op((pcp), val)
|
|
|
|
|
#define __this_cpu_add_4(pcp, val) percpu_add_op((pcp), val)
|
2009-10-03 12:48:22 +02:00
|
|
|
#define __this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define __this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define __this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define __this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define __this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define __this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define __this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val)
|
|
|
|
|
#define __this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val)
|
|
|
|
|
#define __this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val)
|
2010-12-14 17:28:44 +01:00
|
|
|
/*
|
|
|
|
|
* Generic fallback operations for __this_cpu_xchg_[1-4] are okay and much
|
|
|
|
|
* faster than an xchg with forced lock semantics.
|
|
|
|
|
*/
|
|
|
|
|
#define __this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval)
|
|
|
|
|
#define __this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
2009-10-03 12:48:22 +02:00
|
|
|
|
|
|
|
|
#define this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
|
|
|
|
|
#define this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
|
|
|
|
|
#define this_cpu_read_4(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
|
|
|
|
|
#define this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val)
|
|
|
|
|
#define this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val)
|
|
|
|
|
#define this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val)
|
2010-01-05 07:34:50 +01:00
|
|
|
#define this_cpu_add_1(pcp, val) percpu_add_op((pcp), val)
|
|
|
|
|
#define this_cpu_add_2(pcp, val) percpu_add_op((pcp), val)
|
|
|
|
|
#define this_cpu_add_4(pcp, val) percpu_add_op((pcp), val)
|
2009-10-03 12:48:22 +02:00
|
|
|
#define this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val)
|
|
|
|
|
#define this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val)
|
|
|
|
|
#define this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val)
|
2010-12-14 17:28:44 +01:00
|
|
|
#define this_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval)
|
|
|
|
|
#define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval)
|
|
|
|
|
#define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval)
|
2009-10-03 12:48:22 +02:00
|
|
|
|
2010-01-05 07:34:50 +01:00
|
|
|
#define irqsafe_cpu_add_1(pcp, val) percpu_add_op((pcp), val)
|
|
|
|
|
#define irqsafe_cpu_add_2(pcp, val) percpu_add_op((pcp), val)
|
|
|
|
|
#define irqsafe_cpu_add_4(pcp, val) percpu_add_op((pcp), val)
|
2009-10-03 12:48:22 +02:00
|
|
|
#define irqsafe_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define irqsafe_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define irqsafe_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define irqsafe_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define irqsafe_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define irqsafe_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define irqsafe_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val)
|
|
|
|
|
#define irqsafe_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val)
|
|
|
|
|
#define irqsafe_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val)
|
2010-12-14 17:28:44 +01:00
|
|
|
#define irqsafe_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval)
|
|
|
|
|
#define irqsafe_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval)
|
|
|
|
|
#define irqsafe_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval)
|
2009-10-03 12:48:22 +02:00
|
|
|
|
2010-12-06 18:40:00 +01:00
|
|
|
#ifndef CONFIG_M386
|
|
|
|
|
#define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
|
|
|
|
|
#define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
|
|
|
|
|
#define __this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
|
2010-12-14 17:28:44 +01:00
|
|
|
#define __this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
|
|
|
|
#define __this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
|
|
|
|
#define __this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
|
|
|
|
|
2010-12-06 18:40:00 +01:00
|
|
|
#define this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
|
|
|
|
|
#define this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
|
|
|
|
|
#define this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
|
2010-12-14 17:28:44 +01:00
|
|
|
#define this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
|
|
|
|
#define this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
|
|
|
|
#define this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
|
|
|
|
|
|
|
|
|
#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
|
|
|
|
#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
|
|
|
|
#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
|
|
|
|
#endif /* !CONFIG_M386 */
|
|
|
|
|
|
2011-02-28 11:02:24 +01:00
|
|
|
#ifdef CONFIG_X86_CMPXCHG64
|
|
|
|
|
#define percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) \
|
|
|
|
|
({ \
|
|
|
|
|
char __ret; \
|
|
|
|
|
typeof(o1) __o1 = o1; \
|
|
|
|
|
typeof(o1) __n1 = n1; \
|
|
|
|
|
typeof(o2) __o2 = o2; \
|
|
|
|
|
typeof(o2) __n2 = n2; \
|
|
|
|
|
typeof(o2) __dummy = n2; \
|
|
|
|
|
asm volatile("cmpxchg8b "__percpu_arg(1)"\n\tsetz %0\n\t" \
|
|
|
|
|
: "=a"(__ret), "=m" (pcp1), "=d"(__dummy) \
|
|
|
|
|
: "b"(__n1), "c"(__n2), "a"(__o1), "d"(__o2)); \
|
|
|
|
|
__ret; \
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
#define __this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2)
|
|
|
|
|
#define this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2)
|
|
|
|
|
#define irqsafe_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2)
|
|
|
|
|
#endif /* CONFIG_X86_CMPXCHG64 */
|
|
|
|
|
|
2009-10-03 12:48:22 +02:00
|
|
|
/*
|
|
|
|
|
* Per cpu atomic 64 bit operations are only available under 64 bit.
|
|
|
|
|
* 32 bit must fall back to generic operations.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
|
#define __this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
|
|
|
|
|
#define __this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val)
|
2010-01-05 07:34:50 +01:00
|
|
|
#define __this_cpu_add_8(pcp, val) percpu_add_op((pcp), val)
|
2009-10-03 12:48:22 +02:00
|
|
|
#define __this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define __this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define __this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val)
|
2010-12-17 15:47:04 +01:00
|
|
|
#define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
|
2009-10-03 12:48:22 +02:00
|
|
|
|
|
|
|
|
#define this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
|
|
|
|
|
#define this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val)
|
2010-01-05 07:34:50 +01:00
|
|
|
#define this_cpu_add_8(pcp, val) percpu_add_op((pcp), val)
|
2009-10-03 12:48:22 +02:00
|
|
|
#define this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val)
|
2010-12-17 15:47:04 +01:00
|
|
|
#define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
|
2011-01-11 18:54:53 +01:00
|
|
|
#define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval)
|
|
|
|
|
#define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
2009-10-03 12:48:22 +02:00
|
|
|
|
2010-01-05 07:34:50 +01:00
|
|
|
#define irqsafe_cpu_add_8(pcp, val) percpu_add_op((pcp), val)
|
2009-10-03 12:48:22 +02:00
|
|
|
#define irqsafe_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val)
|
|
|
|
|
#define irqsafe_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val)
|
|
|
|
|
#define irqsafe_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val)
|
2011-01-11 18:54:53 +01:00
|
|
|
#define irqsafe_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval)
|
|
|
|
|
#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
|
2011-02-28 11:02:24 +01:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Pretty complex macro to generate cmpxchg16 instruction. The instruction
|
|
|
|
|
* is not supported on early AMD64 processors so we must be able to emulate
|
|
|
|
|
* it in software. The address used in the cmpxchg16 instruction must be
|
|
|
|
|
* aligned to a 16 byte boundary.
|
|
|
|
|
*/
|
2011-03-28 18:06:58 +02:00
|
|
|
#ifdef CONFIG_SMP
|
2011-05-24 20:53:42 +02:00
|
|
|
#define CMPXCHG16B_EMU_CALL "call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP3
|
2011-03-28 18:06:58 +02:00
|
|
|
#else
|
2011-05-24 20:53:42 +02:00
|
|
|
#define CMPXCHG16B_EMU_CALL "call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP2
|
2011-03-28 18:06:58 +02:00
|
|
|
#endif
|
2011-02-28 11:02:24 +01:00
|
|
|
#define percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) \
|
|
|
|
|
({ \
|
|
|
|
|
char __ret; \
|
|
|
|
|
typeof(o1) __o1 = o1; \
|
|
|
|
|
typeof(o1) __n1 = n1; \
|
|
|
|
|
typeof(o2) __o2 = o2; \
|
|
|
|
|
typeof(o2) __n2 = n2; \
|
|
|
|
|
typeof(o2) __dummy; \
|
2011-03-28 18:06:58 +02:00
|
|
|
alternative_io(CMPXCHG16B_EMU_CALL, \
|
2011-03-27 03:57:18 +02:00
|
|
|
"cmpxchg16b " __percpu_prefix "(%%rsi)\n\tsetz %0\n\t", \
|
2011-02-28 11:02:24 +01:00
|
|
|
X86_FEATURE_CX16, \
|
|
|
|
|
ASM_OUTPUT2("=a"(__ret), "=d"(__dummy)), \
|
|
|
|
|
"S" (&pcp1), "b"(__n1), "c"(__n2), \
|
2011-03-27 03:57:18 +02:00
|
|
|
"a"(__o1), "d"(__o2) : "memory"); \
|
2011-02-28 11:02:24 +01:00
|
|
|
__ret; \
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
#define __this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)
|
|
|
|
|
#define this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)
|
|
|
|
|
#define irqsafe_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)
|
|
|
|
|
|
2009-10-03 12:48:22 +02:00
|
|
|
#endif
|
|
|
|
|
|
2009-01-13 12:41:35 +01:00
|
|
|
/* This is not atomic against other CPUs -- CPU preemption needs to be off */
|
|
|
|
|
#define x86_test_and_clear_bit_percpu(bit, var) \
|
|
|
|
|
({ \
|
|
|
|
|
int old__; \
|
2009-01-18 16:38:59 +01:00
|
|
|
asm volatile("btr %2,"__percpu_arg(1)"\n\tsbbl %0,%0" \
|
2009-10-29 14:34:15 +01:00
|
|
|
: "=r" (old__), "+m" (var) \
|
2009-01-18 16:38:59 +01:00
|
|
|
: "dIr" (bit)); \
|
2009-01-13 12:41:35 +01:00
|
|
|
old__; \
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-12 12:50:10 +01:00
|
|
|
static __always_inline int x86_this_cpu_constant_test_bit(unsigned int nr,
|
|
|
|
|
const unsigned long __percpu *addr)
|
|
|
|
|
{
|
|
|
|
|
unsigned long __percpu *a = (unsigned long *)addr + nr / BITS_PER_LONG;
|
|
|
|
|
|
|
|
|
|
return ((1UL << (nr % BITS_PER_LONG)) & percpu_read(*a)) != 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int x86_this_cpu_variable_test_bit(int nr,
|
|
|
|
|
const unsigned long __percpu *addr)
|
|
|
|
|
{
|
|
|
|
|
int oldbit;
|
|
|
|
|
|
|
|
|
|
asm volatile("bt "__percpu_arg(2)",%1\n\t"
|
|
|
|
|
"sbb %0,%0"
|
|
|
|
|
: "=r" (oldbit)
|
|
|
|
|
: "m" (*(unsigned long *)addr), "Ir" (nr));
|
|
|
|
|
|
|
|
|
|
return oldbit;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define x86_this_cpu_test_bit(nr, addr) \
|
|
|
|
|
(__builtin_constant_p((nr)) \
|
|
|
|
|
? x86_this_cpu_constant_test_bit((nr), (addr)) \
|
|
|
|
|
: x86_this_cpu_variable_test_bit((nr), (addr)))
|
|
|
|
|
|
|
|
|
|
|
percpu: add optimized generic percpu accessors
It is an optimization and a cleanup, and adds the following new
generic percpu methods:
percpu_read()
percpu_write()
percpu_add()
percpu_sub()
percpu_and()
percpu_or()
percpu_xor()
and implements support for them on x86. (other architectures will fall
back to a default implementation)
The advantage is that for example to read a local percpu variable,
instead of this sequence:
return __get_cpu_var(var);
ffffffff8102ca2b: 48 8b 14 fd 80 09 74 mov -0x7e8bf680(,%rdi,8),%rdx
ffffffff8102ca32: 81
ffffffff8102ca33: 48 c7 c0 d8 59 00 00 mov $0x59d8,%rax
ffffffff8102ca3a: 48 8b 04 10 mov (%rax,%rdx,1),%rax
We can get a single instruction by using the optimized variants:
return percpu_read(var);
ffffffff8102ca3f: 65 48 8b 05 91 8f fd mov %gs:0x7efd8f91(%rip),%rax
I also cleaned up the x86-specific APIs and made the x86 code use
these new generic percpu primitives.
tj: * fixed generic percpu_sub() definition as Roel Kluin pointed out
* added percpu_and() for completeness's sake
* made generic percpu ops atomic against preemption
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Tejun Heo <tj@kernel.org>
2009-01-15 14:15:53 +01:00
|
|
|
#include <asm-generic/percpu.h>
|
|
|
|
|
|
|
|
|
|
/* We can use this directly for local CPU (faster). */
|
|
|
|
|
DECLARE_PER_CPU(unsigned long, this_cpu_off);
|
|
|
|
|
|
2008-01-30 13:32:53 +01:00
|
|
|
#endif /* !__ASSEMBLY__ */
|
x86: cleanup early per cpu variables/accesses v4
* Introduce a new PER_CPU macro called "EARLY_PER_CPU". This is
used by some per_cpu variables that are initialized and accessed
before there are per_cpu areas allocated.
["Early" in respect to per_cpu variables is "earlier than the per_cpu
areas have been setup".]
This patchset adds these new macros:
DEFINE_EARLY_PER_CPU(_type, _name, _initvalue)
EXPORT_EARLY_PER_CPU_SYMBOL(_name)
DECLARE_EARLY_PER_CPU(_type, _name)
early_per_cpu_ptr(_name)
early_per_cpu_map(_name, _idx)
early_per_cpu(_name, _cpu)
The DEFINE macro defines the per_cpu variable as well as the early
map and pointer. It also initializes the per_cpu variable and map
elements to "_initvalue". The early_* macros provide access to
the initial map (usually setup during system init) and the early
pointer. This pointer is initialized to point to the early map
but is then NULL'ed when the actual per_cpu areas are setup. After
that the per_cpu variable is the correct access to the variable.
The early_per_cpu() macro is not very efficient but does show how to
access the variable if you have a function that can be called both
"early" and "late". It tests the early ptr to be NULL, and if not
then it's still valid. Otherwise, the per_cpu variable is used
instead:
#define early_per_cpu(_name, _cpu) \
(early_per_cpu_ptr(_name) ? \
early_per_cpu_ptr(_name)[_cpu] : \
per_cpu(_name, _cpu))
A better method is to actually check the pointer manually. In the
case below, numa_set_node can be called both "early" and "late":
void __cpuinit numa_set_node(int cpu, int node)
{
int *cpu_to_node_map = early_per_cpu_ptr(x86_cpu_to_node_map);
if (cpu_to_node_map)
cpu_to_node_map[cpu] = node;
else
per_cpu(x86_cpu_to_node_map, cpu) = node;
}
* Add a flag "arch_provides_topology_pointers" that indicates pointers
to topology cpumask_t maps are available. Otherwise, use the function
returning the cpumask_t value. This is useful if cpumask_t set size
is very large to avoid copying data on to/off of the stack.
* The coverage of CONFIG_DEBUG_PER_CPU_MAPS has been increased while
the non-debug case has been optimized a bit.
* Remove an unreferenced compiler warning in drivers/base/topology.c
* Clean up #ifdef in setup.c
For inclusion into sched-devel/latest tree.
Based on:
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ sched-devel/latest .../mingo/linux-2.6-sched-devel.git
Signed-off-by: Mike Travis <travis@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-12 21:21:12 +02:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Define the "EARLY_PER_CPU" macros. These are used for some per_cpu
|
|
|
|
|
* variables that are initialized and accessed before there are per_cpu
|
|
|
|
|
* areas allocated.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \
|
|
|
|
|
DEFINE_PER_CPU(_type, _name) = _initvalue; \
|
|
|
|
|
__typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \
|
|
|
|
|
{ [0 ... NR_CPUS-1] = _initvalue }; \
|
x86, percpu: silence section mismatch warnings related to EARLY_PER_CPU variables
Quoting Mike Travis in "x86: cleanup early per cpu variables/accesses v4"
(23ca4bba3e20c6c3cb11c1bb0ab4770b724d39ac):
The DEFINE macro defines the per_cpu variable as well as the early
map and pointer. It also initializes the per_cpu variable and map
elements to "_initvalue". The early_* macros provide access to
the initial map (usually setup during system init) and the early
pointer. This pointer is initialized to point to the early map
but is then NULL'ed when the actual per_cpu areas are setup. After
that the per_cpu variable is the correct access to the variable.
As these variables are NULL'ed before __init sections are dropped
(in setup_per_cpu_maps), they can be safely annotated as __ref.
This change silences following section mismatch warnings:
WARNING: vmlinux.o(.data+0x46c0): Section mismatch in reference from the variable x86_cpu_to_apicid_early_ptr to the variable .init.data:x86_cpu_to_apicid_early_map
The variable x86_cpu_to_apicid_early_ptr references
the variable __initdata x86_cpu_to_apicid_early_map
If the reference is valid then annotate the
variable with __init* (see linux/init.h) or name the variable:
*driver, *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
WARNING: vmlinux.o(.data+0x46c8): Section mismatch in reference from the variable x86_bios_cpu_apicid_early_ptr to the variable .init.data:x86_bios_cpu_apicid_early_map
The variable x86_bios_cpu_apicid_early_ptr references
the variable __initdata x86_bios_cpu_apicid_early_map
If the reference is valid then annotate the
variable with __init* (see linux/init.h) or name the variable:
*driver, *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
WARNING: vmlinux.o(.data+0x46d0): Section mismatch in reference from the variable x86_cpu_to_node_map_early_ptr to the variable .init.data:x86_cpu_to_node_map_early_map
The variable x86_cpu_to_node_map_early_ptr references
the variable __initdata x86_cpu_to_node_map_early_map
If the reference is valid then annotate the
variable with __init* (see linux/init.h) or name the variable:
*driver, *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
Cc: Mike Travis <travis@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-08-17 17:50:50 +02:00
|
|
|
__typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
|
x86: cleanup early per cpu variables/accesses v4
* Introduce a new PER_CPU macro called "EARLY_PER_CPU". This is
used by some per_cpu variables that are initialized and accessed
before there are per_cpu areas allocated.
["Early" in respect to per_cpu variables is "earlier than the per_cpu
areas have been setup".]
This patchset adds these new macros:
DEFINE_EARLY_PER_CPU(_type, _name, _initvalue)
EXPORT_EARLY_PER_CPU_SYMBOL(_name)
DECLARE_EARLY_PER_CPU(_type, _name)
early_per_cpu_ptr(_name)
early_per_cpu_map(_name, _idx)
early_per_cpu(_name, _cpu)
The DEFINE macro defines the per_cpu variable as well as the early
map and pointer. It also initializes the per_cpu variable and map
elements to "_initvalue". The early_* macros provide access to
the initial map (usually setup during system init) and the early
pointer. This pointer is initialized to point to the early map
but is then NULL'ed when the actual per_cpu areas are setup. After
that the per_cpu variable is the correct access to the variable.
The early_per_cpu() macro is not very efficient but does show how to
access the variable if you have a function that can be called both
"early" and "late". It tests the early ptr to be NULL, and if not
then it's still valid. Otherwise, the per_cpu variable is used
instead:
#define early_per_cpu(_name, _cpu) \
(early_per_cpu_ptr(_name) ? \
early_per_cpu_ptr(_name)[_cpu] : \
per_cpu(_name, _cpu))
A better method is to actually check the pointer manually. In the
case below, numa_set_node can be called both "early" and "late":
void __cpuinit numa_set_node(int cpu, int node)
{
int *cpu_to_node_map = early_per_cpu_ptr(x86_cpu_to_node_map);
if (cpu_to_node_map)
cpu_to_node_map[cpu] = node;
else
per_cpu(x86_cpu_to_node_map, cpu) = node;
}
* Add a flag "arch_provides_topology_pointers" that indicates pointers
to topology cpumask_t maps are available. Otherwise, use the function
returning the cpumask_t value. This is useful if cpumask_t set size
is very large to avoid copying data on to/off of the stack.
* The coverage of CONFIG_DEBUG_PER_CPU_MAPS has been increased while
the non-debug case has been optimized a bit.
* Remove an unreferenced compiler warning in drivers/base/topology.c
* Clean up #ifdef in setup.c
For inclusion into sched-devel/latest tree.
Based on:
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ sched-devel/latest .../mingo/linux-2.6-sched-devel.git
Signed-off-by: Mike Travis <travis@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-12 21:21:12 +02:00
|
|
|
|
|
|
|
|
#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \
|
|
|
|
|
EXPORT_PER_CPU_SYMBOL(_name)
|
|
|
|
|
|
|
|
|
|
#define DECLARE_EARLY_PER_CPU(_type, _name) \
|
|
|
|
|
DECLARE_PER_CPU(_type, _name); \
|
|
|
|
|
extern __typeof__(_type) *_name##_early_ptr; \
|
|
|
|
|
extern __typeof__(_type) _name##_early_map[]
|
|
|
|
|
|
|
|
|
|
#define early_per_cpu_ptr(_name) (_name##_early_ptr)
|
|
|
|
|
#define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx])
|
|
|
|
|
#define early_per_cpu(_name, _cpu) \
|
2009-01-13 12:41:34 +01:00
|
|
|
*(early_per_cpu_ptr(_name) ? \
|
|
|
|
|
&early_per_cpu_ptr(_name)[_cpu] : \
|
|
|
|
|
&per_cpu(_name, _cpu))
|
x86: cleanup early per cpu variables/accesses v4
* Introduce a new PER_CPU macro called "EARLY_PER_CPU". This is
used by some per_cpu variables that are initialized and accessed
before there are per_cpu areas allocated.
["Early" in respect to per_cpu variables is "earlier than the per_cpu
areas have been setup".]
This patchset adds these new macros:
DEFINE_EARLY_PER_CPU(_type, _name, _initvalue)
EXPORT_EARLY_PER_CPU_SYMBOL(_name)
DECLARE_EARLY_PER_CPU(_type, _name)
early_per_cpu_ptr(_name)
early_per_cpu_map(_name, _idx)
early_per_cpu(_name, _cpu)
The DEFINE macro defines the per_cpu variable as well as the early
map and pointer. It also initializes the per_cpu variable and map
elements to "_initvalue". The early_* macros provide access to
the initial map (usually setup during system init) and the early
pointer. This pointer is initialized to point to the early map
but is then NULL'ed when the actual per_cpu areas are setup. After
that the per_cpu variable is the correct access to the variable.
The early_per_cpu() macro is not very efficient but does show how to
access the variable if you have a function that can be called both
"early" and "late". It tests the early ptr to be NULL, and if not
then it's still valid. Otherwise, the per_cpu variable is used
instead:
#define early_per_cpu(_name, _cpu) \
(early_per_cpu_ptr(_name) ? \
early_per_cpu_ptr(_name)[_cpu] : \
per_cpu(_name, _cpu))
A better method is to actually check the pointer manually. In the
case below, numa_set_node can be called both "early" and "late":
void __cpuinit numa_set_node(int cpu, int node)
{
int *cpu_to_node_map = early_per_cpu_ptr(x86_cpu_to_node_map);
if (cpu_to_node_map)
cpu_to_node_map[cpu] = node;
else
per_cpu(x86_cpu_to_node_map, cpu) = node;
}
* Add a flag "arch_provides_topology_pointers" that indicates pointers
to topology cpumask_t maps are available. Otherwise, use the function
returning the cpumask_t value. This is useful if cpumask_t set size
is very large to avoid copying data on to/off of the stack.
* The coverage of CONFIG_DEBUG_PER_CPU_MAPS has been increased while
the non-debug case has been optimized a bit.
* Remove an unreferenced compiler warning in drivers/base/topology.c
* Clean up #ifdef in setup.c
For inclusion into sched-devel/latest tree.
Based on:
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ sched-devel/latest .../mingo/linux-2.6-sched-devel.git
Signed-off-by: Mike Travis <travis@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-12 21:21:12 +02:00
|
|
|
|
|
|
|
|
#else /* !CONFIG_SMP */
|
|
|
|
|
#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \
|
|
|
|
|
DEFINE_PER_CPU(_type, _name) = _initvalue
|
|
|
|
|
|
|
|
|
|
#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \
|
|
|
|
|
EXPORT_PER_CPU_SYMBOL(_name)
|
|
|
|
|
|
|
|
|
|
#define DECLARE_EARLY_PER_CPU(_type, _name) \
|
|
|
|
|
DECLARE_PER_CPU(_type, _name)
|
|
|
|
|
|
|
|
|
|
#define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu)
|
|
|
|
|
#define early_per_cpu_ptr(_name) NULL
|
|
|
|
|
/* no early_per_cpu_map() */
|
|
|
|
|
|
|
|
|
|
#endif /* !CONFIG_SMP */
|
|
|
|
|
|
2008-10-23 07:26:29 +02:00
|
|
|
#endif /* _ASM_X86_PERCPU_H */
|