2005-04-17 00:20:36 +02:00
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/*
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* sata_promise.c - Promise SATA
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003-2004 Red Hat, Inc.
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*
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*
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2005-08-29 02:18:39 +02:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware information only available under NDA.
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2005-04-17 00:20:36 +02:00
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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2005-10-30 20:39:11 +01:00
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#include <linux/device.h>
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2005-04-17 00:20:36 +02:00
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#include <scsi/scsi_host.h>
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2005-11-07 06:59:37 +01:00
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#include <scsi/scsi_cmnd.h>
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2005-04-17 00:20:36 +02:00
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#include <linux/libata.h>
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#include <asm/io.h>
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#include "sata_promise.h"
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#define DRV_NAME "sata_promise"
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2006-01-28 18:39:29 +01:00
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#define DRV_VERSION "1.04"
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2005-04-17 00:20:36 +02:00
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enum {
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PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
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PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
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PDC_TBG_MODE = 0x41, /* TBG mode */
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PDC_FLASH_CTL = 0x44, /* Flash control register */
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PDC_PCI_CTL = 0x48, /* PCI control and status register */
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PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
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PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
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PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
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2006-01-28 18:39:29 +01:00
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PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
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2005-04-17 00:20:36 +02:00
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PDC_SLEW_CTL = 0x470, /* slew rate control reg */
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PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
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(1<<8) | (1<<9) | (1<<10),
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board_2037x = 0, /* FastTrak S150 TX2plus */
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board_20319 = 1, /* FastTrak S150 TX4 */
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2005-05-12 21:51:01 +02:00
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board_20619 = 2, /* FastTrak TX4000 */
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2006-01-17 14:06:21 +01:00
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board_20771 = 3, /* FastTrak TX2300 */
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2006-01-28 18:39:29 +01:00
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board_2057x = 4, /* SATAII150 Tx2plus */
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board_40518 = 5, /* SATAII150 Tx4 */
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2005-04-17 00:20:36 +02:00
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2006-01-28 18:39:29 +01:00
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PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
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2005-04-17 00:20:36 +02:00
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PDC_RESET = (1 << 11), /* HDMA reset */
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2005-12-14 04:28:19 +01:00
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PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
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ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
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ATA_FLAG_PIO_POLLING,
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2005-04-17 00:20:36 +02:00
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};
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struct pdc_port_priv {
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u8 *pkt;
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dma_addr_t pkt_dma;
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};
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2006-01-28 18:39:29 +01:00
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struct pdc_host_priv {
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int hotplug_offset;
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};
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2005-04-17 00:20:36 +02:00
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static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
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static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
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static void pdc_eng_timeout(struct ata_port *ap);
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static int pdc_port_start(struct ata_port *ap);
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static void pdc_port_stop(struct ata_port *ap);
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2005-08-29 11:12:30 +02:00
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static void pdc_pata_phy_reset(struct ata_port *ap);
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static void pdc_sata_phy_reset(struct ata_port *ap);
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2005-04-17 00:20:36 +02:00
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static void pdc_qc_prep(struct ata_queued_cmd *qc);
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2005-10-22 20:27:05 +02:00
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static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
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static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
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2005-04-17 00:20:36 +02:00
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static void pdc_irq_clear(struct ata_port *ap);
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2006-01-23 05:09:36 +01:00
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static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
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2006-01-28 18:39:29 +01:00
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static void pdc_host_stop(struct ata_host_set *host_set);
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2005-04-17 00:20:36 +02:00
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2005-08-30 11:42:52 +02:00
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2005-11-07 06:59:37 +01:00
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static struct scsi_host_template pdc_ata_sht = {
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2005-04-17 00:20:36 +02:00
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.eh_strategy_handler = ata_scsi_error,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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};
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2005-10-22 20:27:05 +02:00
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static const struct ata_port_operations pdc_sata_ops = {
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2005-04-17 00:20:36 +02:00
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.port_disable = ata_port_disable,
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.tf_load = pdc_tf_load_mmio,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = pdc_exec_command_mmio,
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.dev_select = ata_std_dev_select,
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2005-08-29 11:12:30 +02:00
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.phy_reset = pdc_sata_phy_reset,
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2005-04-17 00:20:36 +02:00
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.qc_prep = pdc_qc_prep,
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.qc_issue = pdc_qc_issue_prot,
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.eng_timeout = pdc_eng_timeout,
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.irq_handler = pdc_interrupt,
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.irq_clear = pdc_irq_clear,
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2005-08-29 11:12:30 +02:00
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2005-04-17 00:20:36 +02:00
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.scr_read = pdc_sata_scr_read,
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.scr_write = pdc_sata_scr_write,
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.port_start = pdc_port_start,
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.port_stop = pdc_port_stop,
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2006-01-28 18:39:29 +01:00
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.host_stop = pdc_host_stop,
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2005-04-17 00:20:36 +02:00
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};
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2005-10-22 20:27:05 +02:00
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static const struct ata_port_operations pdc_pata_ops = {
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2005-08-29 11:12:30 +02:00
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.port_disable = ata_port_disable,
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.tf_load = pdc_tf_load_mmio,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = pdc_exec_command_mmio,
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.dev_select = ata_std_dev_select,
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.phy_reset = pdc_pata_phy_reset,
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.qc_prep = pdc_qc_prep,
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.qc_issue = pdc_qc_issue_prot,
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.eng_timeout = pdc_eng_timeout,
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.irq_handler = pdc_interrupt,
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.irq_clear = pdc_irq_clear,
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.port_start = pdc_port_start,
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.port_stop = pdc_port_stop,
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2006-01-28 18:39:29 +01:00
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.host_stop = pdc_host_stop,
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2005-08-29 11:12:30 +02:00
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};
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2005-11-28 10:06:23 +01:00
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static const struct ata_port_info pdc_port_info[] = {
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2005-04-17 00:20:36 +02:00
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/* board_2037x */
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{
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.sht = &pdc_ata_sht,
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2005-12-14 04:28:19 +01:00
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.host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
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2005-04-17 00:20:36 +02:00
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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2005-08-29 11:12:30 +02:00
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.port_ops = &pdc_sata_ops,
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2005-04-17 00:20:36 +02:00
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},
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/* board_20319 */
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{
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.sht = &pdc_ata_sht,
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2005-12-14 04:28:19 +01:00
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.host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
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2005-04-17 00:20:36 +02:00
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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2005-08-29 11:12:30 +02:00
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.port_ops = &pdc_sata_ops,
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2005-04-17 00:20:36 +02:00
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},
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2005-05-12 21:51:01 +02:00
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/* board_20619 */
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{
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.sht = &pdc_ata_sht,
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2005-12-14 04:28:19 +01:00
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.host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
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2005-05-12 21:51:01 +02:00
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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2005-08-29 11:12:30 +02:00
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.port_ops = &pdc_pata_ops,
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2005-05-12 21:51:01 +02:00
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},
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2006-01-17 14:06:21 +01:00
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/* board_20771 */
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{
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.sht = &pdc_ata_sht,
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.host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_sata_ops,
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},
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2006-01-28 18:39:29 +01:00
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/* board_2057x */
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{
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.sht = &pdc_ata_sht,
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.host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_sata_ops,
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},
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/* board_40518 */
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{
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.sht = &pdc_ata_sht,
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.host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_sata_ops,
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},
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2005-04-17 00:20:36 +02:00
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};
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2005-11-10 17:04:11 +01:00
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static const struct pci_device_id pdc_ata_pci_tbl[] = {
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2005-04-17 00:20:36 +02:00
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{ PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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2005-10-28 23:00:31 +02:00
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{ PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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2005-05-26 01:29:37 +02:00
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{ PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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2005-04-17 00:20:36 +02:00
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{ PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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2006-01-28 18:39:29 +01:00
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board_2057x },
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2005-04-17 00:20:36 +02:00
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{ PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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2006-01-28 18:39:29 +01:00
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board_2057x },
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2005-07-17 05:32:19 +02:00
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{ PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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2005-04-17 00:20:36 +02:00
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{ PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_20319 },
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{ PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_20319 },
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2006-03-04 16:36:21 +01:00
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{ PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_20319 },
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2005-08-22 15:59:23 +02:00
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{ PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_20319 },
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2005-08-22 15:58:57 +02:00
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{ PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_20319 },
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2005-04-17 00:20:36 +02:00
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{ PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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2006-01-28 18:39:29 +01:00
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board_40518 },
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2005-04-17 00:20:36 +02:00
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2005-05-12 21:51:01 +02:00
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|
|
{ PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
|
|
|
board_20619 },
|
|
|
|
|
2006-01-17 14:06:21 +01:00
|
|
|
{ PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
|
|
|
board_20771 },
|
2005-04-17 00:20:36 +02:00
|
|
|
{ } /* terminate list */
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static struct pci_driver pdc_ata_pci_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = pdc_ata_pci_tbl,
|
|
|
|
.probe = pdc_ata_init_one,
|
|
|
|
.remove = ata_pci_remove_one,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static int pdc_port_start(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
struct device *dev = ap->host_set->dev;
|
|
|
|
struct pdc_port_priv *pp;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = ata_port_start(ap);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
pp = kzalloc(sizeof(*pp), GFP_KERNEL);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (!pp) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
|
|
|
|
if (!pp->pkt) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_kfree;
|
|
|
|
}
|
|
|
|
|
|
|
|
ap->private_data = pp;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out_kfree:
|
|
|
|
kfree(pp);
|
|
|
|
err_out:
|
|
|
|
ata_port_stop(ap);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void pdc_port_stop(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
struct device *dev = ap->host_set->dev;
|
|
|
|
struct pdc_port_priv *pp = ap->private_data;
|
|
|
|
|
|
|
|
ap->private_data = NULL;
|
|
|
|
dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
|
|
|
|
kfree(pp);
|
|
|
|
ata_port_stop(ap);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
static void pdc_host_stop(struct ata_host_set *host_set)
|
|
|
|
{
|
|
|
|
struct pdc_host_priv *hp = host_set->private_data;
|
|
|
|
|
|
|
|
ata_pci_host_stop(host_set);
|
|
|
|
|
|
|
|
kfree(hp);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
static void pdc_reset_port(struct ata_port *ap)
|
|
|
|
{
|
2005-08-30 11:18:18 +02:00
|
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
|
2005-04-17 00:20:36 +02:00
|
|
|
unsigned int i;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
for (i = 11; i > 0; i--) {
|
|
|
|
tmp = readl(mmio);
|
|
|
|
if (tmp & PDC_RESET)
|
|
|
|
break;
|
|
|
|
|
|
|
|
udelay(100);
|
|
|
|
|
|
|
|
tmp |= PDC_RESET;
|
|
|
|
writel(tmp, mmio);
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp &= ~PDC_RESET;
|
|
|
|
writel(tmp, mmio);
|
|
|
|
readl(mmio); /* flush */
|
|
|
|
}
|
|
|
|
|
2005-08-29 11:12:30 +02:00
|
|
|
static void pdc_sata_phy_reset(struct ata_port *ap)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
pdc_reset_port(ap);
|
|
|
|
sata_phy_reset(ap);
|
|
|
|
}
|
|
|
|
|
2005-08-29 11:12:30 +02:00
|
|
|
static void pdc_pata_phy_reset(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
/* FIXME: add cable detect. Don't assume 40-pin cable */
|
|
|
|
ap->cbl = ATA_CBL_PATA40;
|
|
|
|
ap->udma_mask &= ATA_UDMA_MASK_40C;
|
|
|
|
|
|
|
|
pdc_reset_port(ap);
|
|
|
|
ata_port_probe(ap);
|
|
|
|
ata_bus_reset(ap);
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
|
|
|
|
{
|
|
|
|
if (sc_reg > SCR_CONTROL)
|
|
|
|
return 0xffffffffU;
|
2005-10-21 07:46:02 +02:00
|
|
|
return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
|
|
|
|
u32 val)
|
|
|
|
{
|
|
|
|
if (sc_reg > SCR_CONTROL)
|
|
|
|
return;
|
2005-10-21 07:46:02 +02:00
|
|
|
writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc_qc_prep(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct pdc_port_priv *pp = qc->ap->private_data;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
ata_qc_prep(qc);
|
|
|
|
/* fall through */
|
|
|
|
|
|
|
|
case ATA_PROT_NODATA:
|
|
|
|
i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
|
|
|
|
qc->dev->devno, pp->pkt);
|
|
|
|
|
|
|
|
if (qc->tf.flags & ATA_TFLAG_LBA48)
|
|
|
|
i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
|
|
|
|
else
|
|
|
|
i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
|
|
|
|
|
|
|
|
pdc_pkt_footer(&qc->tf, pp->pkt, i);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc_eng_timeout(struct ata_port *ap)
|
|
|
|
{
|
2005-08-26 04:01:20 +02:00
|
|
|
struct ata_host_set *host_set = ap->host_set;
|
2005-04-17 00:20:36 +02:00
|
|
|
u8 drv_stat;
|
|
|
|
struct ata_queued_cmd *qc;
|
2005-08-26 04:01:20 +02:00
|
|
|
unsigned long flags;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
DPRINTK("ENTER\n");
|
|
|
|
|
2005-08-26 04:01:20 +02:00
|
|
|
spin_lock_irqsave(&host_set->lock, flags);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
qc = ata_qc_from_tag(ap, ap->active_tag);
|
|
|
|
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
case ATA_PROT_NODATA:
|
|
|
|
printk(KERN_ERR "ata%u: command timeout\n", ap->id);
|
2005-10-30 10:44:42 +01:00
|
|
|
drv_stat = ata_wait_idle(ap);
|
2005-12-05 08:38:02 +01:00
|
|
|
qc->err_mask |= __ac_err_mask(drv_stat);
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
|
|
|
|
|
|
|
|
printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
|
|
|
|
ap->id, qc->tf.command, drv_stat);
|
|
|
|
|
2005-12-05 08:38:02 +01:00
|
|
|
qc->err_mask |= ac_err_mask(drv_stat);
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2005-08-26 04:01:20 +02:00
|
|
|
spin_unlock_irqrestore(&host_set->lock, flags);
|
2006-02-10 07:10:48 +01:00
|
|
|
ata_eh_qc_complete(qc);
|
2005-04-17 00:20:36 +02:00
|
|
|
DPRINTK("EXIT\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int pdc_host_intr( struct ata_port *ap,
|
|
|
|
struct ata_queued_cmd *qc)
|
|
|
|
{
|
2005-12-05 08:38:02 +01:00
|
|
|
unsigned int handled = 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
u32 tmp;
|
2005-08-30 11:18:18 +02:00
|
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
tmp = readl(mmio);
|
|
|
|
if (tmp & PDC_ERR_MASK) {
|
2005-12-05 08:38:02 +01:00
|
|
|
qc->err_mask |= AC_ERR_DEV;
|
2005-04-17 00:20:36 +02:00
|
|
|
pdc_reset_port(ap);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
case ATA_PROT_NODATA:
|
2005-12-05 08:38:02 +01:00
|
|
|
qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
|
|
|
|
ata_qc_complete(qc);
|
2005-04-17 00:20:36 +02:00
|
|
|
handled = 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2005-09-27 11:34:38 +02:00
|
|
|
ap->stats.idle_irq++;
|
|
|
|
break;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2005-09-27 11:34:38 +02:00
|
|
|
return handled;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc_irq_clear(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
struct ata_host_set *host_set = ap->host_set;
|
2005-08-30 11:18:18 +02:00
|
|
|
void __iomem *mmio = host_set->mmio_base;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
readl(mmio + PDC_INT_SEQMASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
struct ata_host_set *host_set = dev_instance;
|
|
|
|
struct ata_port *ap;
|
|
|
|
u32 mask = 0;
|
|
|
|
unsigned int i, tmp;
|
|
|
|
unsigned int handled = 0;
|
2005-08-30 11:18:18 +02:00
|
|
|
void __iomem *mmio_base;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
|
|
|
|
if (!host_set || !host_set->mmio_base) {
|
|
|
|
VPRINTK("QUICK EXIT\n");
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
mmio_base = host_set->mmio_base;
|
|
|
|
|
|
|
|
/* reading should also clear interrupts */
|
|
|
|
mask = readl(mmio_base + PDC_INT_SEQMASK);
|
|
|
|
|
|
|
|
if (mask == 0xffffffff) {
|
|
|
|
VPRINTK("QUICK EXIT 2\n");
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
2006-01-28 18:39:29 +01:00
|
|
|
|
|
|
|
spin_lock(&host_set->lock);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
mask &= 0xffff; /* only 16 tags possible */
|
|
|
|
if (!mask) {
|
|
|
|
VPRINTK("QUICK EXIT 3\n");
|
2006-01-28 18:39:29 +01:00
|
|
|
goto done_irq;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
writel(mask, mmio_base + PDC_INT_SEQMASK);
|
|
|
|
|
|
|
|
for (i = 0; i < host_set->n_ports; i++) {
|
|
|
|
VPRINTK("port %u\n", i);
|
|
|
|
ap = host_set->ports[i];
|
|
|
|
tmp = mask & (1 << (i + 1));
|
2005-08-22 07:59:24 +02:00
|
|
|
if (tmp && ap &&
|
2005-09-27 11:39:50 +02:00
|
|
|
!(ap->flags & ATA_FLAG_PORT_DISABLED)) {
|
2005-04-17 00:20:36 +02:00
|
|
|
struct ata_queued_cmd *qc;
|
|
|
|
|
|
|
|
qc = ata_qc_from_tag(ap, ap->active_tag);
|
2005-09-27 11:39:50 +02:00
|
|
|
if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
|
2005-04-17 00:20:36 +02:00
|
|
|
handled += pdc_host_intr(ap, qc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
VPRINTK("EXIT\n");
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
done_irq:
|
|
|
|
spin_unlock(&host_set->lock);
|
2005-04-17 00:20:36 +02:00
|
|
|
return IRQ_RETVAL(handled);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void pdc_packet_start(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct pdc_port_priv *pp = ap->private_data;
|
|
|
|
unsigned int port_no = ap->port_no;
|
|
|
|
u8 seq = (u8) (port_no + 1);
|
|
|
|
|
|
|
|
VPRINTK("ENTER, ap %p\n", ap);
|
|
|
|
|
|
|
|
writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
|
|
|
|
readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
|
|
|
|
|
|
|
|
pp->pkt[2] = seq;
|
|
|
|
wmb(); /* flush PRD, pkt writes */
|
2005-10-21 07:46:02 +02:00
|
|
|
writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
|
|
|
|
readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2006-01-23 05:09:36 +01:00
|
|
|
static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
case ATA_PROT_NODATA:
|
|
|
|
pdc_packet_start(qc);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case ATA_PROT_ATAPI_DMA:
|
|
|
|
BUG();
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ata_qc_issue_prot(qc);
|
|
|
|
}
|
|
|
|
|
2005-10-22 20:27:05 +02:00
|
|
|
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
|
|
|
tf->protocol == ATA_PROT_NODATA);
|
|
|
|
ata_tf_load(ap, tf);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-10-22 20:27:05 +02:00
|
|
|
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
|
|
|
tf->protocol == ATA_PROT_NODATA);
|
|
|
|
ata_exec_command(ap, tf);
|
|
|
|
}
|
|
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|
|
|
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|
|
|
static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
|
|
|
|
{
|
|
|
|
port->cmd_addr = base;
|
|
|
|
port->data_addr = base;
|
|
|
|
port->feature_addr =
|
|
|
|
port->error_addr = base + 0x4;
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|
|
port->nsect_addr = base + 0x8;
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|
|
port->lbal_addr = base + 0xc;
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|
|
port->lbam_addr = base + 0x10;
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|
|
port->lbah_addr = base + 0x14;
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|
|
port->device_addr = base + 0x18;
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|
|
port->command_addr =
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|
port->status_addr = base + 0x1c;
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|
port->altstatus_addr =
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|
|
port->ctl_addr = base + 0x38;
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|
}
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|
|
static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
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|
|
{
|
2005-08-30 11:18:18 +02:00
|
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|
void __iomem *mmio = pe->mmio_base;
|
2006-01-28 18:39:29 +01:00
|
|
|
struct pdc_host_priv *hp = pe->private_data;
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|
|
int hotplug_offset = hp->hotplug_offset;
|
2005-04-17 00:20:36 +02:00
|
|
|
u32 tmp;
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|
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|
|
/*
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|
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|
* Except for the hotplug stuff, this is voodoo from the
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|
* Promise driver. Label this entire section
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|
|
* "TODO: figure out why we do this"
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|
|
|
*/
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|
|
/* change FIFO_SHD to 8 dwords, enable BMR_BURST */
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|
|
tmp = readl(mmio + PDC_FLASH_CTL);
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|
|
tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
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|
|
writel(tmp, mmio + PDC_FLASH_CTL);
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|
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|
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|
|
/* clear plug/unplug flags for all ports */
|
2006-01-28 18:39:29 +01:00
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|
tmp = readl(mmio + hotplug_offset);
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|
|
writel(tmp | 0xff, mmio + hotplug_offset);
|
2005-04-17 00:20:36 +02:00
|
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|
|
/* mask plug/unplug ints */
|
2006-01-28 18:39:29 +01:00
|
|
|
tmp = readl(mmio + hotplug_offset);
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|
|
writel(tmp | 0xff0000, mmio + hotplug_offset);
|
2005-04-17 00:20:36 +02:00
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|
|
/* reduce TBG clock to 133 Mhz. */
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|
tmp = readl(mmio + PDC_TBG_MODE);
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tmp &= ~0x30000; /* clear bit 17, 16*/
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tmp |= 0x10000; /* set bit 17:16 = 0:1 */
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writel(tmp, mmio + PDC_TBG_MODE);
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readl(mmio + PDC_TBG_MODE); /* flush */
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|
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msleep(10);
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/* adjust slew rate control register. */
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tmp = readl(mmio + PDC_SLEW_CTL);
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tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
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tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
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|
|
writel(tmp, mmio + PDC_SLEW_CTL);
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|
|
}
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|
|
static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
{
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|
|
|
static int printed_version;
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|
|
|
struct ata_probe_ent *probe_ent = NULL;
|
2006-01-28 18:39:29 +01:00
|
|
|
struct pdc_host_priv *hp;
|
2005-04-17 00:20:36 +02:00
|
|
|
unsigned long base;
|
2005-08-30 11:18:18 +02:00
|
|
|
void __iomem *mmio_base;
|
2005-04-17 00:20:36 +02:00
|
|
|
unsigned int board_idx = (unsigned int) ent->driver_data;
|
|
|
|
int pci_dev_busy = 0;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (!printed_version++)
|
2005-10-30 20:39:11 +01:00
|
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If this driver happens to only be useful on Apple's K2, then
|
|
|
|
* we should check that here as it has a normal Serverworks ID
|
|
|
|
*/
|
|
|
|
rc = pci_enable_device(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
rc = pci_request_regions(pdev, DRV_NAME);
|
|
|
|
if (rc) {
|
|
|
|
pci_dev_busy = 1;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
|
|
|
|
if (rc)
|
|
|
|
goto err_out_regions;
|
|
|
|
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
|
|
|
|
if (rc)
|
|
|
|
goto err_out_regions;
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (probe_ent == NULL) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_regions;
|
|
|
|
}
|
|
|
|
|
|
|
|
probe_ent->dev = pci_dev_to_dev(pdev);
|
|
|
|
INIT_LIST_HEAD(&probe_ent->node);
|
|
|
|
|
2005-08-30 11:42:52 +02:00
|
|
|
mmio_base = pci_iomap(pdev, 3, 0);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (mmio_base == NULL) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_free_ent;
|
|
|
|
}
|
|
|
|
base = (unsigned long) mmio_base;
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
hp = kzalloc(sizeof(*hp), GFP_KERNEL);
|
|
|
|
if (hp == NULL) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_free_ent;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set default hotplug offset */
|
|
|
|
hp->hotplug_offset = PDC_SATA_PLUG_CSR;
|
|
|
|
probe_ent->private_data = hp;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
probe_ent->sht = pdc_port_info[board_idx].sht;
|
|
|
|
probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
|
|
|
|
probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
|
|
|
|
probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
|
|
|
|
probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
|
|
|
|
probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
|
|
|
|
|
|
|
|
probe_ent->irq = pdev->irq;
|
|
|
|
probe_ent->irq_flags = SA_SHIRQ;
|
|
|
|
probe_ent->mmio_base = mmio_base;
|
|
|
|
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
|
|
|
|
|
|
|
|
probe_ent->port[0].scr_addr = base + 0x400;
|
|
|
|
probe_ent->port[1].scr_addr = base + 0x500;
|
|
|
|
|
|
|
|
/* notice 4-port boards */
|
|
|
|
switch (board_idx) {
|
2006-01-28 18:39:29 +01:00
|
|
|
case board_40518:
|
|
|
|
/* Override hotplug offset for SATAII150 */
|
|
|
|
hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
|
|
|
|
/* Fall through */
|
2005-04-17 00:20:36 +02:00
|
|
|
case board_20319:
|
|
|
|
probe_ent->n_ports = 4;
|
|
|
|
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
|
|
|
|
|
|
|
|
probe_ent->port[2].scr_addr = base + 0x600;
|
|
|
|
probe_ent->port[3].scr_addr = base + 0x700;
|
|
|
|
break;
|
2006-01-28 18:39:29 +01:00
|
|
|
case board_2057x:
|
|
|
|
/* Override hotplug offset for SATAII150 */
|
|
|
|
hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
|
|
|
|
/* Fall through */
|
2005-04-17 00:20:36 +02:00
|
|
|
case board_2037x:
|
2005-11-30 22:42:55 +01:00
|
|
|
probe_ent->n_ports = 2;
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
2006-01-17 14:06:21 +01:00
|
|
|
case board_20771:
|
|
|
|
probe_ent->n_ports = 2;
|
|
|
|
break;
|
2005-05-12 21:51:01 +02:00
|
|
|
case board_20619:
|
|
|
|
probe_ent->n_ports = 4;
|
|
|
|
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
|
|
|
|
|
|
|
|
probe_ent->port[2].scr_addr = base + 0x600;
|
|
|
|
probe_ent->port[3].scr_addr = base + 0x700;
|
2005-11-30 22:42:55 +01:00
|
|
|
break;
|
2005-04-17 00:20:36 +02:00
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_set_master(pdev);
|
|
|
|
|
|
|
|
/* initialize adapter */
|
|
|
|
pdc_host_init(board_idx, probe_ent);
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
/* FIXME: Need any other frees than hp? */
|
|
|
|
if (!ata_device_add(probe_ent))
|
|
|
|
kfree(hp);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
kfree(probe_ent);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out_free_ent:
|
|
|
|
kfree(probe_ent);
|
|
|
|
err_out_regions:
|
|
|
|
pci_release_regions(pdev);
|
|
|
|
err_out:
|
|
|
|
if (!pci_dev_busy)
|
|
|
|
pci_disable_device(pdev);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int __init pdc_ata_init(void)
|
|
|
|
{
|
|
|
|
return pci_module_init(&pdc_ata_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void __exit pdc_ata_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&pdc_ata_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Jeff Garzik");
|
2005-05-12 21:51:01 +02:00
|
|
|
MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
|
2005-04-17 00:20:36 +02:00
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
|
|
|
|
module_init(pdc_ata_init);
|
|
|
|
module_exit(pdc_ata_exit);
|