2012-03-05 12:49:30 +01:00
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/*
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* SMP initialisation and IPI support
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* Based on arch/arm/kernel/smp.c
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*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/cache.h>
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#include <linux/profile.h>
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#include <linux/errno.h>
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#include <linux/mm.h>
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#include <linux/err.h>
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#include <linux/cpu.h>
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#include <linux/smp.h>
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#include <linux/seq_file.h>
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#include <linux/irq.h>
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#include <linux/percpu.h>
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#include <linux/clockchips.h>
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#include <linux/completion.h>
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#include <linux/of.h>
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2014-05-12 17:48:51 +02:00
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#include <linux/irq_work.h>
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2012-03-05 12:49:30 +01:00
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#include <asm/atomic.h>
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#include <asm/cacheflush.h>
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2014-07-16 17:32:44 +02:00
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#include <asm/cpu.h>
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2012-03-05 12:49:30 +01:00
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#include <asm/cputype.h>
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2013-10-24 21:30:15 +02:00
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#include <asm/cpu_ops.h>
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2012-03-05 12:49:30 +01:00
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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2012-08-29 10:47:19 +02:00
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#include <asm/smp_plat.h>
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2012-03-05 12:49:30 +01:00
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#include <asm/sections.h>
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#include <asm/tlbflush.h>
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#include <asm/ptrace.h>
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2014-07-25 22:05:32 +02:00
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#define CREATE_TRACE_POINTS
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#include <trace/events/ipi.h>
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2012-03-05 12:49:30 +01:00
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/*
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* as from 2.5, kernels no longer have an init_tasks structure
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* so we need some other way of telling a new secondary core
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* where to place its SVC stack
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*/
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struct secondary_data secondary_data;
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enum ipi_msg_type {
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IPI_RESCHEDULE,
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IPI_CALL_FUNC,
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IPI_CALL_FUNC_SINGLE,
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IPI_CPU_STOP,
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2013-09-04 11:55:17 +02:00
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IPI_TIMER,
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2014-05-12 17:48:51 +02:00
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IPI_IRQ_WORK,
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2012-03-05 12:49:30 +01:00
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};
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/*
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* Boot a secondary CPU, and assign it the specified idle task.
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* This also gives us the initial stack to use for this CPU.
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*/
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2013-06-18 16:18:31 +02:00
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static int boot_secondary(unsigned int cpu, struct task_struct *idle)
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2012-03-05 12:49:30 +01:00
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{
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arm64: factor out spin-table boot method
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-24 21:30:16 +02:00
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if (cpu_ops[cpu]->cpu_boot)
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return cpu_ops[cpu]->cpu_boot(cpu);
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2012-03-05 12:49:30 +01:00
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arm64: factor out spin-table boot method
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-24 21:30:16 +02:00
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return -EOPNOTSUPP;
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2012-03-05 12:49:30 +01:00
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}
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static DECLARE_COMPLETION(cpu_running);
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2013-06-18 16:18:31 +02:00
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int __cpu_up(unsigned int cpu, struct task_struct *idle)
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2012-03-05 12:49:30 +01:00
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{
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int ret;
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/*
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* We need to tell the secondary core where to find its stack and the
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* page tables.
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*/
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secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
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__flush_dcache_area(&secondary_data, sizeof(secondary_data));
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/*
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* Now bring the CPU into our world.
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*/
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ret = boot_secondary(cpu, idle);
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if (ret == 0) {
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/*
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* CPU was successfully started, wait for it to come online or
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* time out.
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*/
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wait_for_completion_timeout(&cpu_running,
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msecs_to_jiffies(1000));
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if (!cpu_online(cpu)) {
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pr_crit("CPU%u: failed to come online\n", cpu);
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ret = -EIO;
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}
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} else {
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pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
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}
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secondary_data.stack = NULL;
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return ret;
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}
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2014-03-04 08:51:17 +01:00
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static void smp_store_cpu_info(unsigned int cpuid)
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{
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store_cpu_topology(cpuid);
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}
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2012-03-05 12:49:30 +01:00
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/*
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* This is the secondary CPU boot entry. We're using this CPUs
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* idle thread stack, but a set of temporary page tables.
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*/
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2013-06-18 16:18:31 +02:00
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asmlinkage void secondary_start_kernel(void)
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2012-03-05 12:49:30 +01:00
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{
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struct mm_struct *mm = &init_mm;
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unsigned int cpu = smp_processor_id();
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/*
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* All kernel threads share the same mm context; grab a
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* reference and switch to it.
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*/
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atomic_inc(&mm->mm_count);
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current->active_mm = mm;
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cpumask_set_cpu(cpu, mm_cpumask(mm));
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2013-11-05 19:10:47 +01:00
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set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
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printk("CPU%u: Booted secondary processor\n", cpu);
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2012-03-05 12:49:30 +01:00
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/*
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* TTBR0 is only used for the identity mapping at this stage. Make it
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* point to zero page to avoid speculatively fetching new entries.
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*/
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cpu_set_reserved_ttbr0();
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flush_tlb_all();
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preempt_disable();
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trace_hardirqs_off();
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|
arm64: factor out spin-table boot method
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-24 21:30:16 +02:00
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if (cpu_ops[cpu]->cpu_postboot)
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cpu_ops[cpu]->cpu_postboot();
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2012-03-05 12:49:30 +01:00
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2014-07-16 17:32:44 +02:00
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/*
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* Log the CPU info before it is marked online and might get read.
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*/
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cpuinfo_store_cpu();
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2013-11-04 17:55:22 +01:00
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/*
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* Enable GIC and timers.
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*/
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notify_cpu_starting(cpu);
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2014-03-04 08:51:17 +01:00
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smp_store_cpu_info(cpu);
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2012-03-05 12:49:30 +01:00
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/*
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* OK, now it's safe to let the boot CPU continue. Wait for
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* the CPU migration code to notice that the CPU is online
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* before we continue.
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*/
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set_cpu_online(cpu, true);
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2012-11-07 18:00:05 +01:00
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complete(&cpu_running);
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2012-03-05 12:49:30 +01:00
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2014-02-21 06:13:49 +01:00
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local_dbg_enable();
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2013-07-19 16:08:15 +02:00
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local_irq_enable();
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2013-11-21 15:46:17 +01:00
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local_async_enable();
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2013-07-19 16:08:15 +02:00
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2012-03-05 12:49:30 +01:00
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/*
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* OK, it's off to the idle thread for us
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*/
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2013-03-21 22:49:39 +01:00
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cpu_startup_entry(CPUHP_ONLINE);
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2012-03-05 12:49:30 +01:00
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}
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2013-10-24 21:30:18 +02:00
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#ifdef CONFIG_HOTPLUG_CPU
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static int op_cpu_disable(unsigned int cpu)
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{
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/*
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* If we don't have a cpu_die method, abort before we reach the point
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* of no return. CPU0 may not have an cpu_ops, so test for it.
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*/
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if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die)
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return -EOPNOTSUPP;
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/*
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* We may need to abort a hot unplug for some other mechanism-specific
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* reason.
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*/
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if (cpu_ops[cpu]->cpu_disable)
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return cpu_ops[cpu]->cpu_disable(cpu);
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return 0;
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}
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/*
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* __cpu_disable runs on the processor to be shutdown.
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*/
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int __cpu_disable(void)
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{
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unsigned int cpu = smp_processor_id();
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int ret;
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ret = op_cpu_disable(cpu);
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if (ret)
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return ret;
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/*
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* Take this CPU offline. Once we clear this, we can't return,
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* and we must not schedule until we're ready to give up the cpu.
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*/
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set_cpu_online(cpu, false);
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/*
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* OK - migrate IRQs away from this CPU
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*/
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migrate_irqs();
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/*
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* Remove this CPU from the vm mask set of all processes.
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*/
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clear_tasks_mm_cpumask(cpu);
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return 0;
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}
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|
2014-05-07 16:18:36 +02:00
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|
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static int op_cpu_kill(unsigned int cpu)
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{
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/*
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* If we have no means of synchronising with the dying CPU, then assume
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* that it is really dead. We can only wait for an arbitrary length of
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* time and hope that it's dead, so let's skip the wait and just hope.
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*/
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if (!cpu_ops[cpu]->cpu_kill)
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return 1;
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return cpu_ops[cpu]->cpu_kill(cpu);
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|
}
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|
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|
2013-10-24 21:30:18 +02:00
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static DECLARE_COMPLETION(cpu_died);
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/*
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* called on the thread which is asking for a CPU to be shutdown -
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* waits until shutdown has completed, or it is timed out.
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*/
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void __cpu_die(unsigned int cpu)
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{
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if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
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pr_crit("CPU%u: cpu didn't die\n", cpu);
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return;
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}
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|
pr_notice("CPU%u: shutdown\n", cpu);
|
2014-05-07 16:18:36 +02:00
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/*
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* Now that the dying CPU is beyond the point of no return w.r.t.
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* in-kernel synchronisation, try to get the firwmare to help us to
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* verify that it has really left the kernel before we consider
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* clobbering anything it might still be using.
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*/
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if (!op_cpu_kill(cpu))
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pr_warn("CPU%d may not have shut down cleanly\n", cpu);
|
2013-10-24 21:30:18 +02:00
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|
|
}
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/*
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* Called from the idle thread for the CPU which has been shutdown.
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*
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|
* Note that we disable IRQs here, but do not re-enable them
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|
* before returning to the caller. This is also the behaviour
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|
* of the other hotplug-cpu capable cores, so presumably coming
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|
* out of idle fixes this.
|
|
|
|
*/
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|
|
|
void cpu_die(void)
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|
|
|
{
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|
unsigned int cpu = smp_processor_id();
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idle_task_exit();
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local_irq_disable();
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/* Tell __cpu_die() that this CPU is now safe to dispose of */
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|
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complete(&cpu_died);
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/*
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|
|
* Actually shutdown the CPU. This must never fail. The specific hotplug
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|
* mechanism must perform all required cache maintenance to ensure that
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|
|
* no dirty lines are lost in the process of shutting down the CPU.
|
|
|
|
*/
|
|
|
|
cpu_ops[cpu]->cpu_die(cpu);
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|
|
|
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-03-05 12:49:30 +01:00
|
|
|
void __init smp_cpus_done(unsigned int max_cpus)
|
|
|
|
{
|
2013-08-30 19:06:48 +02:00
|
|
|
pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
|
2012-03-05 12:49:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void __init smp_prepare_boot_cpu(void)
|
|
|
|
{
|
2013-11-05 19:10:47 +01:00
|
|
|
set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
|
2012-03-05 12:49:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2012-08-29 10:47:19 +02:00
|
|
|
* Enumerate the possible CPU set from the device tree and build the
|
|
|
|
* cpu logical map array containing MPIDR values related to logical
|
|
|
|
* cpus. Assumes that cpu_logical_map(0) has already been initialized.
|
2012-03-05 12:49:30 +01:00
|
|
|
*/
|
|
|
|
void __init smp_init_cpus(void)
|
|
|
|
{
|
|
|
|
struct device_node *dn = NULL;
|
2013-10-24 21:30:15 +02:00
|
|
|
unsigned int i, cpu = 1;
|
2012-08-29 10:47:19 +02:00
|
|
|
bool bootcpu_valid = false;
|
2012-03-05 12:49:30 +01:00
|
|
|
|
|
|
|
while ((dn = of_find_node_by_type(dn, "cpu"))) {
|
2013-04-22 19:28:55 +02:00
|
|
|
const u32 *cell;
|
2012-08-29 10:47:19 +02:00
|
|
|
u64 hwid;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* A cpu node with missing "reg" property is
|
|
|
|
* considered invalid to build a cpu_logical_map
|
|
|
|
* entry.
|
|
|
|
*/
|
2013-04-22 19:28:55 +02:00
|
|
|
cell = of_get_property(dn, "reg", NULL);
|
|
|
|
if (!cell) {
|
2012-08-29 10:47:19 +02:00
|
|
|
pr_err("%s: missing reg property\n", dn->full_name);
|
|
|
|
goto next;
|
|
|
|
}
|
2013-04-22 19:28:55 +02:00
|
|
|
hwid = of_read_number(cell, of_n_addr_cells(dn));
|
2012-08-29 10:47:19 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Non affinity bits must be set to 0 in the DT
|
|
|
|
*/
|
|
|
|
if (hwid & ~MPIDR_HWID_BITMASK) {
|
|
|
|
pr_err("%s: invalid reg property\n", dn->full_name);
|
|
|
|
goto next;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Duplicate MPIDRs are a recipe for disaster. Scan
|
|
|
|
* all initialized entries and check for
|
|
|
|
* duplicates. If any is found just ignore the cpu.
|
|
|
|
* cpu_logical_map was initialized to INVALID_HWID to
|
|
|
|
* avoid matching valid MPIDR values.
|
|
|
|
*/
|
|
|
|
for (i = 1; (i < cpu) && (i < NR_CPUS); i++) {
|
|
|
|
if (cpu_logical_map(i) == hwid) {
|
|
|
|
pr_err("%s: duplicate cpu reg properties in the DT\n",
|
|
|
|
dn->full_name);
|
|
|
|
goto next;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The numbering scheme requires that the boot CPU
|
|
|
|
* must be assigned logical id 0. Record it so that
|
|
|
|
* the logical map built from DT is validated and can
|
|
|
|
* be used.
|
|
|
|
*/
|
|
|
|
if (hwid == cpu_logical_map(0)) {
|
|
|
|
if (bootcpu_valid) {
|
|
|
|
pr_err("%s: duplicate boot cpu reg property in DT\n",
|
|
|
|
dn->full_name);
|
|
|
|
goto next;
|
|
|
|
}
|
|
|
|
|
|
|
|
bootcpu_valid = true;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* cpu_logical_map has already been
|
|
|
|
* initialized and the boot cpu doesn't need
|
|
|
|
* the enable-method so continue without
|
|
|
|
* incrementing cpu.
|
|
|
|
*/
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2012-03-05 12:49:30 +01:00
|
|
|
if (cpu >= NR_CPUS)
|
|
|
|
goto next;
|
|
|
|
|
2013-10-24 21:30:17 +02:00
|
|
|
if (cpu_read_ops(dn, cpu) != 0)
|
2012-03-05 12:49:30 +01:00
|
|
|
goto next;
|
|
|
|
|
2013-10-24 21:30:15 +02:00
|
|
|
if (cpu_ops[cpu]->cpu_init(dn, cpu))
|
2013-01-02 16:24:22 +01:00
|
|
|
goto next;
|
|
|
|
|
2012-08-29 10:47:19 +02:00
|
|
|
pr_debug("cpu logical map 0x%llx\n", hwid);
|
|
|
|
cpu_logical_map(cpu) = hwid;
|
2012-03-05 12:49:30 +01:00
|
|
|
next:
|
|
|
|
cpu++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* sanity check */
|
|
|
|
if (cpu > NR_CPUS)
|
|
|
|
pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
|
|
|
|
cpu, NR_CPUS);
|
2012-08-29 10:47:19 +02:00
|
|
|
|
|
|
|
if (!bootcpu_valid) {
|
|
|
|
pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* All the cpus that made it to the cpu_logical_map have been
|
|
|
|
* validated so set them as possible cpus.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < NR_CPUS; i++)
|
|
|
|
if (cpu_logical_map(i) != INVALID_HWID)
|
|
|
|
set_cpu_possible(i, true);
|
2012-03-05 12:49:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void __init smp_prepare_cpus(unsigned int max_cpus)
|
|
|
|
{
|
2013-10-24 21:30:15 +02:00
|
|
|
int err;
|
|
|
|
unsigned int cpu, ncores = num_possible_cpus();
|
2012-03-05 12:49:30 +01:00
|
|
|
|
2014-03-04 08:51:17 +01:00
|
|
|
init_cpu_topology();
|
|
|
|
|
|
|
|
smp_store_cpu_info(smp_processor_id());
|
|
|
|
|
2012-03-05 12:49:30 +01:00
|
|
|
/*
|
|
|
|
* are we trying to boot more cores than exist?
|
|
|
|
*/
|
|
|
|
if (max_cpus > ncores)
|
|
|
|
max_cpus = ncores;
|
|
|
|
|
2013-01-02 16:24:22 +01:00
|
|
|
/* Don't bother if we're effectively UP */
|
|
|
|
if (max_cpus <= 1)
|
|
|
|
return;
|
|
|
|
|
2012-03-05 12:49:30 +01:00
|
|
|
/*
|
|
|
|
* Initialise the present map (which describes the set of CPUs
|
|
|
|
* actually populated at the present time) and release the
|
|
|
|
* secondaries from the bootloader.
|
2013-01-02 16:24:22 +01:00
|
|
|
*
|
|
|
|
* Make sure we online at most (max_cpus - 1) additional CPUs.
|
2012-03-05 12:49:30 +01:00
|
|
|
*/
|
2013-01-02 16:24:22 +01:00
|
|
|
max_cpus--;
|
2012-03-05 12:49:30 +01:00
|
|
|
for_each_possible_cpu(cpu) {
|
|
|
|
if (max_cpus == 0)
|
|
|
|
break;
|
|
|
|
|
2013-01-02 16:24:22 +01:00
|
|
|
if (cpu == smp_processor_id())
|
|
|
|
continue;
|
|
|
|
|
2013-10-24 21:30:15 +02:00
|
|
|
if (!cpu_ops[cpu])
|
2012-03-05 12:49:30 +01:00
|
|
|
continue;
|
|
|
|
|
2013-10-24 21:30:15 +02:00
|
|
|
err = cpu_ops[cpu]->cpu_prepare(cpu);
|
2013-01-02 16:24:22 +01:00
|
|
|
if (err)
|
|
|
|
continue;
|
2012-03-05 12:49:30 +01:00
|
|
|
|
|
|
|
set_cpu_present(cpu, true);
|
|
|
|
max_cpus--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-08-16 18:48:05 +02:00
|
|
|
void (*__smp_cross_call)(const struct cpumask *, unsigned int);
|
2012-03-05 12:49:30 +01:00
|
|
|
|
|
|
|
void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
|
|
|
|
{
|
2014-07-25 22:05:32 +02:00
|
|
|
__smp_cross_call = fn;
|
2012-03-05 12:49:30 +01:00
|
|
|
}
|
|
|
|
|
2014-07-25 22:05:32 +02:00
|
|
|
static const char *ipi_types[NR_IPI] __tracepoint_string = {
|
|
|
|
#define S(x,s) [x] = s
|
2012-03-05 12:49:30 +01:00
|
|
|
S(IPI_RESCHEDULE, "Rescheduling interrupts"),
|
|
|
|
S(IPI_CALL_FUNC, "Function call interrupts"),
|
|
|
|
S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
|
|
|
|
S(IPI_CPU_STOP, "CPU stop interrupts"),
|
2013-09-04 11:55:17 +02:00
|
|
|
S(IPI_TIMER, "Timer broadcast interrupts"),
|
2014-05-12 17:48:51 +02:00
|
|
|
S(IPI_IRQ_WORK, "IRQ work interrupts"),
|
2012-03-05 12:49:30 +01:00
|
|
|
};
|
|
|
|
|
2014-07-25 22:05:32 +02:00
|
|
|
static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
|
|
|
|
{
|
|
|
|
trace_ipi_raise(target, ipi_types[ipinr]);
|
|
|
|
__smp_cross_call(target, ipinr);
|
|
|
|
}
|
|
|
|
|
2012-03-05 12:49:30 +01:00
|
|
|
void show_ipi_list(struct seq_file *p, int prec)
|
|
|
|
{
|
|
|
|
unsigned int cpu, i;
|
|
|
|
|
|
|
|
for (i = 0; i < NR_IPI; i++) {
|
2014-07-25 22:05:32 +02:00
|
|
|
seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
|
2012-03-05 12:49:30 +01:00
|
|
|
prec >= 4 ? " " : "");
|
2013-11-07 16:25:44 +01:00
|
|
|
for_each_online_cpu(cpu)
|
2012-03-05 12:49:30 +01:00
|
|
|
seq_printf(p, "%10u ",
|
|
|
|
__get_irq_stat(cpu, ipi_irqs[i]));
|
|
|
|
seq_printf(p, " %s\n", ipi_types[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
u64 smp_irq_stat_cpu(unsigned int cpu)
|
|
|
|
{
|
|
|
|
u64 sum = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < NR_IPI; i++)
|
|
|
|
sum += __get_irq_stat(cpu, ipi_irqs[i]);
|
|
|
|
|
|
|
|
return sum;
|
|
|
|
}
|
|
|
|
|
2014-07-25 22:05:32 +02:00
|
|
|
void arch_send_call_function_ipi_mask(const struct cpumask *mask)
|
|
|
|
{
|
|
|
|
smp_cross_call(mask, IPI_CALL_FUNC);
|
|
|
|
}
|
|
|
|
|
|
|
|
void arch_send_call_function_single_ipi(int cpu)
|
|
|
|
{
|
|
|
|
smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_IRQ_WORK
|
|
|
|
void arch_irq_work_raise(void)
|
|
|
|
{
|
|
|
|
if (__smp_cross_call)
|
|
|
|
smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-03-05 12:49:30 +01:00
|
|
|
static DEFINE_RAW_SPINLOCK(stop_lock);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ipi_cpu_stop - handle IPI from smp_send_stop()
|
|
|
|
*/
|
|
|
|
static void ipi_cpu_stop(unsigned int cpu)
|
|
|
|
{
|
|
|
|
if (system_state == SYSTEM_BOOTING ||
|
|
|
|
system_state == SYSTEM_RUNNING) {
|
|
|
|
raw_spin_lock(&stop_lock);
|
|
|
|
pr_crit("CPU%u: stopping\n", cpu);
|
|
|
|
dump_stack();
|
|
|
|
raw_spin_unlock(&stop_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
set_cpu_online(cpu, false);
|
|
|
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
|
|
|
while (1)
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Main handler for inter-processor interrupts
|
|
|
|
*/
|
|
|
|
void handle_IPI(int ipinr, struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
struct pt_regs *old_regs = set_irq_regs(regs);
|
|
|
|
|
2014-07-25 22:05:32 +02:00
|
|
|
if ((unsigned)ipinr < NR_IPI) {
|
|
|
|
trace_ipi_entry(ipi_types[ipinr]);
|
|
|
|
__inc_irq_stat(cpu, ipi_irqs[ipinr]);
|
|
|
|
}
|
2012-03-05 12:49:30 +01:00
|
|
|
|
|
|
|
switch (ipinr) {
|
|
|
|
case IPI_RESCHEDULE:
|
|
|
|
scheduler_ipi();
|
|
|
|
break;
|
|
|
|
|
|
|
|
case IPI_CALL_FUNC:
|
|
|
|
irq_enter();
|
|
|
|
generic_smp_call_function_interrupt();
|
|
|
|
irq_exit();
|
|
|
|
break;
|
|
|
|
|
|
|
|
case IPI_CALL_FUNC_SINGLE:
|
|
|
|
irq_enter();
|
|
|
|
generic_smp_call_function_single_interrupt();
|
|
|
|
irq_exit();
|
|
|
|
break;
|
|
|
|
|
|
|
|
case IPI_CPU_STOP:
|
|
|
|
irq_enter();
|
|
|
|
ipi_cpu_stop(cpu);
|
|
|
|
irq_exit();
|
|
|
|
break;
|
|
|
|
|
2013-09-04 11:55:17 +02:00
|
|
|
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
|
|
|
|
case IPI_TIMER:
|
|
|
|
irq_enter();
|
|
|
|
tick_receive_broadcast();
|
|
|
|
irq_exit();
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2014-05-12 17:48:51 +02:00
|
|
|
#ifdef CONFIG_IRQ_WORK
|
|
|
|
case IPI_IRQ_WORK:
|
|
|
|
irq_enter();
|
|
|
|
irq_work_run();
|
|
|
|
irq_exit();
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2012-03-05 12:49:30 +01:00
|
|
|
default:
|
|
|
|
pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
|
|
|
|
break;
|
|
|
|
}
|
2014-07-25 22:05:32 +02:00
|
|
|
|
|
|
|
if ((unsigned)ipinr < NR_IPI)
|
|
|
|
trace_ipi_exit(ipi_types[ipinr]);
|
2012-03-05 12:49:30 +01:00
|
|
|
set_irq_regs(old_regs);
|
|
|
|
}
|
|
|
|
|
|
|
|
void smp_send_reschedule(int cpu)
|
|
|
|
{
|
|
|
|
smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
|
|
|
|
}
|
|
|
|
|
2013-09-04 11:55:17 +02:00
|
|
|
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
|
|
|
|
void tick_broadcast(const struct cpumask *mask)
|
|
|
|
{
|
|
|
|
smp_cross_call(mask, IPI_TIMER);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-03-05 12:49:30 +01:00
|
|
|
void smp_send_stop(void)
|
|
|
|
{
|
|
|
|
unsigned long timeout;
|
|
|
|
|
|
|
|
if (num_online_cpus() > 1) {
|
|
|
|
cpumask_t mask;
|
|
|
|
|
|
|
|
cpumask_copy(&mask, cpu_online_mask);
|
|
|
|
cpu_clear(smp_processor_id(), mask);
|
|
|
|
|
|
|
|
smp_cross_call(&mask, IPI_CPU_STOP);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Wait up to one second for other CPUs to stop */
|
|
|
|
timeout = USEC_PER_SEC;
|
|
|
|
while (num_online_cpus() > 1 && timeout--)
|
|
|
|
udelay(1);
|
|
|
|
|
|
|
|
if (num_online_cpus() > 1)
|
|
|
|
pr_warning("SMP: failed to stop secondary CPUs\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* not supported here
|
|
|
|
*/
|
|
|
|
int setup_profiling_timer(unsigned int multiplier)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|