[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
/*
|
2008-03-27 19:51:41 +01:00
|
|
|
* arch/arm/mach-orion5x/common.c
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
*
|
2008-03-27 19:51:41 +01:00
|
|
|
* Core functions for Marvell Orion 5x SoCs
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
*
|
|
|
|
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
|
|
|
|
*
|
2008-03-27 19:51:41 +01:00
|
|
|
* This file is licensed under the terms of the GNU General Public
|
|
|
|
* License version 2. This program is licensed "as is" without any
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
* warranty of any kind, whether express or implied.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/init.h>
|
2007-10-23 21:14:42 +02:00
|
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <linux/serial_8250.h>
|
2008-03-27 19:51:39 +01:00
|
|
|
#include <linux/mbus.h>
|
2007-11-12 08:51:36 +01:00
|
|
|
#include <linux/mv643xx_i2c.h>
|
2008-03-27 19:51:39 +01:00
|
|
|
#include <linux/ata_platform.h>
|
2008-09-25 16:23:48 +02:00
|
|
|
#include <net/dsa.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
#include <asm/page.h>
|
2008-02-29 21:12:57 +01:00
|
|
|
#include <asm/setup.h>
|
2007-10-23 21:14:42 +02:00
|
|
|
#include <asm/timex.h>
|
2008-02-29 21:12:57 +01:00
|
|
|
#include <asm/mach/arch.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
#include <asm/mach/map.h>
|
2008-03-27 19:51:40 +01:00
|
|
|
#include <asm/mach/time.h>
|
2010-10-15 16:50:26 +02:00
|
|
|
#include <mach/bridge-regs.h>
|
2008-08-05 17:14:15 +02:00
|
|
|
#include <mach/hardware.h>
|
|
|
|
#include <mach/orion5x.h>
|
2008-08-09 13:44:58 +02:00
|
|
|
#include <plat/ehci-orion.h>
|
2008-06-17 12:25:12 +02:00
|
|
|
#include <plat/mv_xor.h>
|
2008-08-09 13:44:58 +02:00
|
|
|
#include <plat/orion_nand.h>
|
2009-06-01 19:56:02 +02:00
|
|
|
#include <plat/orion_wdt.h>
|
2008-08-09 13:44:58 +02:00
|
|
|
#include <plat/time.h>
|
2011-05-15 13:32:41 +02:00
|
|
|
#include <plat/common.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
#include "common.h"
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* I/O Address Mapping
|
|
|
|
****************************************************************************/
|
2008-03-27 19:51:41 +01:00
|
|
|
static struct map_desc orion5x_io_desc[] __initdata = {
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
{
|
2008-03-27 19:51:41 +01:00
|
|
|
.virtual = ORION5X_REGS_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
|
|
|
|
.length = ORION5X_REGS_SIZE,
|
2008-05-10 16:30:01 +02:00
|
|
|
.type = MT_DEVICE,
|
|
|
|
}, {
|
2008-03-27 19:51:41 +01:00
|
|
|
.virtual = ORION5X_PCIE_IO_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
|
|
|
|
.length = ORION5X_PCIE_IO_SIZE,
|
2008-05-10 16:30:01 +02:00
|
|
|
.type = MT_DEVICE,
|
|
|
|
}, {
|
2008-03-27 19:51:41 +01:00
|
|
|
.virtual = ORION5X_PCI_IO_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
|
|
|
|
.length = ORION5X_PCI_IO_SIZE,
|
2008-05-10 16:30:01 +02:00
|
|
|
.type = MT_DEVICE,
|
|
|
|
}, {
|
2008-03-27 19:51:41 +01:00
|
|
|
.virtual = ORION5X_PCIE_WA_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
|
|
|
|
.length = ORION5X_PCIE_WA_SIZE,
|
2008-05-10 16:30:01 +02:00
|
|
|
.type = MT_DEVICE,
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 19:51:41 +01:00
|
|
|
void __init orion5x_map_io(void)
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
{
|
2008-03-27 19:51:41 +01:00
|
|
|
iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 21:14:41 +02:00
|
|
|
}
|
2007-10-23 21:14:42 +02:00
|
|
|
|
2008-04-22 05:37:12 +02:00
|
|
|
|
2007-10-23 21:14:42 +02:00
|
|
|
/*****************************************************************************
|
2008-04-22 05:37:12 +02:00
|
|
|
* EHCI
|
2007-10-23 21:14:42 +02:00
|
|
|
****************************************************************************/
|
2008-04-22 05:37:12 +02:00
|
|
|
static struct orion_ehci_data orion5x_ehci_data = {
|
|
|
|
.dram = &orion5x_mbus_dram_info,
|
2008-09-17 09:08:05 +02:00
|
|
|
.phy_version = EHCI_PHY_ORION,
|
2007-10-23 21:14:42 +02:00
|
|
|
};
|
|
|
|
|
2011-05-15 13:32:40 +02:00
|
|
|
static u64 ehci_dmamask = DMA_BIT_MASK(32);
|
2007-10-23 21:14:42 +02:00
|
|
|
|
|
|
|
|
2008-04-22 05:37:12 +02:00
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI0
|
|
|
|
****************************************************************************/
|
2008-03-27 19:51:41 +01:00
|
|
|
static struct resource orion5x_ehci0_resources[] = {
|
2007-10-23 21:14:42 +02:00
|
|
|
{
|
2008-03-27 19:51:41 +01:00
|
|
|
.start = ORION5X_USB0_PHYS_BASE,
|
2008-04-25 22:30:21 +02:00
|
|
|
.end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
|
2007-10-23 21:14:42 +02:00
|
|
|
.flags = IORESOURCE_MEM,
|
2008-05-10 16:30:01 +02:00
|
|
|
}, {
|
2008-03-27 19:51:41 +01:00
|
|
|
.start = IRQ_ORION5X_USB0_CTRL,
|
|
|
|
.end = IRQ_ORION5X_USB0_CTRL,
|
2007-10-23 21:14:42 +02:00
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 19:51:41 +01:00
|
|
|
static struct platform_device orion5x_ehci0 = {
|
2007-10-23 21:14:42 +02:00
|
|
|
.name = "orion-ehci",
|
|
|
|
.id = 0,
|
|
|
|
.dev = {
|
|
|
|
.dma_mask = &ehci_dmamask,
|
2011-05-15 13:32:40 +02:00
|
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
2008-03-27 19:51:41 +01:00
|
|
|
.platform_data = &orion5x_ehci_data,
|
2007-10-23 21:14:42 +02:00
|
|
|
},
|
2008-03-27 19:51:41 +01:00
|
|
|
.resource = orion5x_ehci0_resources,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
|
2007-10-23 21:14:42 +02:00
|
|
|
};
|
|
|
|
|
2008-04-22 05:37:12 +02:00
|
|
|
void __init orion5x_ehci0_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_ehci0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI1
|
|
|
|
****************************************************************************/
|
|
|
|
static struct resource orion5x_ehci1_resources[] = {
|
|
|
|
{
|
|
|
|
.start = ORION5X_USB1_PHYS_BASE,
|
|
|
|
.end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.start = IRQ_ORION5X_USB1_CTRL,
|
|
|
|
.end = IRQ_ORION5X_USB1_CTRL,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 19:51:41 +01:00
|
|
|
static struct platform_device orion5x_ehci1 = {
|
2007-10-23 21:14:42 +02:00
|
|
|
.name = "orion-ehci",
|
|
|
|
.id = 1,
|
|
|
|
.dev = {
|
|
|
|
.dma_mask = &ehci_dmamask,
|
2011-05-15 13:32:40 +02:00
|
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
2008-03-27 19:51:41 +01:00
|
|
|
.platform_data = &orion5x_ehci_data,
|
2007-10-23 21:14:42 +02:00
|
|
|
},
|
2008-03-27 19:51:41 +01:00
|
|
|
.resource = orion5x_ehci1_resources,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
|
2007-10-23 21:14:42 +02:00
|
|
|
};
|
|
|
|
|
2008-04-22 05:37:12 +02:00
|
|
|
void __init orion5x_ehci1_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_ehci1);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-10-31 11:42:41 +01:00
|
|
|
/*****************************************************************************
|
2011-05-15 13:32:40 +02:00
|
|
|
* GE00
|
2007-10-31 11:42:41 +01:00
|
|
|
****************************************************************************/
|
2008-03-27 19:51:41 +01:00
|
|
|
void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
|
2007-10-31 11:42:41 +01:00
|
|
|
{
|
2011-05-15 13:32:44 +02:00
|
|
|
orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
|
|
|
|
ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
|
|
|
|
IRQ_ORION5X_ETH_ERR, orion5x_tclk);
|
2007-10-31 11:42:41 +01:00
|
|
|
}
|
|
|
|
|
2008-04-22 05:37:12 +02:00
|
|
|
|
2008-09-25 16:23:48 +02:00
|
|
|
/*****************************************************************************
|
|
|
|
* Ethernet switch
|
|
|
|
****************************************************************************/
|
|
|
|
void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
|
|
|
|
{
|
2011-05-15 13:32:44 +02:00
|
|
|
orion_ge00_switch_init(d, irq);
|
2008-09-25 16:23:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-11-12 08:51:36 +01:00
|
|
|
/*****************************************************************************
|
2008-04-22 05:37:12 +02:00
|
|
|
* I2C
|
2007-11-12 08:51:36 +01:00
|
|
|
****************************************************************************/
|
2008-04-22 05:37:12 +02:00
|
|
|
void __init orion5x_i2c_init(void)
|
|
|
|
{
|
2011-05-15 13:32:45 +02:00
|
|
|
orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
|
|
|
|
|
2008-04-22 05:37:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-01-29 23:33:32 +01:00
|
|
|
/*****************************************************************************
|
2008-04-22 05:37:12 +02:00
|
|
|
* SATA
|
2008-01-29 23:33:32 +01:00
|
|
|
****************************************************************************/
|
2008-03-27 19:51:41 +01:00
|
|
|
static struct resource orion5x_sata_resources[] = {
|
2008-01-29 23:33:32 +01:00
|
|
|
{
|
2008-05-10 16:30:01 +02:00
|
|
|
.name = "sata base",
|
|
|
|
.start = ORION5X_SATA_PHYS_BASE,
|
|
|
|
.end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.name = "sata irq",
|
|
|
|
.start = IRQ_ORION5X_SATA,
|
|
|
|
.end = IRQ_ORION5X_SATA,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
2008-01-29 23:33:32 +01:00
|
|
|
};
|
|
|
|
|
2008-03-27 19:51:41 +01:00
|
|
|
static struct platform_device orion5x_sata = {
|
2008-05-10 16:30:01 +02:00
|
|
|
.name = "sata_mv",
|
|
|
|
.id = 0,
|
2008-01-29 23:33:32 +01:00
|
|
|
.dev = {
|
2011-05-15 13:32:40 +02:00
|
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
2008-01-29 23:33:32 +01:00
|
|
|
},
|
2008-05-10 16:30:01 +02:00
|
|
|
.num_resources = ARRAY_SIZE(orion5x_sata_resources),
|
|
|
|
.resource = orion5x_sata_resources,
|
2008-01-29 23:33:32 +01:00
|
|
|
};
|
|
|
|
|
2008-03-27 19:51:41 +01:00
|
|
|
void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
|
2008-01-29 23:33:32 +01:00
|
|
|
{
|
2008-03-27 19:51:41 +01:00
|
|
|
sata_data->dram = &orion5x_mbus_dram_info;
|
|
|
|
orion5x_sata.dev.platform_data = sata_data;
|
|
|
|
platform_device_register(&orion5x_sata);
|
2008-01-29 23:33:32 +01:00
|
|
|
}
|
|
|
|
|
2008-04-22 05:37:12 +02:00
|
|
|
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 06:55:06 +02:00
|
|
|
/*****************************************************************************
|
|
|
|
* SPI
|
|
|
|
****************************************************************************/
|
|
|
|
void __init orion5x_spi_init()
|
|
|
|
{
|
2011-05-15 13:32:46 +02:00
|
|
|
orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 06:55:06 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-03-27 19:51:40 +01:00
|
|
|
/*****************************************************************************
|
2008-04-22 05:37:12 +02:00
|
|
|
* UART0
|
|
|
|
****************************************************************************/
|
|
|
|
void __init orion5x_uart0_init(void)
|
|
|
|
{
|
2011-05-15 13:32:41 +02:00
|
|
|
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
|
|
|
|
IRQ_ORION5X_UART0, orion5x_tclk);
|
2008-04-22 05:37:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* UART1
|
2008-03-27 19:51:40 +01:00
|
|
|
****************************************************************************/
|
2008-04-22 05:37:12 +02:00
|
|
|
void __init orion5x_uart1_init(void)
|
|
|
|
{
|
2011-05-15 13:32:41 +02:00
|
|
|
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
|
|
|
|
IRQ_ORION5X_UART1, orion5x_tclk);
|
2008-04-22 05:37:12 +02:00
|
|
|
}
|
2008-03-27 19:51:40 +01:00
|
|
|
|
2008-06-17 12:25:12 +02:00
|
|
|
/*****************************************************************************
|
|
|
|
* XOR engine
|
|
|
|
****************************************************************************/
|
2009-03-02 16:30:36 +01:00
|
|
|
struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
|
|
|
|
.dram = &orion5x_mbus_dram_info,
|
|
|
|
};
|
|
|
|
|
2008-06-17 12:25:12 +02:00
|
|
|
static struct resource orion5x_xor_shared_resources[] = {
|
|
|
|
{
|
|
|
|
.name = "xor low",
|
|
|
|
.start = ORION5X_XOR_PHYS_BASE,
|
|
|
|
.end = ORION5X_XOR_PHYS_BASE + 0xff,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.name = "xor high",
|
|
|
|
.start = ORION5X_XOR_PHYS_BASE + 0x200,
|
|
|
|
.end = ORION5X_XOR_PHYS_BASE + 0x2ff,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_xor_shared = {
|
|
|
|
.name = MV_XOR_SHARED_NAME,
|
|
|
|
.id = 0,
|
2009-03-02 16:30:36 +01:00
|
|
|
.dev = {
|
|
|
|
.platform_data = &orion5x_xor_shared_data,
|
|
|
|
},
|
2008-06-17 12:25:12 +02:00
|
|
|
.num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
|
|
|
|
.resource = orion5x_xor_shared_resources,
|
|
|
|
};
|
|
|
|
|
2009-04-07 04:01:15 +02:00
|
|
|
static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
|
2008-06-17 12:25:12 +02:00
|
|
|
|
|
|
|
static struct resource orion5x_xor0_resources[] = {
|
|
|
|
[0] = {
|
|
|
|
.start = IRQ_ORION5X_XOR0,
|
|
|
|
.end = IRQ_ORION5X_XOR0,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct mv_xor_platform_data orion5x_xor0_data = {
|
|
|
|
.shared = &orion5x_xor_shared,
|
|
|
|
.hw_id = 0,
|
|
|
|
.pool_size = PAGE_SIZE,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_xor0_channel = {
|
|
|
|
.name = MV_XOR_NAME,
|
|
|
|
.id = 0,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_xor0_resources),
|
|
|
|
.resource = orion5x_xor0_resources,
|
|
|
|
.dev = {
|
|
|
|
.dma_mask = &orion5x_xor_dmamask,
|
2009-04-07 04:01:13 +02:00
|
|
|
.coherent_dma_mask = DMA_BIT_MASK(64),
|
2010-01-29 23:56:58 +01:00
|
|
|
.platform_data = &orion5x_xor0_data,
|
2008-06-17 12:25:12 +02:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct resource orion5x_xor1_resources[] = {
|
|
|
|
[0] = {
|
|
|
|
.start = IRQ_ORION5X_XOR1,
|
|
|
|
.end = IRQ_ORION5X_XOR1,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct mv_xor_platform_data orion5x_xor1_data = {
|
|
|
|
.shared = &orion5x_xor_shared,
|
|
|
|
.hw_id = 1,
|
|
|
|
.pool_size = PAGE_SIZE,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_xor1_channel = {
|
|
|
|
.name = MV_XOR_NAME,
|
|
|
|
.id = 1,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_xor1_resources),
|
|
|
|
.resource = orion5x_xor1_resources,
|
|
|
|
.dev = {
|
|
|
|
.dma_mask = &orion5x_xor_dmamask,
|
2009-04-07 04:01:13 +02:00
|
|
|
.coherent_dma_mask = DMA_BIT_MASK(64),
|
2010-01-29 23:56:58 +01:00
|
|
|
.platform_data = &orion5x_xor1_data,
|
2008-06-17 12:25:12 +02:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init orion5x_xor_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_xor_shared);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* two engines can't do memset simultaneously, this limitation
|
|
|
|
* satisfied by removing memset support from one of the engines.
|
|
|
|
*/
|
|
|
|
dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
|
|
|
|
dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
|
|
|
|
platform_device_register(&orion5x_xor0_channel);
|
|
|
|
|
|
|
|
dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
|
|
|
|
dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
|
|
|
|
dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
|
|
|
|
platform_device_register(&orion5x_xor1_channel);
|
|
|
|
}
|
|
|
|
|
2009-05-07 22:59:24 +02:00
|
|
|
static struct resource orion5x_crypto_res[] = {
|
|
|
|
{
|
|
|
|
.name = "regs",
|
|
|
|
.start = ORION5X_CRYPTO_PHYS_BASE,
|
|
|
|
.end = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.name = "sram",
|
|
|
|
.start = ORION5X_SRAM_PHYS_BASE,
|
|
|
|
.end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.name = "crypto interrupt",
|
|
|
|
.start = IRQ_ORION5X_CESA,
|
|
|
|
.end = IRQ_ORION5X_CESA,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_crypto_device = {
|
|
|
|
.name = "mv_crypto",
|
|
|
|
.id = -1,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_crypto_res),
|
|
|
|
.resource = orion5x_crypto_res,
|
|
|
|
};
|
|
|
|
|
2009-06-11 22:27:20 +02:00
|
|
|
static int __init orion5x_crypto_init(void)
|
2009-05-07 22:59:24 +02:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = orion5x_setup_sram_win();
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return platform_device_register(&orion5x_crypto_device);
|
|
|
|
}
|
2008-06-17 12:25:12 +02:00
|
|
|
|
2009-02-24 23:59:22 +01:00
|
|
|
/*****************************************************************************
|
|
|
|
* Watchdog
|
|
|
|
****************************************************************************/
|
2009-06-01 19:56:02 +02:00
|
|
|
static struct orion_wdt_platform_data orion5x_wdt_data = {
|
2009-02-24 23:59:22 +01:00
|
|
|
.tclk = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_wdt_device = {
|
2009-06-01 19:56:02 +02:00
|
|
|
.name = "orion_wdt",
|
2009-02-24 23:59:22 +01:00
|
|
|
.id = -1,
|
|
|
|
.dev = {
|
|
|
|
.platform_data = &orion5x_wdt_data,
|
|
|
|
},
|
|
|
|
.num_resources = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init orion5x_wdt_init(void)
|
|
|
|
{
|
|
|
|
orion5x_wdt_data.tclk = orion5x_tclk;
|
|
|
|
platform_device_register(&orion5x_wdt_device);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-04-22 05:37:12 +02:00
|
|
|
/*****************************************************************************
|
|
|
|
* Time handling
|
|
|
|
****************************************************************************/
|
2010-10-15 16:50:26 +02:00
|
|
|
void __init orion5x_init_early(void)
|
|
|
|
{
|
|
|
|
orion_time_set_base(TIMER_VIRT_BASE);
|
|
|
|
}
|
|
|
|
|
2008-08-29 05:55:51 +02:00
|
|
|
int orion5x_tclk;
|
|
|
|
|
|
|
|
int __init orion5x_find_tclk(void)
|
|
|
|
{
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 06:55:06 +02:00
|
|
|
u32 dev, rev;
|
|
|
|
|
|
|
|
orion5x_pcie_id(&dev, &rev);
|
|
|
|
if (dev == MV88F6183_DEV_ID &&
|
|
|
|
(readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
|
|
|
|
return 133333333;
|
|
|
|
|
2008-08-29 05:55:51 +02:00
|
|
|
return 166666667;
|
|
|
|
}
|
|
|
|
|
2008-03-27 19:51:41 +01:00
|
|
|
static void orion5x_timer_init(void)
|
2008-03-27 19:51:40 +01:00
|
|
|
{
|
2008-08-29 05:55:51 +02:00
|
|
|
orion5x_tclk = orion5x_find_tclk();
|
2010-10-15 16:50:26 +02:00
|
|
|
|
|
|
|
orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
|
|
|
|
IRQ_ORION5X_BRIDGE, orion5x_tclk);
|
2008-03-27 19:51:40 +01:00
|
|
|
}
|
|
|
|
|
2008-03-27 19:51:41 +01:00
|
|
|
struct sys_timer orion5x_timer = {
|
2008-05-10 16:30:01 +02:00
|
|
|
.init = orion5x_timer_init,
|
2008-03-27 19:51:40 +01:00
|
|
|
};
|
|
|
|
|
2008-04-22 05:37:12 +02:00
|
|
|
|
2007-10-23 21:14:42 +02:00
|
|
|
/*****************************************************************************
|
|
|
|
* General
|
|
|
|
****************************************************************************/
|
|
|
|
/*
|
2008-04-25 22:31:32 +02:00
|
|
|
* Identify device ID and rev from PCIe configuration header space '0'.
|
2007-10-23 21:14:42 +02:00
|
|
|
*/
|
2008-03-27 19:51:41 +01:00
|
|
|
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
|
2007-10-23 21:14:42 +02:00
|
|
|
{
|
2008-03-27 19:51:41 +01:00
|
|
|
orion5x_pcie_id(dev, rev);
|
2007-10-23 21:14:42 +02:00
|
|
|
|
|
|
|
if (*dev == MV88F5281_DEV_ID) {
|
|
|
|
if (*rev == MV88F5281_REV_D2) {
|
|
|
|
*dev_name = "MV88F5281-D2";
|
|
|
|
} else if (*rev == MV88F5281_REV_D1) {
|
|
|
|
*dev_name = "MV88F5281-D1";
|
2008-08-09 15:17:27 +02:00
|
|
|
} else if (*rev == MV88F5281_REV_D0) {
|
|
|
|
*dev_name = "MV88F5281-D0";
|
2007-10-23 21:14:42 +02:00
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F5281-Rev-Unsupported";
|
|
|
|
}
|
|
|
|
} else if (*dev == MV88F5182_DEV_ID) {
|
|
|
|
if (*rev == MV88F5182_REV_A2) {
|
|
|
|
*dev_name = "MV88F5182-A2";
|
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F5182-Rev-Unsupported";
|
|
|
|
}
|
2007-11-11 12:05:11 +01:00
|
|
|
} else if (*dev == MV88F5181_DEV_ID) {
|
|
|
|
if (*rev == MV88F5181_REV_B1) {
|
|
|
|
*dev_name = "MV88F5181-Rev-B1";
|
2008-05-31 08:30:40 +02:00
|
|
|
} else if (*rev == MV88F5181L_REV_A1) {
|
|
|
|
*dev_name = "MV88F5181L-Rev-A1";
|
2007-11-11 12:05:11 +01:00
|
|
|
} else {
|
2008-05-31 08:30:40 +02:00
|
|
|
*dev_name = "MV88F5181(L)-Rev-Unsupported";
|
2007-11-11 12:05:11 +01:00
|
|
|
}
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 06:55:06 +02:00
|
|
|
} else if (*dev == MV88F6183_DEV_ID) {
|
|
|
|
if (*rev == MV88F6183_REV_B0) {
|
|
|
|
*dev_name = "MV88F6183-Rev-B0";
|
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F6183-Rev-Unsupported";
|
|
|
|
}
|
2007-10-23 21:14:42 +02:00
|
|
|
} else {
|
|
|
|
*dev_name = "Device-Unknown";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-03-27 19:51:41 +01:00
|
|
|
void __init orion5x_init(void)
|
2007-10-23 21:14:42 +02:00
|
|
|
{
|
|
|
|
char *dev_name;
|
|
|
|
u32 dev, rev;
|
|
|
|
|
2008-03-27 19:51:41 +01:00
|
|
|
orion5x_id(&dev, &rev, &dev_name);
|
2008-08-29 05:55:51 +02:00
|
|
|
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
|
|
|
|
|
2007-10-23 21:14:42 +02:00
|
|
|
/*
|
|
|
|
* Setup Orion address map
|
|
|
|
*/
|
2008-03-27 19:51:41 +01:00
|
|
|
orion5x_setup_cpu_mbus_bridge();
|
2008-08-09 15:17:27 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Don't issue "Wait for Interrupt" instruction if we are
|
|
|
|
* running on D0 5281 silicon.
|
|
|
|
*/
|
|
|
|
if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
|
|
|
|
printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
|
|
|
|
disable_hlt();
|
|
|
|
}
|
2009-02-24 23:59:22 +01:00
|
|
|
|
2009-06-11 22:27:20 +02:00
|
|
|
/*
|
|
|
|
* The 5082/5181l/5182/6082/6082l/6183 have crypto
|
|
|
|
* while 5180n/5181/5281 don't have crypto.
|
|
|
|
*/
|
|
|
|
if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
|
|
|
|
dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
|
|
|
|
orion5x_crypto_init();
|
|
|
|
|
2009-02-24 23:59:22 +01:00
|
|
|
/*
|
|
|
|
* Register watchdog driver
|
|
|
|
*/
|
|
|
|
orion5x_wdt_init();
|
2007-10-23 21:14:42 +02:00
|
|
|
}
|
2008-02-29 21:12:57 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Many orion-based systems have buggy bootloader implementations.
|
|
|
|
* This is a common fixup for bogus memory tags.
|
|
|
|
*/
|
|
|
|
void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
|
|
|
|
char **from, struct meminfo *meminfo)
|
|
|
|
{
|
|
|
|
for (; t->hdr.size; t = tag_next(t))
|
|
|
|
if (t->hdr.tag == ATAG_MEM &&
|
|
|
|
(!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
|
|
|
|
t->u.mem.start & ~PAGE_MASK)) {
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"Clearing invalid memory bank %dKB@0x%08x\n",
|
|
|
|
t->u.mem.size / 1024, t->u.mem.start);
|
|
|
|
t->hdr.tag = 0;
|
|
|
|
}
|
|
|
|
}
|