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linux/arch/tile/kernel/hvglue.lds

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arch/tile: core support for Tilera 32-bit chips. This change is the core kernel support for TILEPro and TILE64 chips. No driver support (except the console driver) is included yet. This includes the relevant Linux headers in asm/; the low-level low-level "Tile architecture" headers in arch/, which are shared with the hypervisor, etc., and are build-system agnostic; and the relevant hypervisor headers in hv/. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Reviewed-by: Paul Mundt <lethal@linux-sh.org>
2010-05-29 05:09:12 +02:00
/* Hypervisor call vector addresses; see <hv/hypervisor.h> */
hv_init = TEXT_OFFSET + 0x10020;
hv_install_context = TEXT_OFFSET + 0x10040;
hv_sysconf = TEXT_OFFSET + 0x10060;
hv_get_rtc = TEXT_OFFSET + 0x10080;
hv_set_rtc = TEXT_OFFSET + 0x100a0;
hv_flush_asid = TEXT_OFFSET + 0x100c0;
hv_flush_page = TEXT_OFFSET + 0x100e0;
hv_flush_pages = TEXT_OFFSET + 0x10100;
hv_restart = TEXT_OFFSET + 0x10120;
hv_halt = TEXT_OFFSET + 0x10140;
hv_power_off = TEXT_OFFSET + 0x10160;
hv_inquire_physical = TEXT_OFFSET + 0x10180;
hv_inquire_memory_controller = TEXT_OFFSET + 0x101a0;
hv_inquire_virtual = TEXT_OFFSET + 0x101c0;
hv_inquire_asid = TEXT_OFFSET + 0x101e0;
hv_nanosleep = TEXT_OFFSET + 0x10200;
hv_console_read_if_ready = TEXT_OFFSET + 0x10220;
hv_console_write = TEXT_OFFSET + 0x10240;
hv_downcall_dispatch = TEXT_OFFSET + 0x10260;
hv_inquire_topology = TEXT_OFFSET + 0x10280;
hv_fs_findfile = TEXT_OFFSET + 0x102a0;
hv_fs_fstat = TEXT_OFFSET + 0x102c0;
hv_fs_pread = TEXT_OFFSET + 0x102e0;
hv_physaddr_read64 = TEXT_OFFSET + 0x10300;
hv_physaddr_write64 = TEXT_OFFSET + 0x10320;
hv_get_command_line = TEXT_OFFSET + 0x10340;
hv_set_caching = TEXT_OFFSET + 0x10360;
hv_bzero_page = TEXT_OFFSET + 0x10380;
hv_register_message_state = TEXT_OFFSET + 0x103a0;
hv_send_message = TEXT_OFFSET + 0x103c0;
hv_receive_message = TEXT_OFFSET + 0x103e0;
hv_inquire_context = TEXT_OFFSET + 0x10400;
hv_start_all_tiles = TEXT_OFFSET + 0x10420;
hv_dev_open = TEXT_OFFSET + 0x10440;
hv_dev_close = TEXT_OFFSET + 0x10460;
hv_dev_pread = TEXT_OFFSET + 0x10480;
hv_dev_pwrite = TEXT_OFFSET + 0x104a0;
hv_dev_poll = TEXT_OFFSET + 0x104c0;
hv_dev_poll_cancel = TEXT_OFFSET + 0x104e0;
hv_dev_preada = TEXT_OFFSET + 0x10500;
hv_dev_pwritea = TEXT_OFFSET + 0x10520;
hv_flush_remote = TEXT_OFFSET + 0x10540;
hv_console_putc = TEXT_OFFSET + 0x10560;
hv_inquire_tiles = TEXT_OFFSET + 0x10580;
hv_confstr = TEXT_OFFSET + 0x105a0;
hv_reexec = TEXT_OFFSET + 0x105c0;
hv_set_command_line = TEXT_OFFSET + 0x105e0;
arch/tile: Enable more sophisticated IRQ model for 32-bit chips. This model is based on the on-chip interrupt model used by the TILE-Gx next-generation hardware, and interacts much more cleanly with the Linux generic IRQ layer. The change includes modifications to the Tilera hypervisor, which are reflected in the hypervisor headers in arch/tile/include/arch/. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
2010-06-25 22:41:11 +02:00
hv_clear_intr = TEXT_OFFSET + 0x10600;
arch/tile: core support for Tilera 32-bit chips. This change is the core kernel support for TILEPro and TILE64 chips. No driver support (except the console driver) is included yet. This includes the relevant Linux headers in asm/; the low-level low-level "Tile architecture" headers in arch/, which are shared with the hypervisor, etc., and are build-system agnostic; and the relevant hypervisor headers in hv/. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Reviewed-by: Paul Mundt <lethal@linux-sh.org>
2010-05-29 05:09:12 +02:00
hv_enable_intr = TEXT_OFFSET + 0x10620;
hv_disable_intr = TEXT_OFFSET + 0x10640;
arch/tile: Enable more sophisticated IRQ model for 32-bit chips. This model is based on the on-chip interrupt model used by the TILE-Gx next-generation hardware, and interacts much more cleanly with the Linux generic IRQ layer. The change includes modifications to the Tilera hypervisor, which are reflected in the hypervisor headers in arch/tile/include/arch/. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
2010-06-25 22:41:11 +02:00
hv_raise_intr = TEXT_OFFSET + 0x10660;
hv_trigger_ipi = TEXT_OFFSET + 0x10680;
hv_store_mapping = TEXT_OFFSET + 0x106a0;
hv_inquire_realpa = TEXT_OFFSET + 0x106c0;
hv_flush_all = TEXT_OFFSET + 0x106e0;
hv_get_ipi_pte = TEXT_OFFSET + 0x10700;
arch/tile: support multiple huge page sizes dynamically This change adds support for a new "super" bit in the PTE, using the new arch_make_huge_pte() method. The Tilera hypervisor sees the bit set at a given level of the page table and gangs together 4, 16, or 64 consecutive pages from that level of the hierarchy to create a larger TLB entry. One extra "super" page size can be specified at each of the three levels of the page table hierarchy on tilegx, using the "hugepagesz" argument on the boot command line. A new hypervisor API is added to allow Linux to tell the hypervisor how many PTEs to gang together at each level of the page table. To allow pre-allocating huge pages larger than the buddy allocator can handle, this change modifies the Tilera bootmem support to put all of memory on tilegx platforms into bootmem. As part of this change I eliminate the vestigial CONFIG_HIGHPTE support, which never worked anyway, and eliminate the hv_page_size() API in favor of the standard vma_kernel_pagesize() API. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-01 20:04:21 +02:00
hv_set_pte_super_shift = TEXT_OFFSET + 0x10720;
hv_glue_internals = TEXT_OFFSET + 0x10740;