2008-10-23 07:26:29 +02:00
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#ifndef _ASM_X86_MCE_H
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#define _ASM_X86_MCE_H
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2007-10-17 18:04:40 +02:00
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2009-01-30 18:17:27 +01:00
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#include <linux/types.h>
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2007-10-17 18:04:40 +02:00
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#include <asm/ioctls.h>
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/*
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* Machine Check support for x86
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*/
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2011-06-08 03:56:56 +02:00
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/* MCG_CAP register defines */
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2009-04-08 12:31:24 +02:00
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#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
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2009-06-21 08:27:16 +02:00
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#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
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2009-04-08 12:31:24 +02:00
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#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
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#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
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#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
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#define MCG_EXT_CNT_SHIFT 16
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#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
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2009-05-27 21:56:57 +02:00
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#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
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2007-10-17 18:04:40 +02:00
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2011-06-08 03:56:56 +02:00
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/* MCG_STATUS register defines */
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2009-04-08 12:31:25 +02:00
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#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
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#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
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2007-10-17 18:04:40 +02:00
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2011-06-08 03:56:56 +02:00
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/* MCi_STATUS register defines */
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2009-04-08 12:31:25 +02:00
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#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
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#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
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#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
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#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
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#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
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#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
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2009-05-27 21:56:57 +02:00
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#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
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#define MCI_STATUS_AR (1ULL<<55) /* Action required */
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2012-07-19 20:21:53 +02:00
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#define MCACOD 0xffff /* MCA Error Code */
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/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
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#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
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#define MCACOD_SCRUBMSK 0xfff0
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#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
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#define MCACOD_DATA 0x0134 /* Data Load */
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#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
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2009-05-27 21:56:57 +02:00
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2011-06-08 03:56:56 +02:00
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/* MCi_MISC register defines */
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#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
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#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
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#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
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#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
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#define MCI_MISC_ADDR_PHYS 2 /* physical address */
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#define MCI_MISC_ADDR_MEM 3 /* memory address */
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#define MCI_MISC_ADDR_GENERIC 7 /* generic */
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2007-10-17 18:04:40 +02:00
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2010-06-08 08:09:08 +02:00
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/* CTL2 register defines */
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#define MCI_CTL2_CMCI_EN (1ULL << 30)
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2010-06-08 08:09:10 +02:00
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#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
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2010-06-08 08:09:08 +02:00
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2009-07-31 03:41:40 +02:00
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#define MCJ_CTX_MASK 3
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#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
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#define MCJ_CTX_RANDOM 0 /* inject context: random */
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2011-12-07 18:21:37 +01:00
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#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
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#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
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#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
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#define MCJ_EXCEPTION 0x8 /* raise as exception */
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#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
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2009-07-31 03:41:40 +02:00
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2007-10-17 18:04:40 +02:00
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/* Fields are zero when not available */
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struct mce {
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__u64 status;
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__u64 misc;
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__u64 addr;
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__u64 mcgstatus;
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2008-01-30 13:30:56 +01:00
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__u64 ip;
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2007-10-17 18:04:40 +02:00
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__u64 tsc; /* cpu time stamp counter */
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2009-05-27 21:56:56 +02:00
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__u64 time; /* wall time_t when error was detected */
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__u8 cpuvendor; /* cpu vendor as encoded in system.h */
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2009-07-31 03:41:40 +02:00
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__u8 inject_flags; /* software inject flags */
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__u16 pad;
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2009-05-27 21:56:56 +02:00
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__u32 cpuid; /* CPUID 1 EAX */
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2007-10-17 18:04:40 +02:00
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__u8 cs; /* code segment */
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__u8 bank; /* machine check bank */
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2009-05-27 21:56:56 +02:00
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__u8 cpu; /* cpu number; obsolete; use extcpu now */
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2007-10-17 18:04:40 +02:00
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__u8 finished; /* entry is valid */
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2009-05-27 21:56:56 +02:00
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__u32 extcpu; /* linux cpu number that detected the error */
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2009-05-27 21:56:56 +02:00
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__u32 socketid; /* CPU socket ID */
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__u32 apicid; /* CPU initial apic ID */
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__u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
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2007-10-17 18:04:40 +02:00
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};
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/*
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* This structure contains all data related to the MCE log. Also
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* carries a signature to make it easier to find from external
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* debugging tools. Each entry is only valid when its finished flag
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* is set.
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*/
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#define MCE_LOG_LEN 32
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struct mce_log {
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char signature[12]; /* "MACHINECHECK" */
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unsigned len; /* = MCE_LOG_LEN */
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unsigned next;
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unsigned flags;
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2009-05-27 21:56:55 +02:00
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unsigned recordlen; /* length of struct mce */
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struct mce entry[MCE_LOG_LEN];
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};
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
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#define MCE_LOG_SIGNATURE "MACHINECHECK"
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#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
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#define MCE_GET_LOG_LEN _IOR('M', 2, int)
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#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
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/* Software defined banks */
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#define MCE_EXTENDED_BANK 128
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#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
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#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
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#define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
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#define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
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#define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
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#define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
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#define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
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#define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
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#define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
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2009-10-07 13:20:38 +02:00
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2007-10-17 18:04:40 +02:00
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#ifdef __KERNEL__
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2011-12-04 15:12:09 +01:00
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extern void mce_register_decode_chain(struct notifier_block *nb);
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extern void mce_unregister_decode_chain(struct notifier_block *nb);
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2010-01-04 17:17:21 +01:00
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2009-06-15 10:22:15 +02:00
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#include <linux/percpu.h>
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#include <linux/init.h>
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2011-07-27 01:09:06 +02:00
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#include <linux/atomic.h>
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2009-06-15 10:22:15 +02:00
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2007-10-17 18:04:40 +02:00
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extern int mce_disabled;
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2009-06-15 10:22:49 +02:00
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extern int mce_p5_enabled;
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2007-10-17 18:04:40 +02:00
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2009-06-15 10:27:47 +02:00
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#ifdef CONFIG_X86_MCE
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2009-11-10 02:38:24 +01:00
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int mcheck_init(void);
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2009-10-16 12:31:32 +02:00
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void mcheck_cpu_init(struct cpuinfo_x86 *c);
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2009-06-15 10:27:47 +02:00
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#else
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2009-11-10 02:38:24 +01:00
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static inline int mcheck_init(void) { return 0; }
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2009-10-16 12:31:32 +02:00
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static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
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2009-06-15 10:27:47 +02:00
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#endif
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2009-06-15 10:22:15 +02:00
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#ifdef CONFIG_X86_ANCIENT_MCE
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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2009-06-15 10:22:49 +02:00
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static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
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2009-06-15 10:22:15 +02:00
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#else
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static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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2009-06-15 10:22:49 +02:00
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static inline void enable_p5_mce(void) {}
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2009-06-15 10:22:15 +02:00
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#endif
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2009-02-12 13:43:22 +01:00
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void mce_setup(struct mce *m);
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2007-10-17 18:04:40 +02:00
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void mce_log(struct mce *m);
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2012-01-27 00:49:14 +01:00
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DECLARE_PER_CPU(struct device *, mce_device);
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2007-10-17 18:04:40 +02:00
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2009-02-12 13:49:30 +01:00
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/*
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2009-07-09 00:31:45 +02:00
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* Maximum banks number.
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* This is the limit of the current register layout on
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* Intel CPUs.
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2009-02-12 13:49:30 +01:00
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*/
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2009-07-09 00:31:45 +02:00
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#define MAX_NR_BANKS 32
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2009-02-12 13:49:30 +01:00
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2007-10-17 18:04:40 +02:00
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#ifdef CONFIG_X86_MCE_INTEL
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2009-06-11 09:06:07 +02:00
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extern int mce_cmci_disabled;
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extern int mce_ignore_ce;
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2007-10-17 18:04:40 +02:00
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void mce_intel_feature_init(struct cpuinfo_x86 *c);
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2009-02-12 13:49:36 +01:00
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void cmci_clear(void);
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void cmci_reenable(void);
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void cmci_rediscover(int dying);
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void cmci_recheck(void);
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2007-10-17 18:04:40 +02:00
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#else
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static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
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2009-02-12 13:49:36 +01:00
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static inline void cmci_clear(void) {}
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static inline void cmci_reenable(void) {}
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static inline void cmci_rediscover(int dying) {}
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static inline void cmci_recheck(void) {}
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2007-10-17 18:04:40 +02:00
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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#else
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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#endif
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2009-05-28 19:05:33 +02:00
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int mce_available(struct cpuinfo_x86 *c);
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2009-02-12 13:49:36 +01:00
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2009-05-27 21:56:52 +02:00
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DECLARE_PER_CPU(unsigned, mce_exception_count);
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2009-05-27 21:56:57 +02:00
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DECLARE_PER_CPU(unsigned, mce_poll_count);
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2009-05-27 21:56:52 +02:00
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2007-10-17 18:04:40 +02:00
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extern atomic_t mce_entry;
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2009-02-12 13:49:34 +01:00
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typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
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DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
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2009-02-12 13:43:23 +01:00
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enum mcp_flags {
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MCP_TIMESTAMP = (1 << 0), /* log time stamp */
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MCP_UC = (1 << 1), /* log uncorrected errors */
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2009-04-07 17:06:55 +02:00
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MCP_DONTLOG = (1 << 2), /* only clear, don't log */
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2009-02-12 13:43:23 +01:00
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};
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2009-05-28 19:05:33 +02:00
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void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
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2009-02-12 13:43:23 +01:00
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2009-05-27 21:56:58 +02:00
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int mce_notify_irq(void);
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x86, mce: support action-optional machine checks
Newer Intel CPUs support a new class of machine checks called recoverable
action optional.
Action Optional means that the CPU detected some form of corruption in
the background and tells the OS about using a machine check
exception. The OS can then take appropiate action, like killing the
process with the corrupted data or logging the event properly to disk.
This is done by the new generic high level memory failure handler added
in a earlier patch. The high level handler takes the address with the
failed memory and does the appropiate action, like killing the process.
In this version of the patch the high level handler is stubbed out
with a weak function to not create a direct dependency on the hwpoison
branch.
The high level handler cannot be directly called from the machine check
exception though, because it has to run in a defined process context to
be able to sleep when taking VM locks (it is not expected to sleep for a
long time, just do so in some exceptional cases like lock contention)
Thus the MCE handler has to queue a work item for process context,
trigger process context and then call the high level handler from there.
This patch adds two path to process context: through a per thread kernel
exit notify_user() callback or through a high priority work item.
The first runs when the process exits back to user space, the other when
it goes to sleep and there is no higher priority process.
The machine check handler will schedule both, and whoever runs first
will grab the event. This is done because quick reaction to this
event is critical to avoid a potential more fatal machine check
when the corruption is consumed.
There is a simple lock less ring buffer to queue the corrupted
addresses between the exception handler and the process context handler.
Then in process context it just calls the high level VM code with
the corrupted PFNs.
The code adds the required code to extract the failed address from
the CPU's machine check registers. It doesn't try to handle all
possible cases -- the specification has 6 different ways to specify
memory address -- but only the linear address.
Most of the required checking has been already done earlier in the
mce_severity rule checking engine. Following the Intel
recommendations Action Optional errors are only enabled for known
situations (encoded in MCACODs). The errors are ignored otherwise,
because they are action optional.
v2: Improve comment, disable preemption while processing ring buffer
(reported by Ying Huang)
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-05-27 21:56:59 +02:00
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void mce_notify_process(void);
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2007-10-17 18:04:40 +02:00
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2009-04-29 19:31:00 +02:00
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DECLARE_PER_CPU(struct mce, injectm);
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2011-11-03 19:46:47 +01:00
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extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
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const char __user *ubuf,
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size_t usize, loff_t *off));
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2009-04-29 19:31:00 +02:00
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2009-06-15 10:27:47 +02:00
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/*
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* Exception handler
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*/
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/* Call the installed machine check handler for this CPU setup. */
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extern void (*machine_check_vector)(struct pt_regs *, long error_code);
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void do_machine_check(struct pt_regs *, long);
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/*
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* Threshold handler
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*/
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2007-10-17 18:04:40 +02:00
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2009-02-12 13:49:31 +01:00
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extern void (*mce_threshold_vector)(void);
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2009-06-15 10:27:47 +02:00
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extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
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2009-02-12 13:49:31 +01:00
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2009-06-15 10:24:40 +02:00
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/*
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* Thermal handler
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*/
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void intel_init_thermal(struct cpuinfo_x86 *c);
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void mce_log_therm_throt_event(__u64 status);
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2009-11-10 02:38:24 +01:00
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2011-01-03 12:52:04 +01:00
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/* Interrupt Handler for core thermal thresholds */
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extern int (*platform_thermal_notify)(__u64 msr_val);
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2009-11-10 02:38:24 +01:00
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#ifdef CONFIG_X86_THERMAL_VECTOR
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extern void mcheck_intel_therm_init(void);
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#else
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static inline void mcheck_intel_therm_init(void) { }
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#endif
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ACPI, APEI, Generic Hardware Error Source memory error support
Generic Hardware Error Source provides a way to report platform
hardware errors (such as that from chipset). It works in so called
"Firmware First" mode, that is, hardware errors are reported to
firmware firstly, then reported to Linux by firmware. This way, some
non-standard hardware error registers or non-standard hardware link
can be checked by firmware to produce more valuable hardware error
information for Linux.
Now, only SCI notification type and memory errors are supported. More
notification type and hardware error type will be added later. These
memory errors are reported to user space through /dev/mcelog via
faking a corrected Machine Check, so that the error memory page can be
offlined by /sbin/mcelog if the error count for one page is beyond the
threshold.
On some machines, Machine Check can not report physical address for
some corrected memory errors, but GHES can do that. So this simplified
GHES is implemented firstly.
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2010-05-18 08:35:20 +02:00
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/*
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* Used by APEI to report memory error via /dev/mcelog
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*/
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struct cper_sec_mem_err;
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extern void apei_mce_report_mem_error(int corrected,
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struct cper_sec_mem_err *mem_err);
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2007-10-17 18:04:40 +02:00
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#endif /* __KERNEL__ */
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2008-10-23 07:26:29 +02:00
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#endif /* _ASM_X86_MCE_H */
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