2019-04-21 04:26:56 +02:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2015-07-24 07:24:41 +02:00
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Henry Chen <henryc.chen@mediatek.com>
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*/
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#ifndef __MT6311_REGULATOR_H__
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#define __MT6311_REGULATOR_H__
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#define MT6311_SWCID 0x01
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#define MT6311_TOP_INT_CON 0x18
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#define MT6311_TOP_INT_MON 0x19
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#define MT6311_VDVFS11_CON0 0x87
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#define MT6311_VDVFS11_CON7 0x88
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#define MT6311_VDVFS11_CON8 0x89
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#define MT6311_VDVFS11_CON9 0x8A
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#define MT6311_VDVFS11_CON10 0x8B
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#define MT6311_VDVFS11_CON11 0x8C
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#define MT6311_VDVFS11_CON12 0x8D
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#define MT6311_VDVFS11_CON13 0x8E
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#define MT6311_VDVFS11_CON14 0x8F
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#define MT6311_VDVFS11_CON15 0x90
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#define MT6311_VDVFS11_CON16 0x91
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#define MT6311_VDVFS11_CON17 0x92
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#define MT6311_VDVFS11_CON18 0x93
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#define MT6311_VDVFS11_CON19 0x94
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#define MT6311_LDO_CON0 0xCC
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#define MT6311_LDO_OCFB0 0xCD
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#define MT6311_LDO_CON2 0xCE
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#define MT6311_LDO_CON3 0xCF
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#define MT6311_LDO_CON4 0xD0
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#define MT6311_FQMTR_CON0 0xD1
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#define MT6311_FQMTR_CON1 0xD2
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#define MT6311_FQMTR_CON2 0xD3
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#define MT6311_FQMTR_CON3 0xD4
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#define MT6311_FQMTR_CON4 0xD5
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#define MT6311_PMIC_RG_INT_POL_MASK 0x1
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#define MT6311_PMIC_RG_INT_EN_MASK 0x2
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#define MT6311_PMIC_RG_BUCK_OC_INT_STATUS_MASK 0x10
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#define MT6311_PMIC_VDVFS11_EN_CTRL_MASK 0x1
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#define MT6311_PMIC_VDVFS11_VOSEL_CTRL_MASK 0x2
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#define MT6311_PMIC_VDVFS11_EN_SEL_MASK 0x3
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#define MT6311_PMIC_VDVFS11_VOSEL_SEL_MASK 0xc
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#define MT6311_PMIC_VDVFS11_EN_MASK 0x1
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#define MT6311_PMIC_VDVFS11_VOSEL_MASK 0x7F
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#define MT6311_PMIC_VDVFS11_VOSEL_ON_MASK 0x7F
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#define MT6311_PMIC_VDVFS11_VOSEL_SLEEP_MASK 0x7F
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#define MT6311_PMIC_NI_VDVFS11_VOSEL_MASK 0x7F
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#define MT6311_PMIC_RG_VBIASN_EN_MASK 0x1
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#endif
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