License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 15:07:57 +01:00
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|
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// SPDX-License-Identifier: GPL-2.0
|
2007-07-28 07:39:14 +02:00
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/* iommu.c: Generic sparc64 IOMMU support.
|
2005-04-17 00:20:36 +02:00
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*
|
2008-02-09 03:05:46 +01:00
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* Copyright (C) 1999, 2007, 2008 David S. Miller (davem@davemloft.net)
|
2005-04-17 00:20:36 +02:00
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* Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
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*/
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#include <linux/kernel.h>
|
2011-07-22 19:18:16 +02:00
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#include <linux/export.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 09:04:11 +01:00
|
|
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#include <linux/slab.h>
|
2005-05-11 20:37:00 +02:00
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|
#include <linux/delay.h>
|
2007-07-28 07:39:14 +02:00
|
|
|
#include <linux/device.h>
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|
|
|
#include <linux/dma-mapping.h>
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|
|
|
#include <linux/errno.h>
|
2008-02-09 03:05:46 +01:00
|
|
|
#include <linux/iommu-helper.h>
|
2009-12-16 01:48:28 +01:00
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|
|
#include <linux/bitmap.h>
|
2018-04-03 15:34:58 +02:00
|
|
|
#include <asm/iommu-common.h>
|
2007-07-28 07:39:14 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_PCI
|
2007-05-08 09:43:56 +02:00
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|
#include <linux/pci.h>
|
2007-07-28 07:39:14 +02:00
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|
#endif
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
#include <asm/iommu.h>
|
2005-04-17 00:20:36 +02:00
|
|
|
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|
|
|
#include "iommu_common.h"
|
2014-05-16 23:25:58 +02:00
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|
|
#include "kernel.h"
|
2005-04-17 00:20:36 +02:00
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|
2007-07-28 07:39:14 +02:00
|
|
|
#define STC_CTXMATCH_ADDR(STC, CTX) \
|
2005-04-17 00:20:36 +02:00
|
|
|
((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
|
2007-07-28 07:39:14 +02:00
|
|
|
#define STC_FLUSHFLAG_INIT(STC) \
|
|
|
|
(*((STC)->strbuf_flushflag) = 0UL)
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|
#define STC_FLUSHFLAG_SET(STC) \
|
|
|
|
(*((STC)->strbuf_flushflag) != 0UL)
|
2005-04-17 00:20:36 +02:00
|
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|
|
2007-07-28 07:39:14 +02:00
|
|
|
#define iommu_read(__reg) \
|
2005-04-17 00:20:36 +02:00
|
|
|
({ u64 __ret; \
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|
|
__asm__ __volatile__("ldxa [%1] %2, %0" \
|
|
|
|
: "=r" (__ret) \
|
|
|
|
: "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
|
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|
|
: "memory"); \
|
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|
|
__ret; \
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|
|
})
|
2007-07-28 07:39:14 +02:00
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|
#define iommu_write(__reg, __val) \
|
2005-04-17 00:20:36 +02:00
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__asm__ __volatile__("stxa %0, [%1] %2" \
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|
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: /* no outputs */ \
|
|
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: "r" (__val), "r" (__reg), \
|
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|
|
"i" (ASI_PHYS_BYPASS_EC_E))
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|
/* Must be invoked under the IOMMU lock. */
|
2015-04-09 21:33:31 +02:00
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|
|
static void iommu_flushall(struct iommu_map_table *iommu_map_table)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2015-04-09 21:33:31 +02:00
|
|
|
struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl);
|
2007-05-03 02:31:36 +02:00
|
|
|
if (iommu->iommu_flushinv) {
|
2007-07-28 07:39:14 +02:00
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|
iommu_write(iommu->iommu_flushinv, ~(u64)0);
|
2007-05-03 02:31:36 +02:00
|
|
|
} else {
|
|
|
|
unsigned long tag;
|
|
|
|
int entry;
|
2005-04-17 00:20:36 +02:00
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|
2007-07-28 07:39:14 +02:00
|
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|
tag = iommu->iommu_tags;
|
2007-05-03 02:31:36 +02:00
|
|
|
for (entry = 0; entry < 16; entry++) {
|
2007-07-28 07:39:14 +02:00
|
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|
iommu_write(tag, 0);
|
2007-05-03 02:31:36 +02:00
|
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|
tag += 8;
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|
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|
}
|
2005-04-17 00:20:36 +02:00
|
|
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|
2007-05-03 02:31:36 +02:00
|
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|
/* Ensure completion of previous PIO writes. */
|
2007-07-28 07:39:14 +02:00
|
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|
(void) iommu_read(iommu->write_complete_reg);
|
2007-05-03 02:31:36 +02:00
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
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|
|
|
#define IOPTE_CONSISTENT(CTX) \
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|
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|
(IOPTE_VALID | IOPTE_CACHE | \
|
|
|
|
(((CTX) << 47) & IOPTE_CONTEXT))
|
|
|
|
|
|
|
|
#define IOPTE_STREAMING(CTX) \
|
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|
|
(IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
|
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|
/* Existing mappings are never marked invalid, instead they
|
|
|
|
* are pointed to a dummy page.
|
|
|
|
*/
|
|
|
|
#define IOPTE_IS_DUMMY(iommu, iopte) \
|
|
|
|
((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
|
|
|
|
|
2007-04-27 06:08:21 +02:00
|
|
|
static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
unsigned long val = iopte_val(*iopte);
|
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|
val &= ~IOPTE_PAGE;
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|
val |= iommu->dummy_page_pa;
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|
iopte_val(*iopte) = val;
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|
}
|
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|
2007-07-28 07:39:14 +02:00
|
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|
int iommu_table_init(struct iommu *iommu, int tsbsize,
|
2008-03-19 12:52:48 +01:00
|
|
|
u32 dma_offset, u32 dma_addr_mask,
|
|
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int numa_node)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2008-03-19 12:52:48 +01:00
|
|
|
unsigned long i, order, sz, num_tsb_entries;
|
|
|
|
struct page *page;
|
2005-10-14 07:15:24 +02:00
|
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num_tsb_entries = tsbsize / sizeof(iopte_t);
|
2005-10-14 06:10:08 +02:00
|
|
|
|
|
|
|
/* Setup initial software IOMMU state. */
|
|
|
|
spin_lock_init(&iommu->lock);
|
|
|
|
iommu->ctx_lowest_free = 1;
|
2015-04-09 21:33:31 +02:00
|
|
|
iommu->tbl.table_map_base = dma_offset;
|
2005-10-14 06:10:08 +02:00
|
|
|
iommu->dma_addr_mask = dma_addr_mask;
|
|
|
|
|
2005-10-14 07:15:24 +02:00
|
|
|
/* Allocate and initialize the free area map. */
|
|
|
|
sz = num_tsb_entries / 8;
|
|
|
|
sz = (sz + 7UL) & ~7UL;
|
2015-04-09 21:33:31 +02:00
|
|
|
iommu->tbl.map = kmalloc_node(sz, GFP_KERNEL, numa_node);
|
|
|
|
if (!iommu->tbl.map)
|
2007-07-28 07:39:14 +02:00
|
|
|
return -ENOMEM;
|
2015-04-09 21:33:31 +02:00
|
|
|
memset(iommu->tbl.map, 0, sz);
|
2015-03-13 01:02:36 +01:00
|
|
|
|
2015-04-09 21:33:31 +02:00
|
|
|
iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
|
|
|
|
(tlb_type != hypervisor ? iommu_flushall : NULL),
|
|
|
|
false, 1, false);
|
2008-02-09 03:05:46 +01:00
|
|
|
|
2005-10-14 06:10:08 +02:00
|
|
|
/* Allocate and initialize the dummy page which we
|
|
|
|
* set inactive IO PTEs to point to.
|
|
|
|
*/
|
2008-03-19 12:52:48 +01:00
|
|
|
page = alloc_pages_node(numa_node, GFP_KERNEL, 0);
|
|
|
|
if (!page) {
|
2007-07-28 07:39:14 +02:00
|
|
|
printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
|
|
|
|
goto out_free_map;
|
2005-10-14 06:10:08 +02:00
|
|
|
}
|
2008-03-19 12:52:48 +01:00
|
|
|
iommu->dummy_page = (unsigned long) page_address(page);
|
|
|
|
memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
|
2005-10-14 06:10:08 +02:00
|
|
|
iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
|
|
|
|
|
|
|
|
/* Now allocate and setup the IOMMU page table itself. */
|
|
|
|
order = get_order(tsbsize);
|
2008-03-19 12:52:48 +01:00
|
|
|
page = alloc_pages_node(numa_node, GFP_KERNEL, order);
|
|
|
|
if (!page) {
|
2007-07-28 07:39:14 +02:00
|
|
|
printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
|
|
|
|
goto out_free_dummy_page;
|
2005-10-14 06:10:08 +02:00
|
|
|
}
|
2008-03-19 12:52:48 +01:00
|
|
|
iommu->page_table = (iopte_t *)page_address(page);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-10-14 07:15:24 +02:00
|
|
|
for (i = 0; i < num_tsb_entries; i++)
|
2005-04-17 00:20:36 +02:00
|
|
|
iopte_make_dummy(iommu, &iommu->page_table[i]);
|
2007-07-28 07:39:14 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_free_dummy_page:
|
|
|
|
free_page(iommu->dummy_page);
|
|
|
|
iommu->dummy_page = 0UL;
|
|
|
|
|
|
|
|
out_free_map:
|
2015-04-09 21:33:31 +02:00
|
|
|
kfree(iommu->tbl.map);
|
|
|
|
iommu->tbl.map = NULL;
|
2007-07-28 07:39:14 +02:00
|
|
|
|
|
|
|
return -ENOMEM;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2015-04-09 21:33:31 +02:00
|
|
|
static inline iopte_t *alloc_npages(struct device *dev,
|
|
|
|
struct iommu *iommu,
|
2008-02-09 03:05:46 +01:00
|
|
|
unsigned long npages)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2008-02-09 03:05:46 +01:00
|
|
|
unsigned long entry;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2015-04-09 21:33:31 +02:00
|
|
|
entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
|
|
|
|
(unsigned long)(-1), 0);
|
2015-11-04 20:30:57 +01:00
|
|
|
if (unlikely(entry == IOMMU_ERROR_CODE))
|
2005-10-14 07:15:24 +02:00
|
|
|
return NULL;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-10-14 07:15:24 +02:00
|
|
|
return iommu->page_table + entry;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2007-04-27 06:08:21 +02:00
|
|
|
static int iommu_alloc_ctx(struct iommu *iommu)
|
2005-06-01 01:57:59 +02:00
|
|
|
{
|
|
|
|
int lowest = iommu->ctx_lowest_free;
|
2011-02-08 05:59:50 +01:00
|
|
|
int n = find_next_zero_bit(iommu->ctx_bitmap, IOMMU_NUM_CTXS, lowest);
|
2005-06-01 01:57:59 +02:00
|
|
|
|
2011-02-08 05:59:50 +01:00
|
|
|
if (unlikely(n == IOMMU_NUM_CTXS)) {
|
2005-06-01 01:57:59 +02:00
|
|
|
n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
|
|
|
|
if (unlikely(n == lowest)) {
|
|
|
|
printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
|
|
|
|
n = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (n)
|
|
|
|
__set_bit(n, iommu->ctx_bitmap);
|
|
|
|
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
2007-04-27 06:08:21 +02:00
|
|
|
static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
|
2005-06-01 01:57:59 +02:00
|
|
|
{
|
|
|
|
if (likely(ctx)) {
|
|
|
|
__clear_bit(ctx, iommu->ctx_bitmap);
|
|
|
|
if (ctx < iommu->ctx_lowest_free)
|
|
|
|
iommu->ctx_lowest_free = ctx;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
|
2012-03-27 14:56:55 +02:00
|
|
|
dma_addr_t *dma_addrp, gfp_t gfp,
|
2016-08-03 22:46:00 +02:00
|
|
|
unsigned long attrs)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2015-04-09 21:33:31 +02:00
|
|
|
unsigned long order, first_page;
|
2007-04-27 06:08:21 +02:00
|
|
|
struct iommu *iommu;
|
2008-03-19 12:52:48 +01:00
|
|
|
struct page *page;
|
|
|
|
int npages, nid;
|
2005-04-17 00:20:36 +02:00
|
|
|
iopte_t *iopte;
|
|
|
|
void *ret;
|
|
|
|
|
|
|
|
size = IO_PAGE_ALIGN(size);
|
|
|
|
order = get_order(size);
|
|
|
|
if (order >= 10)
|
|
|
|
return NULL;
|
|
|
|
|
2008-03-19 12:52:48 +01:00
|
|
|
nid = dev->archdata.numa_node;
|
|
|
|
page = alloc_pages_node(nid, gfp, order);
|
|
|
|
if (unlikely(!page))
|
2005-04-17 00:20:36 +02:00
|
|
|
return NULL;
|
2008-03-19 12:52:48 +01:00
|
|
|
|
|
|
|
first_page = (unsigned long) page_address(page);
|
2005-04-17 00:20:36 +02:00
|
|
|
memset((char *)first_page, 0, PAGE_SIZE << order);
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu = dev->archdata.iommu;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-02-09 03:05:46 +01:00
|
|
|
iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT);
|
2005-10-14 07:15:24 +02:00
|
|
|
|
|
|
|
if (unlikely(iopte == NULL)) {
|
2005-04-17 00:20:36 +02:00
|
|
|
free_pages(first_page, order);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2015-04-09 21:33:31 +02:00
|
|
|
*dma_addrp = (iommu->tbl.table_map_base +
|
2005-04-17 00:20:36 +02:00
|
|
|
((iopte - iommu->page_table) << IO_PAGE_SHIFT));
|
|
|
|
ret = (void *) first_page;
|
|
|
|
npages = size >> IO_PAGE_SHIFT;
|
|
|
|
first_page = __pa(first_page);
|
|
|
|
while (npages--) {
|
2005-10-14 07:15:24 +02:00
|
|
|
iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
|
2005-04-17 00:20:36 +02:00
|
|
|
IOPTE_WRITE |
|
|
|
|
(first_page & IOPTE_PAGE));
|
|
|
|
iopte++;
|
|
|
|
first_page += IO_PAGE_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
static void dma_4u_free_coherent(struct device *dev, size_t size,
|
2012-03-27 14:56:55 +02:00
|
|
|
void *cpu, dma_addr_t dvma,
|
2016-08-03 22:46:00 +02:00
|
|
|
unsigned long attrs)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2007-04-27 06:08:21 +02:00
|
|
|
struct iommu *iommu;
|
2015-04-09 21:33:31 +02:00
|
|
|
unsigned long order, npages;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu = dev->archdata.iommu;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2015-11-04 20:30:57 +01:00
|
|
|
iommu_tbl_range_free(&iommu->tbl, dvma, npages, IOMMU_ERROR_CODE);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
order = get_order(size);
|
|
|
|
if (order < 10)
|
|
|
|
free_pages((unsigned long)cpu, order);
|
|
|
|
}
|
|
|
|
|
2009-05-14 18:23:10 +02:00
|
|
|
static dma_addr_t dma_4u_map_page(struct device *dev, struct page *page,
|
|
|
|
unsigned long offset, size_t sz,
|
2009-08-10 04:53:12 +02:00
|
|
|
enum dma_data_direction direction,
|
2016-08-03 22:46:00 +02:00
|
|
|
unsigned long attrs)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2007-04-27 06:08:21 +02:00
|
|
|
struct iommu *iommu;
|
|
|
|
struct strbuf *strbuf;
|
2005-04-17 00:20:36 +02:00
|
|
|
iopte_t *base;
|
|
|
|
unsigned long flags, npages, oaddr;
|
|
|
|
unsigned long i, base_paddr, ctx;
|
|
|
|
u32 bus_addr, ret;
|
|
|
|
unsigned long iopte_protection;
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu = dev->archdata.iommu;
|
|
|
|
strbuf = dev->archdata.stc;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
if (unlikely(direction == DMA_NONE))
|
2005-10-14 07:15:24 +02:00
|
|
|
goto bad_no_ctx;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-05-14 18:23:10 +02:00
|
|
|
oaddr = (unsigned long)(page_address(page) + offset);
|
2005-04-17 00:20:36 +02:00
|
|
|
npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
|
|
|
|
npages >>= IO_PAGE_SHIFT;
|
|
|
|
|
2015-04-18 21:31:25 +02:00
|
|
|
base = alloc_npages(dev, iommu, npages);
|
2015-04-09 21:33:31 +02:00
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
2005-10-14 07:15:24 +02:00
|
|
|
ctx = 0;
|
|
|
|
if (iommu->iommu_ctxflush)
|
|
|
|
ctx = iommu_alloc_ctx(iommu);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-10-14 07:15:24 +02:00
|
|
|
if (unlikely(!base))
|
2005-04-17 00:20:36 +02:00
|
|
|
goto bad;
|
2005-10-14 07:15:24 +02:00
|
|
|
|
2015-04-09 21:33:31 +02:00
|
|
|
bus_addr = (iommu->tbl.table_map_base +
|
2005-04-17 00:20:36 +02:00
|
|
|
((base - iommu->page_table) << IO_PAGE_SHIFT));
|
|
|
|
ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
|
|
|
|
base_paddr = __pa(oaddr & IO_PAGE_MASK);
|
|
|
|
if (strbuf->strbuf_enabled)
|
|
|
|
iopte_protection = IOPTE_STREAMING(ctx);
|
|
|
|
else
|
|
|
|
iopte_protection = IOPTE_CONSISTENT(ctx);
|
2007-07-28 07:39:14 +02:00
|
|
|
if (direction != DMA_TO_DEVICE)
|
2005-04-17 00:20:36 +02:00
|
|
|
iopte_protection |= IOPTE_WRITE;
|
|
|
|
|
|
|
|
for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
|
|
|
|
iopte_val(*base) = iopte_protection | base_paddr;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
bad:
|
2005-10-14 07:15:24 +02:00
|
|
|
iommu_free_ctx(iommu, ctx);
|
|
|
|
bad_no_ctx:
|
|
|
|
if (printk_ratelimit())
|
|
|
|
WARN_ON(1);
|
2017-05-21 13:33:44 +02:00
|
|
|
return SPARC_MAPPING_ERROR;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu,
|
|
|
|
u32 vaddr, unsigned long ctx, unsigned long npages,
|
|
|
|
enum dma_data_direction direction)
|
2005-05-11 20:37:00 +02:00
|
|
|
{
|
|
|
|
int limit;
|
|
|
|
|
|
|
|
if (strbuf->strbuf_ctxflush &&
|
|
|
|
iommu->iommu_ctxflush) {
|
|
|
|
unsigned long matchreg, flushreg;
|
2005-06-01 01:57:59 +02:00
|
|
|
u64 val;
|
2005-05-11 20:37:00 +02:00
|
|
|
|
|
|
|
flushreg = strbuf->strbuf_ctxflush;
|
2007-07-28 07:39:14 +02:00
|
|
|
matchreg = STC_CTXMATCH_ADDR(strbuf, ctx);
|
2005-05-11 20:37:00 +02:00
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu_write(flushreg, ctx);
|
|
|
|
val = iommu_read(matchreg);
|
2005-06-01 04:13:52 +02:00
|
|
|
val &= 0xffff;
|
|
|
|
if (!val)
|
2005-06-01 01:57:59 +02:00
|
|
|
goto do_flush_sync;
|
|
|
|
|
|
|
|
while (val) {
|
|
|
|
if (val & 0x1)
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu_write(flushreg, ctx);
|
2005-06-01 01:57:59 +02:00
|
|
|
val >>= 1;
|
2005-05-20 20:40:32 +02:00
|
|
|
}
|
2007-07-28 07:39:14 +02:00
|
|
|
val = iommu_read(matchreg);
|
2005-06-01 01:57:59 +02:00
|
|
|
if (unlikely(val)) {
|
2007-07-28 07:39:14 +02:00
|
|
|
printk(KERN_WARNING "strbuf_flush: ctx flush "
|
2009-01-06 22:19:28 +01:00
|
|
|
"timeout matchreg[%llx] ctx[%lx]\n",
|
2005-06-01 01:57:59 +02:00
|
|
|
val, ctx);
|
|
|
|
goto do_page_flush;
|
|
|
|
}
|
2005-05-11 20:37:00 +02:00
|
|
|
} else {
|
|
|
|
unsigned long i;
|
|
|
|
|
2005-06-01 01:57:59 +02:00
|
|
|
do_page_flush:
|
2005-05-11 20:37:00 +02:00
|
|
|
for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu_write(strbuf->strbuf_pflush, vaddr);
|
2005-05-11 20:37:00 +02:00
|
|
|
}
|
|
|
|
|
2005-06-01 01:57:59 +02:00
|
|
|
do_flush_sync:
|
|
|
|
/* If the device could not have possibly put dirty data into
|
|
|
|
* the streaming cache, no flush-flag synchronization needs
|
|
|
|
* to be performed.
|
|
|
|
*/
|
2007-07-28 07:39:14 +02:00
|
|
|
if (direction == DMA_TO_DEVICE)
|
2005-06-01 01:57:59 +02:00
|
|
|
return;
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
STC_FLUSHFLAG_INIT(strbuf);
|
|
|
|
iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
|
|
|
|
(void) iommu_read(iommu->write_complete_reg);
|
2005-05-11 20:37:00 +02:00
|
|
|
|
2005-05-20 20:40:32 +02:00
|
|
|
limit = 100000;
|
2007-07-28 07:39:14 +02:00
|
|
|
while (!STC_FLUSHFLAG_SET(strbuf)) {
|
2005-05-11 20:37:00 +02:00
|
|
|
limit--;
|
|
|
|
if (!limit)
|
|
|
|
break;
|
2005-05-20 20:40:32 +02:00
|
|
|
udelay(1);
|
2005-08-29 21:46:22 +02:00
|
|
|
rmb();
|
2005-05-11 20:37:00 +02:00
|
|
|
}
|
|
|
|
if (!limit)
|
2007-07-28 07:39:14 +02:00
|
|
|
printk(KERN_WARNING "strbuf_flush: flushflag timeout "
|
2005-05-11 20:37:00 +02:00
|
|
|
"vaddr[%08x] ctx[%lx] npages[%ld]\n",
|
|
|
|
vaddr, ctx, npages);
|
|
|
|
}
|
|
|
|
|
2009-05-14 18:23:10 +02:00
|
|
|
static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
|
2009-08-10 04:53:12 +02:00
|
|
|
size_t sz, enum dma_data_direction direction,
|
2016-08-03 22:46:00 +02:00
|
|
|
unsigned long attrs)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2007-04-27 06:08:21 +02:00
|
|
|
struct iommu *iommu;
|
|
|
|
struct strbuf *strbuf;
|
2005-04-17 00:20:36 +02:00
|
|
|
iopte_t *base;
|
2005-10-14 07:15:24 +02:00
|
|
|
unsigned long flags, npages, ctx, i;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
if (unlikely(direction == DMA_NONE)) {
|
2005-10-14 07:15:24 +02:00
|
|
|
if (printk_ratelimit())
|
|
|
|
WARN_ON(1);
|
|
|
|
return;
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu = dev->archdata.iommu;
|
|
|
|
strbuf = dev->archdata.stc;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
|
|
|
|
npages >>= IO_PAGE_SHIFT;
|
|
|
|
base = iommu->page_table +
|
2015-04-09 21:33:31 +02:00
|
|
|
((bus_addr - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT);
|
2005-04-17 00:20:36 +02:00
|
|
|
bus_addr &= IO_PAGE_MASK;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
|
|
|
|
/* Record the context, if any. */
|
|
|
|
ctx = 0;
|
|
|
|
if (iommu->iommu_ctxflush)
|
|
|
|
ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
|
|
|
|
|
|
|
|
/* Step 1: Kick data out of streaming buffers if necessary. */
|
2016-12-15 00:05:15 +01:00
|
|
|
if (strbuf->strbuf_enabled && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
|
2007-07-28 07:39:14 +02:00
|
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx,
|
|
|
|
npages, direction);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-10-14 07:15:24 +02:00
|
|
|
/* Step 2: Clear out TSB entries. */
|
|
|
|
for (i = 0; i < npages; i++)
|
|
|
|
iopte_make_dummy(iommu, base + i);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-06-01 01:57:59 +02:00
|
|
|
iommu_free_ctx(iommu, ctx);
|
2015-04-18 21:31:25 +02:00
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
2015-04-09 21:33:31 +02:00
|
|
|
|
2015-11-04 20:30:57 +01:00
|
|
|
iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
|
2009-08-10 04:53:12 +02:00
|
|
|
int nelems, enum dma_data_direction direction,
|
2016-08-03 22:46:00 +02:00
|
|
|
unsigned long attrs)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2008-02-09 12:11:01 +01:00
|
|
|
struct scatterlist *s, *outs, *segstart;
|
|
|
|
unsigned long flags, handle, prot, ctx;
|
|
|
|
dma_addr_t dma_next = 0, dma_addr;
|
|
|
|
unsigned int max_seg_size;
|
2008-03-28 23:55:41 +01:00
|
|
|
unsigned long seg_boundary_size;
|
2008-02-09 12:11:01 +01:00
|
|
|
int outcount, incount, i;
|
2007-04-27 06:08:21 +02:00
|
|
|
struct strbuf *strbuf;
|
2008-02-06 12:50:26 +01:00
|
|
|
struct iommu *iommu;
|
2008-03-28 23:55:41 +01:00
|
|
|
unsigned long base_shift;
|
2008-02-09 12:11:01 +01:00
|
|
|
|
|
|
|
BUG_ON(direction == DMA_NONE);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu = dev->archdata.iommu;
|
|
|
|
strbuf = dev->archdata.stc;
|
2008-02-09 12:11:01 +01:00
|
|
|
if (nelems == 0 || !iommu)
|
|
|
|
return 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
|
2005-10-14 07:15:24 +02:00
|
|
|
ctx = 0;
|
|
|
|
if (iommu->iommu_ctxflush)
|
|
|
|
ctx = iommu_alloc_ctx(iommu);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
if (strbuf->strbuf_enabled)
|
2008-02-09 12:11:01 +01:00
|
|
|
prot = IOPTE_STREAMING(ctx);
|
2005-04-17 00:20:36 +02:00
|
|
|
else
|
2008-02-09 12:11:01 +01:00
|
|
|
prot = IOPTE_CONSISTENT(ctx);
|
2007-07-28 07:39:14 +02:00
|
|
|
if (direction != DMA_TO_DEVICE)
|
2008-02-09 12:11:01 +01:00
|
|
|
prot |= IOPTE_WRITE;
|
|
|
|
|
|
|
|
outs = s = segstart = &sglist[0];
|
|
|
|
outcount = 1;
|
|
|
|
incount = nelems;
|
|
|
|
handle = 0;
|
|
|
|
|
|
|
|
/* Init first segment length for backout at failure */
|
|
|
|
outs->dma_length = 0;
|
|
|
|
|
|
|
|
max_seg_size = dma_get_max_seg_size(dev);
|
2008-03-28 23:55:41 +01:00
|
|
|
seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
|
|
|
|
IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
|
2015-04-09 21:33:31 +02:00
|
|
|
base_shift = iommu->tbl.table_map_base >> IO_PAGE_SHIFT;
|
2008-02-09 12:11:01 +01:00
|
|
|
for_each_sg(sglist, s, nelems, i) {
|
2008-03-28 23:55:41 +01:00
|
|
|
unsigned long paddr, npages, entry, out_entry = 0, slen;
|
2008-02-09 12:11:01 +01:00
|
|
|
iopte_t *base;
|
|
|
|
|
|
|
|
slen = s->length;
|
|
|
|
/* Sanity check */
|
|
|
|
if (slen == 0) {
|
|
|
|
dma_next = 0;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
/* Allocate iommu entries for that segment */
|
|
|
|
paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
|
2008-10-16 07:02:14 +02:00
|
|
|
npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
|
2015-04-09 21:33:31 +02:00
|
|
|
entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages,
|
|
|
|
&handle, (unsigned long)(-1), 0);
|
2008-02-09 12:11:01 +01:00
|
|
|
|
|
|
|
/* Handle failure */
|
2015-11-04 20:30:57 +01:00
|
|
|
if (unlikely(entry == IOMMU_ERROR_CODE)) {
|
2008-02-09 12:11:01 +01:00
|
|
|
if (printk_ratelimit())
|
|
|
|
printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
|
|
|
|
" npages %lx\n", iommu, paddr, npages);
|
|
|
|
goto iommu_map_failed;
|
|
|
|
}
|
2005-10-14 07:15:24 +02:00
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
base = iommu->page_table + entry;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
/* Convert entry to a dma_addr_t */
|
2015-04-09 21:33:31 +02:00
|
|
|
dma_addr = iommu->tbl.table_map_base +
|
2008-02-09 12:11:01 +01:00
|
|
|
(entry << IO_PAGE_SHIFT);
|
|
|
|
dma_addr |= (s->offset & ~IO_PAGE_MASK);
|
2008-02-06 12:50:26 +01:00
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
/* Insert into HW table */
|
2008-02-06 12:50:26 +01:00
|
|
|
paddr &= IO_PAGE_MASK;
|
2008-02-09 12:11:01 +01:00
|
|
|
while (npages--) {
|
|
|
|
iopte_val(*base) = prot | paddr;
|
2008-02-06 12:50:26 +01:00
|
|
|
base++;
|
|
|
|
paddr += IO_PAGE_SIZE;
|
|
|
|
}
|
2008-02-09 12:11:01 +01:00
|
|
|
|
|
|
|
/* If we are in an open segment, try merging */
|
|
|
|
if (segstart != s) {
|
|
|
|
/* We cannot merge if:
|
|
|
|
* - allocated dma_addr isn't contiguous to previous allocation
|
|
|
|
*/
|
|
|
|
if ((dma_addr != dma_next) ||
|
2008-03-28 23:55:41 +01:00
|
|
|
(outs->dma_length + s->length > max_seg_size) ||
|
|
|
|
(is_span_boundary(out_entry, base_shift,
|
|
|
|
seg_boundary_size, outs, s))) {
|
2008-02-09 12:11:01 +01:00
|
|
|
/* Can't merge: create a new segment */
|
|
|
|
segstart = s;
|
|
|
|
outcount++;
|
|
|
|
outs = sg_next(outs);
|
|
|
|
} else {
|
|
|
|
outs->dma_length += s->length;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (segstart == s) {
|
|
|
|
/* This is a new segment, fill entries */
|
|
|
|
outs->dma_address = dma_addr;
|
|
|
|
outs->dma_length = slen;
|
2008-03-28 23:55:41 +01:00
|
|
|
out_entry = entry;
|
2008-02-09 12:11:01 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Calculate next page pointer for contiguous check */
|
|
|
|
dma_next = dma_addr + slen;
|
2008-02-06 12:50:26 +01:00
|
|
|
}
|
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
|
|
|
if (outcount < incount) {
|
|
|
|
outs = sg_next(outs);
|
2017-05-21 13:33:44 +02:00
|
|
|
outs->dma_address = SPARC_MAPPING_ERROR;
|
2008-02-09 12:11:01 +01:00
|
|
|
outs->dma_length = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return outcount;
|
|
|
|
|
|
|
|
iommu_map_failed:
|
|
|
|
for_each_sg(sglist, s, nelems, i) {
|
|
|
|
if (s->dma_length != 0) {
|
2008-03-26 06:44:10 +01:00
|
|
|
unsigned long vaddr, npages, entry, j;
|
2008-02-09 12:11:01 +01:00
|
|
|
iopte_t *base;
|
|
|
|
|
|
|
|
vaddr = s->dma_address & IO_PAGE_MASK;
|
2008-10-16 07:02:14 +02:00
|
|
|
npages = iommu_num_pages(s->dma_address, s->dma_length,
|
|
|
|
IO_PAGE_SIZE);
|
2008-02-09 12:11:01 +01:00
|
|
|
|
2015-04-09 21:33:31 +02:00
|
|
|
entry = (vaddr - iommu->tbl.table_map_base)
|
2008-02-09 12:11:01 +01:00
|
|
|
>> IO_PAGE_SHIFT;
|
|
|
|
base = iommu->page_table + entry;
|
|
|
|
|
2008-03-26 06:44:10 +01:00
|
|
|
for (j = 0; j < npages; j++)
|
|
|
|
iopte_make_dummy(iommu, base + j);
|
2008-02-09 12:11:01 +01:00
|
|
|
|
2015-04-09 21:33:31 +02:00
|
|
|
iommu_tbl_range_free(&iommu->tbl, vaddr, npages,
|
2015-11-04 20:30:57 +01:00
|
|
|
IOMMU_ERROR_CODE);
|
2015-04-09 21:33:31 +02:00
|
|
|
|
2017-05-21 13:33:44 +02:00
|
|
|
s->dma_address = SPARC_MAPPING_ERROR;
|
2008-02-09 12:11:01 +01:00
|
|
|
s->dma_length = 0;
|
|
|
|
}
|
|
|
|
if (s == outs)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-10-14 07:15:24 +02:00
|
|
|
return 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
/* If contexts are being used, they are the same in all of the mappings
|
|
|
|
* we make for a particular SG.
|
|
|
|
*/
|
2015-04-18 21:31:25 +02:00
|
|
|
static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg)
|
2008-02-09 12:11:01 +01:00
|
|
|
{
|
|
|
|
unsigned long ctx = 0;
|
|
|
|
|
|
|
|
if (iommu->iommu_ctxflush) {
|
|
|
|
iopte_t *base;
|
|
|
|
u32 bus_addr;
|
2015-04-09 21:33:31 +02:00
|
|
|
struct iommu_map_table *tbl = &iommu->tbl;
|
2008-02-09 12:11:01 +01:00
|
|
|
|
|
|
|
bus_addr = sg->dma_address & IO_PAGE_MASK;
|
|
|
|
base = iommu->page_table +
|
2015-04-09 21:33:31 +02:00
|
|
|
((bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT);
|
2008-02-09 12:11:01 +01:00
|
|
|
|
|
|
|
ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
|
|
|
|
}
|
|
|
|
return ctx;
|
|
|
|
}
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
2009-08-10 04:53:12 +02:00
|
|
|
int nelems, enum dma_data_direction direction,
|
2016-08-03 22:46:00 +02:00
|
|
|
unsigned long attrs)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2008-02-09 12:11:01 +01:00
|
|
|
unsigned long flags, ctx;
|
|
|
|
struct scatterlist *sg;
|
2007-04-27 06:08:21 +02:00
|
|
|
struct strbuf *strbuf;
|
2008-02-06 12:50:26 +01:00
|
|
|
struct iommu *iommu;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
BUG_ON(direction == DMA_NONE);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu = dev->archdata.iommu;
|
|
|
|
strbuf = dev->archdata.stc;
|
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
ctx = fetch_sg_ctx(iommu, sglist);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
sg = sglist;
|
|
|
|
while (nelems--) {
|
|
|
|
dma_addr_t dma_handle = sg->dma_address;
|
|
|
|
unsigned int len = sg->dma_length;
|
|
|
|
unsigned long npages, entry;
|
|
|
|
iopte_t *base;
|
|
|
|
int i;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
if (!len)
|
|
|
|
break;
|
2008-10-16 07:02:14 +02:00
|
|
|
npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2015-04-09 21:33:31 +02:00
|
|
|
entry = ((dma_handle - iommu->tbl.table_map_base)
|
2008-02-09 12:11:01 +01:00
|
|
|
>> IO_PAGE_SHIFT);
|
|
|
|
base = iommu->page_table + entry;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
dma_handle &= IO_PAGE_MASK;
|
2016-12-15 00:05:15 +01:00
|
|
|
if (strbuf->strbuf_enabled && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
|
2008-02-09 12:11:01 +01:00
|
|
|
strbuf_flush(strbuf, iommu, dma_handle, ctx,
|
|
|
|
npages, direction);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2008-02-09 12:11:01 +01:00
|
|
|
for (i = 0; i < npages; i++)
|
|
|
|
iopte_make_dummy(iommu, base + i);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2015-04-09 21:33:31 +02:00
|
|
|
iommu_tbl_range_free(&iommu->tbl, dma_handle, npages,
|
2015-11-04 20:30:57 +01:00
|
|
|
IOMMU_ERROR_CODE);
|
2008-02-09 12:11:01 +01:00
|
|
|
sg = sg_next(sg);
|
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-06-01 01:57:59 +02:00
|
|
|
iommu_free_ctx(iommu, ctx);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
}
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
static void dma_4u_sync_single_for_cpu(struct device *dev,
|
|
|
|
dma_addr_t bus_addr, size_t sz,
|
|
|
|
enum dma_data_direction direction)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2007-04-27 06:08:21 +02:00
|
|
|
struct iommu *iommu;
|
|
|
|
struct strbuf *strbuf;
|
2005-04-17 00:20:36 +02:00
|
|
|
unsigned long flags, ctx, npages;
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu = dev->archdata.iommu;
|
|
|
|
strbuf = dev->archdata.stc;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
if (!strbuf->strbuf_enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
|
|
|
|
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
|
|
|
|
npages >>= IO_PAGE_SHIFT;
|
|
|
|
bus_addr &= IO_PAGE_MASK;
|
|
|
|
|
|
|
|
/* Step 1: Record the context, if any. */
|
|
|
|
ctx = 0;
|
|
|
|
if (iommu->iommu_ctxflush &&
|
|
|
|
strbuf->strbuf_ctxflush) {
|
|
|
|
iopte_t *iopte;
|
2015-04-09 21:33:31 +02:00
|
|
|
struct iommu_map_table *tbl = &iommu->tbl;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
iopte = iommu->page_table +
|
2015-04-09 21:33:31 +02:00
|
|
|
((bus_addr - tbl->table_map_base)>>IO_PAGE_SHIFT);
|
2005-04-17 00:20:36 +02:00
|
|
|
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Step 2: Kick data out of streaming buffers. */
|
2007-07-28 07:39:14 +02:00
|
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
}
|
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
static void dma_4u_sync_sg_for_cpu(struct device *dev,
|
|
|
|
struct scatterlist *sglist, int nelems,
|
|
|
|
enum dma_data_direction direction)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2007-04-27 06:08:21 +02:00
|
|
|
struct iommu *iommu;
|
|
|
|
struct strbuf *strbuf;
|
2005-05-11 20:37:00 +02:00
|
|
|
unsigned long flags, ctx, npages, i;
|
2007-08-07 09:37:10 +02:00
|
|
|
struct scatterlist *sg, *sgprv;
|
2005-05-11 20:37:00 +02:00
|
|
|
u32 bus_addr;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-07-28 07:39:14 +02:00
|
|
|
iommu = dev->archdata.iommu;
|
|
|
|
strbuf = dev->archdata.stc;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
if (!strbuf->strbuf_enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
|
|
|
|
/* Step 1: Record the context, if any. */
|
|
|
|
ctx = 0;
|
|
|
|
if (iommu->iommu_ctxflush &&
|
|
|
|
strbuf->strbuf_ctxflush) {
|
|
|
|
iopte_t *iopte;
|
2015-04-09 21:33:31 +02:00
|
|
|
struct iommu_map_table *tbl = &iommu->tbl;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2015-04-09 21:33:31 +02:00
|
|
|
iopte = iommu->page_table + ((sglist[0].dma_address -
|
|
|
|
tbl->table_map_base) >> IO_PAGE_SHIFT);
|
2005-04-17 00:20:36 +02:00
|
|
|
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Step 2: Kick data out of streaming buffers. */
|
2005-05-11 20:37:00 +02:00
|
|
|
bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
|
2007-08-07 09:37:10 +02:00
|
|
|
sgprv = NULL;
|
|
|
|
for_each_sg(sglist, sg, nelems, i) {
|
|
|
|
if (sg->dma_length == 0)
|
2005-05-11 20:37:00 +02:00
|
|
|
break;
|
2007-08-07 09:37:10 +02:00
|
|
|
sgprv = sg;
|
|
|
|
}
|
|
|
|
|
|
|
|
npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length)
|
2005-05-11 20:37:00 +02:00
|
|
|
- bus_addr) >> IO_PAGE_SHIFT;
|
2007-07-28 07:39:14 +02:00
|
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
}
|
|
|
|
|
2017-05-21 13:33:44 +02:00
|
|
|
static int dma_4u_mapping_error(struct device *dev, dma_addr_t dma_addr)
|
|
|
|
{
|
|
|
|
return dma_addr == SPARC_MAPPING_ERROR;
|
|
|
|
}
|
|
|
|
|
2017-05-22 09:11:30 +02:00
|
|
|
static int dma_4u_supported(struct device *dev, u64 device_mask)
|
|
|
|
{
|
|
|
|
struct iommu *iommu = dev->archdata.iommu;
|
|
|
|
|
|
|
|
if (device_mask > DMA_BIT_MASK(32))
|
|
|
|
return 0;
|
|
|
|
if ((device_mask & iommu->dma_addr_mask) == iommu->dma_addr_mask)
|
|
|
|
return 1;
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
if (dev_is_pci(dev))
|
|
|
|
return pci64_dma_supported(to_pci_dev(dev), device_mask);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-20 22:04:01 +01:00
|
|
|
static const struct dma_map_ops sun4u_dma_ops = {
|
2012-03-27 14:56:55 +02:00
|
|
|
.alloc = dma_4u_alloc_coherent,
|
|
|
|
.free = dma_4u_free_coherent,
|
2009-05-14 18:23:10 +02:00
|
|
|
.map_page = dma_4u_map_page,
|
|
|
|
.unmap_page = dma_4u_unmap_page,
|
2007-07-28 07:39:14 +02:00
|
|
|
.map_sg = dma_4u_map_sg,
|
|
|
|
.unmap_sg = dma_4u_unmap_sg,
|
|
|
|
.sync_single_for_cpu = dma_4u_sync_single_for_cpu,
|
|
|
|
.sync_sg_for_cpu = dma_4u_sync_sg_for_cpu,
|
2017-05-22 09:11:30 +02:00
|
|
|
.dma_supported = dma_4u_supported,
|
2017-05-21 13:33:44 +02:00
|
|
|
.mapping_error = dma_4u_mapping_error,
|
2006-02-10 06:32:07 +01:00
|
|
|
};
|
|
|
|
|
2017-01-20 22:04:01 +01:00
|
|
|
const struct dma_map_ops *dma_ops = &sun4u_dma_ops;
|
2007-07-28 07:39:14 +02:00
|
|
|
EXPORT_SYMBOL(dma_ops);
|