2006-02-01 03:29:18 +01:00
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/* arch/sparc64/mm/tsb.c
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*
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* Copyright (C) 2006 David S. Miller <davem@davemloft.net>
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*/
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#include <linux/kernel.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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2006-02-01 03:31:06 +01:00
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#include <asm/mmu_context.h>
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2006-02-01 03:31:20 +01:00
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#include <asm/pgtable.h>
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2006-02-01 03:31:38 +01:00
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#include <asm/tsb.h>
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2006-02-01 03:29:18 +01:00
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extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
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2006-02-01 03:31:20 +01:00
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static inline unsigned long tsb_hash(unsigned long vaddr, unsigned long nentries)
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2006-02-01 03:29:18 +01:00
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{
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vaddr >>= PAGE_SHIFT;
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2006-02-01 03:31:20 +01:00
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return vaddr & (nentries - 1);
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2006-02-01 03:29:18 +01:00
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}
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2006-02-18 03:01:02 +01:00
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static inline int tag_compare(unsigned long tag, unsigned long vaddr)
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2006-02-01 03:29:18 +01:00
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{
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2006-02-18 03:01:02 +01:00
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return (tag == (vaddr >> 22));
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2006-02-01 03:29:18 +01:00
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}
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/* TSB flushes need only occur on the processor initiating the address
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* space modification, not on each cpu the address space has run on.
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* Only the TLB flush needs that treatment.
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*/
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void flush_tsb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long v;
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for (v = start; v < end; v += PAGE_SIZE) {
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2006-02-01 03:31:20 +01:00
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unsigned long hash = tsb_hash(v, KERNEL_TSB_NENTRIES);
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struct tsb *ent = &swapper_tsb[hash];
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2006-02-01 03:29:18 +01:00
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2006-02-18 03:01:02 +01:00
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if (tag_compare(ent->tag, v)) {
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ent->tag = (1UL << TSB_TAG_INVALID_BIT);
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2006-02-01 03:29:18 +01:00
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membar_storeload_storestore();
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}
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}
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}
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void flush_tsb_user(struct mmu_gather *mp)
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{
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struct mm_struct *mm = mp->mm;
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2006-02-01 03:31:20 +01:00
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struct tsb *tsb = mm->context.tsb;
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unsigned long nentries = mm->context.tsb_nentries;
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2006-02-18 03:01:02 +01:00
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unsigned long base;
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2006-02-01 03:29:18 +01:00
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int i;
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2006-02-16 06:01:31 +01:00
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if (tlb_type == cheetah_plus || tlb_type == hypervisor)
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2006-02-02 00:55:21 +01:00
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base = __pa(tsb);
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else
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base = (unsigned long) tsb;
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2006-02-01 03:29:18 +01:00
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for (i = 0; i < mp->tlb_nr; i++) {
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unsigned long v = mp->vaddrs[i];
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2006-02-02 00:55:21 +01:00
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unsigned long tag, ent, hash;
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2006-02-01 03:29:18 +01:00
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v &= ~0x1UL;
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2006-02-02 00:55:21 +01:00
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hash = tsb_hash(v, nentries);
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ent = base + (hash * sizeof(struct tsb));
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2006-02-18 03:01:02 +01:00
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tag = (v >> 22UL);
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2006-02-02 00:55:21 +01:00
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tsb_flush(ent, tag);
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2006-02-01 03:29:18 +01:00
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}
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}
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2006-02-01 03:31:06 +01:00
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2006-02-01 03:31:20 +01:00
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static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_bytes)
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{
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unsigned long tsb_reg, base, tsb_paddr;
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unsigned long page_sz, tte;
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mm->context.tsb_nentries = tsb_bytes / sizeof(struct tsb);
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base = TSBMAP_BASE;
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2006-02-12 06:57:54 +01:00
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tte = pgprot_val(PAGE_KERNEL_LOCKED);
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2006-02-01 03:31:20 +01:00
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tsb_paddr = __pa(mm->context.tsb);
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2006-02-02 00:55:21 +01:00
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BUG_ON(tsb_paddr & (tsb_bytes - 1UL));
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2006-02-01 03:31:20 +01:00
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/* Use the smallest page size that can map the whole TSB
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* in one TLB entry.
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*/
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switch (tsb_bytes) {
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case 8192 << 0:
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tsb_reg = 0x0UL;
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#ifdef DCACHE_ALIASING_POSSIBLE
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base += (tsb_paddr & 8192);
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#endif
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page_sz = 8192;
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break;
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case 8192 << 1:
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tsb_reg = 0x1UL;
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page_sz = 64 * 1024;
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break;
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case 8192 << 2:
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tsb_reg = 0x2UL;
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page_sz = 64 * 1024;
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break;
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case 8192 << 3:
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tsb_reg = 0x3UL;
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page_sz = 64 * 1024;
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break;
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case 8192 << 4:
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tsb_reg = 0x4UL;
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page_sz = 512 * 1024;
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break;
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case 8192 << 5:
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tsb_reg = 0x5UL;
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page_sz = 512 * 1024;
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break;
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case 8192 << 6:
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tsb_reg = 0x6UL;
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page_sz = 512 * 1024;
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break;
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case 8192 << 7:
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tsb_reg = 0x7UL;
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page_sz = 4 * 1024 * 1024;
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break;
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2006-02-01 03:31:38 +01:00
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default:
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BUG();
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2006-02-01 03:31:20 +01:00
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};
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2006-02-12 06:57:54 +01:00
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tte |= pte_sz_bits(page_sz);
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2006-02-01 03:31:20 +01:00
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2006-02-10 02:21:53 +01:00
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if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
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2006-02-02 00:55:21 +01:00
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/* Physical mapping, no locked TLB entry for TSB. */
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tsb_reg |= tsb_paddr;
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mm->context.tsb_reg_val = tsb_reg;
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mm->context.tsb_map_vaddr = 0;
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mm->context.tsb_map_pte = 0;
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} else {
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tsb_reg |= base;
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tsb_reg |= (tsb_paddr & (page_sz - 1UL));
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tte |= (tsb_paddr & ~(page_sz - 1UL));
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mm->context.tsb_reg_val = tsb_reg;
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mm->context.tsb_map_vaddr = base;
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mm->context.tsb_map_pte = tte;
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}
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2006-02-01 03:31:20 +01:00
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2006-02-10 02:21:53 +01:00
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/* Setup the Hypervisor TSB descriptor. */
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if (tlb_type == hypervisor) {
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struct hv_tsb_descr *hp = &mm->context.tsb_descr;
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switch (PAGE_SIZE) {
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case 8192:
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default:
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hp->pgsz_idx = HV_PGSZ_IDX_8K;
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break;
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case 64 * 1024:
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hp->pgsz_idx = HV_PGSZ_IDX_64K;
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break;
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case 512 * 1024:
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hp->pgsz_idx = HV_PGSZ_IDX_512K;
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break;
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case 4 * 1024 * 1024:
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hp->pgsz_idx = HV_PGSZ_IDX_4MB;
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break;
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};
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hp->assoc = 1;
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hp->num_ttes = tsb_bytes / 16;
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hp->ctx_idx = 0;
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switch (PAGE_SIZE) {
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case 8192:
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default:
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hp->pgsz_mask = HV_PGSZ_MASK_8K;
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break;
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case 64 * 1024:
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hp->pgsz_mask = HV_PGSZ_MASK_64K;
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break;
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case 512 * 1024:
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hp->pgsz_mask = HV_PGSZ_MASK_512K;
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break;
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case 4 * 1024 * 1024:
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hp->pgsz_mask = HV_PGSZ_MASK_4MB;
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break;
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};
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hp->tsb_base = tsb_paddr;
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hp->resv = 0;
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}
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2006-02-01 03:31:20 +01:00
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}
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2006-02-01 03:31:38 +01:00
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/* The page tables are locked against modifications while this
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* runs.
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*
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* XXX do some prefetching...
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*/
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static void copy_tsb(struct tsb *old_tsb, unsigned long old_size,
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struct tsb *new_tsb, unsigned long new_size)
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{
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unsigned long old_nentries = old_size / sizeof(struct tsb);
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unsigned long new_nentries = new_size / sizeof(struct tsb);
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unsigned long i;
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for (i = 0; i < old_nentries; i++) {
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register unsigned long tag asm("o4");
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register unsigned long pte asm("o5");
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2006-02-02 00:55:21 +01:00
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unsigned long v, hash;
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2006-02-11 19:19:37 +01:00
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if (tlb_type == hypervisor) {
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__asm__ __volatile__(
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"ldda [%2] %3, %0"
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: "=r" (tag), "=r" (pte)
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: "r" (__pa(&old_tsb[i])),
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"i" (ASI_QUAD_LDD_PHYS_4V));
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} else if (tlb_type == cheetah_plus) {
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2006-02-02 00:55:21 +01:00
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__asm__ __volatile__(
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"ldda [%2] %3, %0"
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: "=r" (tag), "=r" (pte)
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: "r" (__pa(&old_tsb[i])),
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"i" (ASI_QUAD_LDD_PHYS));
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} else {
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__asm__ __volatile__(
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"ldda [%2] %3, %0"
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: "=r" (tag), "=r" (pte)
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: "r" (&old_tsb[i]),
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"i" (ASI_NUCLEUS_QUAD_LDD));
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}
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2006-02-01 03:31:38 +01:00
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2006-02-18 03:01:02 +01:00
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if (tag & ((1UL << TSB_TAG_LOCK_BIT) |
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(1UL << TSB_TAG_INVALID_BIT)))
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2006-02-01 03:31:38 +01:00
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continue;
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/* We only put base page size PTEs into the TSB,
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* but that might change in the future. This code
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* would need to be changed if we start putting larger
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* page size PTEs into there.
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*/
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WARN_ON((pte & _PAGE_ALL_SZ_BITS) != _PAGE_SZBITS);
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/* The tag holds bits 22 to 63 of the virtual address
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* and the context. Clear out the context, and shift
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* up to make a virtual address.
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*/
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v = (tag & ((1UL << 42UL) - 1UL)) << 22UL;
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/* The implied bits of the tag (bits 13 to 21) are
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* determined by the TSB entry index, so fill that in.
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*/
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v |= (i & (512UL - 1UL)) << 13UL;
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hash = tsb_hash(v, new_nentries);
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2006-02-11 19:19:37 +01:00
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if (tlb_type == cheetah_plus ||
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tlb_type == hypervisor) {
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2006-02-02 00:55:21 +01:00
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__asm__ __volatile__(
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"stxa %0, [%1] %2\n\t"
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"stxa %3, [%4] %2"
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: /* no outputs */
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: "r" (tag),
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"r" (__pa(&new_tsb[hash].tag)),
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"i" (ASI_PHYS_USE_EC),
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"r" (pte),
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"r" (__pa(&new_tsb[hash].pte)));
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} else {
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new_tsb[hash].tag = tag;
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new_tsb[hash].pte = pte;
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}
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2006-02-01 03:31:38 +01:00
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}
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}
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/* When the RSS of an address space exceeds mm->context.tsb_rss_limit,
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* update_mmu_cache() invokes this routine to try and grow the TSB.
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* When we reach the maximum TSB size supported, we stick ~0UL into
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* mm->context.tsb_rss_limit so the grow checks in update_mmu_cache()
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* will not trigger any longer.
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*
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* The TSB can be anywhere from 8K to 1MB in size, in increasing powers
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* of two. The TSB must be aligned to it's size, so f.e. a 512K TSB
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* must be 512K aligned.
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*
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* The idea here is to grow the TSB when the RSS of the process approaches
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* the number of entries that the current TSB can hold at once. Currently,
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* we trigger when the RSS hits 3/4 of the TSB capacity.
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*/
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void tsb_grow(struct mm_struct *mm, unsigned long rss, gfp_t gfp_flags)
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{
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unsigned long max_tsb_size = 1 * 1024 * 1024;
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unsigned long size, old_size;
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struct page *page;
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struct tsb *old_tsb;
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if (max_tsb_size > (PAGE_SIZE << MAX_ORDER))
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max_tsb_size = (PAGE_SIZE << MAX_ORDER);
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for (size = PAGE_SIZE; size < max_tsb_size; size <<= 1UL) {
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unsigned long n_entries = size / sizeof(struct tsb);
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n_entries = (n_entries * 3) / 4;
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if (n_entries > rss)
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break;
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}
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|
2006-02-18 03:01:02 +01:00
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page = alloc_pages(gfp_flags, get_order(size));
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2006-02-01 03:31:38 +01:00
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if (unlikely(!page))
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return;
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2006-02-18 03:01:02 +01:00
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/* Mark all tags as invalid. */
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memset(page_address(page), 0x40, size);
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2006-02-01 03:31:38 +01:00
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if (size == max_tsb_size)
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mm->context.tsb_rss_limit = ~0UL;
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else
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mm->context.tsb_rss_limit =
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((size / sizeof(struct tsb)) * 3) / 4;
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old_tsb = mm->context.tsb;
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old_size = mm->context.tsb_nentries * sizeof(struct tsb);
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if (old_tsb)
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copy_tsb(old_tsb, old_size, page_address(page), size);
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|
|
|
|
mm->context.tsb = page_address(page);
|
|
|
|
setup_tsb_params(mm, size);
|
|
|
|
|
|
|
|
/* If old_tsb is NULL, we're being invoked for the first time
|
|
|
|
* from init_new_context().
|
|
|
|
*/
|
|
|
|
if (old_tsb) {
|
|
|
|
/* Now force all other processors to reload the new
|
|
|
|
* TSB state.
|
|
|
|
*/
|
|
|
|
smp_tsb_sync(mm);
|
|
|
|
|
|
|
|
/* Finally reload it on the local cpu. No further
|
|
|
|
* references will remain to the old TSB and we can
|
|
|
|
* thus free it up.
|
|
|
|
*/
|
|
|
|
tsb_context_switch(mm);
|
|
|
|
|
|
|
|
free_pages((unsigned long) old_tsb, get_order(old_size));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-02-01 03:31:06 +01:00
|
|
|
int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
|
|
|
|
{
|
2006-03-07 04:59:50 +01:00
|
|
|
spin_lock_init(&mm->context.lock);
|
2006-02-01 03:31:06 +01:00
|
|
|
|
|
|
|
mm->context.sparc64_ctx_val = 0UL;
|
|
|
|
|
2006-02-01 03:31:38 +01:00
|
|
|
/* copy_mm() copies over the parent's mm_struct before calling
|
|
|
|
* us, so we need to zero out the TSB pointer or else tsb_grow()
|
|
|
|
* will be confused and think there is an older TSB to free up.
|
|
|
|
*/
|
|
|
|
mm->context.tsb = NULL;
|
2006-02-03 01:16:24 +01:00
|
|
|
tsb_grow(mm, 0, GFP_KERNEL);
|
2006-02-01 03:31:38 +01:00
|
|
|
|
|
|
|
if (unlikely(!mm->context.tsb))
|
|
|
|
return -ENOMEM;
|
2006-02-01 03:31:06 +01:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void destroy_context(struct mm_struct *mm)
|
|
|
|
{
|
2006-02-01 03:31:38 +01:00
|
|
|
unsigned long size = mm->context.tsb_nentries * sizeof(struct tsb);
|
2006-02-24 06:40:15 +01:00
|
|
|
unsigned long flags;
|
2006-02-01 03:31:38 +01:00
|
|
|
|
|
|
|
free_pages((unsigned long) mm->context.tsb, get_order(size));
|
2006-02-01 03:31:20 +01:00
|
|
|
|
|
|
|
/* We can remove these later, but for now it's useful
|
|
|
|
* to catch any bogus post-destroy_context() references
|
|
|
|
* to the TSB.
|
|
|
|
*/
|
|
|
|
mm->context.tsb = NULL;
|
|
|
|
mm->context.tsb_reg_val = 0UL;
|
2006-02-01 03:31:06 +01:00
|
|
|
|
2006-02-24 06:40:15 +01:00
|
|
|
spin_lock_irqsave(&ctx_alloc_lock, flags);
|
2006-02-01 03:31:06 +01:00
|
|
|
|
|
|
|
if (CTX_VALID(mm->context)) {
|
|
|
|
unsigned long nr = CTX_NRBITS(mm->context);
|
|
|
|
mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63));
|
|
|
|
}
|
|
|
|
|
2006-02-24 06:40:15 +01:00
|
|
|
spin_unlock_irqrestore(&ctx_alloc_lock, flags);
|
2006-02-01 03:31:06 +01:00
|
|
|
}
|