2006-12-07 17:59:14 +01:00
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/*
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* pata_it8213.c - iTE Tech. Inc. IT8213 PATA driver
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*
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* The IT8213 is a very Intel ICH like device for timing purposes, having
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* a similar register layout and the same split clock arrangement. Cable
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* detection is different, and it does not have slave channels or all the
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* clutter of later ICH/SATA setups.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/ata.h>
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#define DRV_NAME "pata_it8213"
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2007-05-22 02:26:38 +02:00
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#define DRV_VERSION "0.0.3"
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2006-12-07 17:59:14 +01:00
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/**
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2009-12-03 20:32:11 +01:00
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* it8213_pre_reset - probe begin
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2007-08-06 11:36:23 +02:00
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* @link: link
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 08:50:52 +01:00
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* @deadline: deadline jiffies for the operation
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2006-12-07 17:59:14 +01:00
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*
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2007-03-07 17:46:20 +01:00
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* Filter out ports by the enable bits before doing the normal reset
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* and probe.
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2006-12-07 17:59:14 +01:00
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*/
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2007-08-06 11:36:23 +02:00
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static int it8213_pre_reset(struct ata_link *link, unsigned long deadline)
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2006-12-07 17:59:14 +01:00
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{
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static const struct pci_bits it8213_enable_bits[] = {
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{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
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};
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2007-08-06 11:36:23 +02:00
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struct ata_port *ap = link->ap;
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2006-12-07 17:59:14 +01:00
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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if (!pci_test_config_bits(pdev, &it8213_enable_bits[ap->port_no]))
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return -ENOENT;
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 08:50:52 +01:00
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2008-04-07 15:47:16 +02:00
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return ata_sff_prereset(link, deadline);
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2006-12-07 17:59:14 +01:00
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}
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2007-03-07 17:46:20 +01:00
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/**
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* it8213_cable_detect - check for 40/80 pin
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* @ap: Port
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*
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* Perform cable detection for the 8213 ATA interface. This is
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* different to the PIIX arrangement
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*/
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static int it8213_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 tmp;
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pci_read_config_byte(pdev, 0x42, &tmp);
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if (tmp & 2) /* The initial docs are incorrect */
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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2006-12-07 17:59:14 +01:00
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/**
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* it8213_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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2007-03-07 17:46:20 +01:00
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* @adev: Device whose timings we are configuring
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2006-12-07 17:59:14 +01:00
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*
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* Set PIO mode for device, in host controller PCI config space.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio = adev->pio_mode - XFER_PIO_0;
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struct pci_dev *dev = to_pci_dev(ap->host->dev);
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unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
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u16 idetm_data;
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int control = 0;
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/*
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* See Intel Document 298600-004 for the timing programing rules
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* for PIIX/ICH. The 8213 is a clone so very similar
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*/
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static const /* ISP RTC */
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u8 timings[][2] = { { 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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2009-12-03 20:32:10 +01:00
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if (pio > 1)
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control |= 1; /* TIME */
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2006-12-07 17:59:14 +01:00
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if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
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2009-12-03 20:32:10 +01:00
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control |= 2; /* IE */
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2006-12-07 17:59:14 +01:00
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/* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
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if (adev->class != ATA_DEV_ATA)
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2009-12-03 20:32:10 +01:00
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control |= 4; /* PPE */
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2006-12-07 17:59:14 +01:00
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pci_read_config_word(dev, idetm_port, &idetm_data);
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2009-12-03 20:32:10 +01:00
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/* Set PPE, IE, and TIME as appropriate */
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2006-12-07 17:59:14 +01:00
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if (adev->devno == 0) {
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idetm_data &= 0xCCF0;
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idetm_data |= control;
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idetm_data |= (timings[pio][0] << 12) |
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(timings[pio][1] << 8);
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} else {
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u8 slave_data;
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2009-12-03 20:32:10 +01:00
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idetm_data &= 0xFF0F;
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2006-12-07 17:59:14 +01:00
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idetm_data |= (control << 4);
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2008-02-03 16:08:11 +01:00
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/* Slave timing in separate register */
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2006-12-07 17:59:14 +01:00
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pci_read_config_byte(dev, 0x44, &slave_data);
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slave_data &= 0xF0;
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2009-12-03 20:32:10 +01:00
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slave_data |= (timings[pio][0] << 2) | timings[pio][1];
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2006-12-07 17:59:14 +01:00
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pci_write_config_byte(dev, 0x44, slave_data);
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}
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2009-12-03 20:32:10 +01:00
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idetm_data |= 0x4000; /* Ensure SITRE is set */
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2006-12-07 17:59:14 +01:00
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pci_write_config_word(dev, idetm_port, idetm_data);
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}
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/**
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* it8213_set_dmamode - Initialize host controller PATA DMA timings
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* @ap: Port whose timings we are configuring
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* @adev: Device to program
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*
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* Set UDMA/MWDMA mode for device, in host controller PCI config space.
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* This device is basically an ICH alike.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void it8213_set_dmamode (struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *dev = to_pci_dev(ap->host->dev);
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u16 master_data;
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u8 speed = adev->dma_mode;
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int devid = adev->devno;
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u8 udma_enable;
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static const /* ISP RTC */
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u8 timings[][2] = { { 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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pci_read_config_word(dev, 0x40, &master_data);
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pci_read_config_byte(dev, 0x48, &udma_enable);
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if (speed >= XFER_UDMA_0) {
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unsigned int udma = adev->dma_mode - XFER_UDMA_0;
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u16 udma_timing;
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u16 ideconf;
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int u_clock, u_speed;
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/* Clocks follow the PIIX style */
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u_speed = min(2 - (udma & 1), udma);
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if (udma == 5)
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u_clock = 0x1000; /* 100Mhz */
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else if (udma > 2)
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u_clock = 1; /* 66Mhz */
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else
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u_clock = 0; /* 33Mhz */
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udma_enable |= (1 << devid);
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2009-12-03 20:32:10 +01:00
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/* Load the UDMA cycle time */
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2006-12-07 17:59:14 +01:00
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pci_read_config_word(dev, 0x4A, &udma_timing);
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udma_timing &= ~(3 << (4 * devid));
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2009-12-03 20:32:10 +01:00
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udma_timing |= u_speed << (4 * devid);
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2006-12-07 17:59:14 +01:00
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pci_write_config_word(dev, 0x4A, udma_timing);
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/* Load the clock selection */
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pci_read_config_word(dev, 0x54, &ideconf);
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ideconf &= ~(0x1001 << devid);
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ideconf |= u_clock << devid;
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pci_write_config_word(dev, 0x54, ideconf);
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} else {
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/*
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* MWDMA is driven by the PIO timings. We must also enable
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* IORDY unconditionally along with TIME1. PPE has already
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* been set when the PIO timing was set.
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*/
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unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
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unsigned int control;
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u8 slave_data;
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static const unsigned int needed_pio[3] = {
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XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
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};
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int pio = needed_pio[mwdma] - XFER_PIO_0;
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control = 3; /* IORDY|TIME1 */
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/* If the drive MWDMA is faster than it can do PIO then
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we must force PIO into PIO0 */
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if (adev->pio_mode < needed_pio[mwdma])
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/* Enable DMA timing only */
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control |= 8; /* PIO cycles in PIO0 */
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if (devid) { /* Slave */
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master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
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master_data |= control << 4;
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pci_read_config_byte(dev, 0x44, &slave_data);
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2009-12-03 20:32:10 +01:00
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slave_data &= 0xF0;
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2006-12-07 17:59:14 +01:00
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/* Load the matching timing */
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
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pci_write_config_byte(dev, 0x44, slave_data);
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} else { /* Master */
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master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
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and master timing bits */
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master_data |= control;
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master_data |=
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(timings[pio][0] << 12) |
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(timings[pio][1] << 8);
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}
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udma_enable &= ~(1 << devid);
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pci_write_config_word(dev, 0x40, master_data);
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}
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pci_write_config_byte(dev, 0x48, udma_enable);
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}
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static struct scsi_host_template it8213_sht = {
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2008-03-25 04:22:49 +01:00
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ATA_BMDMA_SHT(DRV_NAME),
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2006-12-07 17:59:14 +01:00
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};
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libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 04:22:49 +01:00
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static struct ata_port_operations it8213_ops = {
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.inherits = &ata_bmdma_port_ops,
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.cable_detect = it8213_cable_detect,
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2006-12-07 17:59:14 +01:00
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.set_piomode = it8213_set_piomode,
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.set_dmamode = it8213_set_dmamode,
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libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 04:22:50 +01:00
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|
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.prereset = it8213_pre_reset,
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2006-12-07 17:59:14 +01:00
|
|
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};
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|
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|
|
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|
|
|
|
|
/**
|
|
|
|
* it8213_init_one - Register 8213 ATA PCI device with kernel services
|
|
|
|
* @pdev: PCI device to register
|
|
|
|
* @ent: Entry in it8213_pci_tbl matching with @pdev
|
|
|
|
*
|
|
|
|
* Called from kernel PCI layer.
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|
|
*
|
|
|
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* LOCKING:
|
|
|
|
* Inherited from PCI layer (may sleep).
|
|
|
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*
|
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* RETURNS:
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|
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* Zero on success, or -ERRNO value.
|
|
|
|
*/
|
|
|
|
|
|
|
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static int it8213_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
{
|
|
|
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static int printed_version;
|
2007-05-04 12:43:58 +02:00
|
|
|
static const struct ata_port_info info = {
|
2007-05-28 12:59:48 +02:00
|
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.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 21:38:24 +01:00
|
|
|
.pio_mask = ATA_PIO4,
|
2009-12-03 23:53:27 +01:00
|
|
|
.mwdma_mask = ATA_MWDMA12_ONLY,
|
2007-07-09 18:16:50 +02:00
|
|
|
.udma_mask = ATA_UDMA4, /* FIXME: want UDMA 100? */
|
2006-12-07 17:59:14 +01:00
|
|
|
.port_ops = &it8213_ops,
|
|
|
|
};
|
2007-05-04 12:43:58 +02:00
|
|
|
/* Current IT8213 stuff is single port */
|
|
|
|
const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
|
2006-12-07 17:59:14 +01:00
|
|
|
|
|
|
|
if (!printed_version++)
|
|
|
|
dev_printk(KERN_DEBUG, &pdev->dev,
|
|
|
|
"version " DRV_VERSION "\n");
|
|
|
|
|
2008-04-07 15:47:16 +02:00
|
|
|
return ata_pci_sff_init_one(pdev, ppi, &it8213_sht, NULL);
|
2006-12-07 17:59:14 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pci_device_id it8213_pci_tbl[] = {
|
|
|
|
{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8213), },
|
|
|
|
|
|
|
|
{ } /* terminate list */
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_driver it8213_pci_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = it8213_pci_tbl,
|
|
|
|
.probe = it8213_init_one,
|
|
|
|
.remove = ata_pci_remove_one,
|
2007-03-02 09:31:26 +01:00
|
|
|
#ifdef CONFIG_PM
|
2006-12-07 17:59:14 +01:00
|
|
|
.suspend = ata_pci_device_suspend,
|
|
|
|
.resume = ata_pci_device_resume,
|
2007-03-02 09:31:26 +01:00
|
|
|
#endif
|
2006-12-07 17:59:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __init it8213_init(void)
|
|
|
|
{
|
|
|
|
return pci_register_driver(&it8213_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit it8213_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&it8213_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(it8213_init);
|
|
|
|
module_exit(it8213_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
|
|
MODULE_DESCRIPTION("SCSI low-level driver for the ITE 8213");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|