2005-04-17 00:20:36 +02:00
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/*
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* drivers/mtd/nand/au1550nd.c
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*
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* Copyright (C) 2004 Embedded Edge, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
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#include <linux/interrupt.h>
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2005-04-17 00:20:36 +02:00
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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2005-09-23 03:44:58 +02:00
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#include <asm/mach-au1x00/au1xxx.h>
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2009-10-04 14:55:24 +02:00
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#include <asm/mach-db1x00/bcsr.h>
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2005-04-17 00:20:36 +02:00
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/*
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* MTD structure for NAND controller
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*/
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static struct mtd_info *au1550_mtd = NULL;
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static void __iomem *p_nand;
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2006-05-13 19:07:53 +02:00
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static int nand_width = 1; /* default x8 */
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2006-05-23 23:28:48 +02:00
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static void (*au1550_write_byte)(struct mtd_info *, u_char);
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2005-04-17 00:20:36 +02:00
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/*
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* Define partitions for flash device
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*/
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2006-01-10 05:54:01 +01:00
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static const struct mtd_partition partition_info[] = {
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2005-11-07 12:15:49 +01:00
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{
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2006-05-13 19:07:53 +02:00
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.name = "NAND FS 0",
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.offset = 0,
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.size = 8 * 1024 * 1024},
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2005-11-07 12:15:49 +01:00
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{
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2006-05-13 19:07:53 +02:00
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.name = "NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL}
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2005-04-17 00:20:36 +02:00
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};
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/**
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* au_read_byte - read one byte from the chip
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* @mtd: MTD device structure
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*
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* read function for 8bit buswith
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*/
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static u_char au_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u_char ret = readb(this->IO_ADDR_R);
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au_sync();
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return ret;
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}
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/**
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* au_write_byte - write one byte to the chip
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* @mtd: MTD device structure
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* @byte: pointer to data byte to write
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*
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* write function for 8it buswith
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*/
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static void au_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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writeb(byte, this->IO_ADDR_W);
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au_sync();
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}
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/**
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* au_read_byte16 - read one byte endianess aware from the chip
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* @mtd: MTD device structure
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*
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2005-11-07 12:15:49 +01:00
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* read function for 16bit buswith with
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2005-04-17 00:20:36 +02:00
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* endianess conversion
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*/
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static u_char au_read_byte16(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
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au_sync();
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return ret;
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}
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/**
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* au_write_byte16 - write one byte endianess aware to the chip
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* @mtd: MTD device structure
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* @byte: pointer to data byte to write
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*
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* write function for 16bit buswith with
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* endianess conversion
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*/
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static void au_write_byte16(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
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au_sync();
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}
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/**
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* au_read_word - read one word from the chip
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* @mtd: MTD device structure
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*
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2005-11-07 12:15:49 +01:00
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* read function for 16bit buswith without
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2005-04-17 00:20:36 +02:00
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* endianess conversion
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*/
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static u16 au_read_word(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u16 ret = readw(this->IO_ADDR_R);
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au_sync();
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return ret;
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}
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/**
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* au_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* write function for 8bit buswith
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*/
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static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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2006-05-13 19:07:53 +02:00
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for (i = 0; i < len; i++) {
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2005-04-17 00:20:36 +02:00
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writeb(buf[i], this->IO_ADDR_W);
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au_sync();
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}
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}
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/**
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2005-11-07 12:15:49 +01:00
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* au_read_buf - read chip data into buffer
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2005-04-17 00:20:36 +02:00
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* read function for 8bit buswith
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*/
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static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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2006-05-13 19:07:53 +02:00
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for (i = 0; i < len; i++) {
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2005-04-17 00:20:36 +02:00
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buf[i] = readb(this->IO_ADDR_R);
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2005-11-07 12:15:49 +01:00
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au_sync();
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2005-04-17 00:20:36 +02:00
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}
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}
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/**
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2005-11-07 12:15:49 +01:00
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* au_verify_buf - Verify chip data against buffer
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2005-04-17 00:20:36 +02:00
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* @mtd: MTD device structure
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* @buf: buffer containing the data to compare
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* @len: number of bytes to compare
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*
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* verify function for 8bit buswith
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*/
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static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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2006-05-13 19:07:53 +02:00
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for (i = 0; i < len; i++) {
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2005-04-17 00:20:36 +02:00
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if (buf[i] != readb(this->IO_ADDR_R))
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return -EFAULT;
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au_sync();
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}
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return 0;
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}
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/**
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* au_write_buf16 - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* write function for 16bit buswith
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*/
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static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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2005-11-07 12:15:49 +01:00
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2006-05-13 19:07:53 +02:00
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for (i = 0; i < len; i++) {
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2005-04-17 00:20:36 +02:00
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writew(p[i], this->IO_ADDR_W);
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au_sync();
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}
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2005-11-07 12:15:49 +01:00
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2005-04-17 00:20:36 +02:00
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}
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/**
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2005-11-07 12:15:49 +01:00
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* au_read_buf16 - read chip data into buffer
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2005-04-17 00:20:36 +02:00
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* read function for 16bit buswith
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*/
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static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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2006-05-13 19:07:53 +02:00
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for (i = 0; i < len; i++) {
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2005-04-17 00:20:36 +02:00
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p[i] = readw(this->IO_ADDR_R);
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au_sync();
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}
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}
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/**
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2005-11-07 12:15:49 +01:00
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* au_verify_buf16 - Verify chip data against buffer
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2005-04-17 00:20:36 +02:00
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* @mtd: MTD device structure
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* @buf: buffer containing the data to compare
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* @len: number of bytes to compare
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*
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* verify function for 16bit buswith
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*/
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static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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2006-05-13 19:07:53 +02:00
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for (i = 0; i < len; i++) {
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2005-04-17 00:20:36 +02:00
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if (p[i] != readw(this->IO_ADDR_R))
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return -EFAULT;
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au_sync();
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}
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return 0;
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}
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2006-05-23 23:25:53 +02:00
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/* Select the chip by setting nCE to low */
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#define NAND_CTL_SETNCE 1
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/* Deselect the chip by setting nCE to high */
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#define NAND_CTL_CLRNCE 2
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/* Select the command latch by setting CLE to high */
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#define NAND_CTL_SETCLE 3
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/* Deselect the command latch by setting CLE to low */
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#define NAND_CTL_CLRCLE 4
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/* Select the address latch by setting ALE to high */
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#define NAND_CTL_SETALE 5
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/* Deselect the address latch by setting ALE to low */
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#define NAND_CTL_CLRALE 6
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2005-04-17 00:20:36 +02:00
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static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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register struct nand_chip *this = mtd->priv;
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2006-05-13 19:07:53 +02:00
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switch (cmd) {
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case NAND_CTL_SETCLE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
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break;
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case NAND_CTL_CLRCLE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
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break;
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2005-04-17 00:20:36 +02:00
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2006-05-13 19:07:53 +02:00
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case NAND_CTL_SETALE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
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break;
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2005-04-17 00:20:36 +02:00
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2005-11-07 12:15:49 +01:00
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case NAND_CTL_CLRALE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
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2006-05-13 19:07:53 +02:00
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/* FIXME: Nobody knows why this is necessary,
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2005-04-17 00:20:36 +02:00
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* but it works only that way */
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2005-11-07 12:15:49 +01:00
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udelay(1);
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2005-04-17 00:20:36 +02:00
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break;
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2005-11-07 12:15:49 +01:00
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case NAND_CTL_SETNCE:
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2005-04-17 00:20:36 +02:00
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/* assert (force assert) chip enable */
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2006-05-13 19:07:53 +02:00
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au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
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2005-04-17 00:20:36 +02:00
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break;
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2005-11-07 12:15:49 +01:00
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case NAND_CTL_CLRNCE:
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2006-05-13 19:07:53 +02:00
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/* deassert chip enable */
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au_writel(0, MEM_STNDCTL);
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2005-04-17 00:20:36 +02:00
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break;
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}
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this->IO_ADDR_R = this->IO_ADDR_W;
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2005-11-07 12:15:49 +01:00
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2005-04-17 00:20:36 +02:00
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/* Drain the writebuffer */
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au_sync();
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}
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int au1550_device_ready(struct mtd_info *mtd)
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{
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int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
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au_sync();
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return ret;
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}
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|
|
|
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
/**
|
|
|
|
* au1550_select_chip - control -CE line
|
|
|
|
* Forbid driving -CE manually permitting the NAND controller to do this.
|
|
|
|
* Keeping -CE asserted during the whole sector reads interferes with the
|
|
|
|
* NOR flash and PCMCIA drivers as it causes contention on the static bus.
|
|
|
|
* We only have to hold -CE low for the NAND read commands since the flash
|
|
|
|
* chip needs it to be asserted during chip not ready time but the NAND
|
|
|
|
* controller keeps it released.
|
|
|
|
*
|
|
|
|
* @mtd: MTD device structure
|
|
|
|
* @chip: chipnumber to select, -1 for deselect
|
|
|
|
*/
|
|
|
|
static void au1550_select_chip(struct mtd_info *mtd, int chip)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* au1550_command - Send command to NAND device
|
|
|
|
* @mtd: MTD device structure
|
|
|
|
* @command: the command to be sent
|
|
|
|
* @column: the column address for this command, -1 if none
|
|
|
|
* @page_addr: the page address for this command, -1 if none
|
|
|
|
*/
|
|
|
|
static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
|
|
|
|
{
|
|
|
|
register struct nand_chip *this = mtd->priv;
|
|
|
|
int ce_override = 0, i;
|
|
|
|
ulong flags;
|
|
|
|
|
|
|
|
/* Begin command latch cycle */
|
2006-05-23 23:25:53 +02:00
|
|
|
au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
/*
|
|
|
|
* Write out the command to the device.
|
|
|
|
*/
|
|
|
|
if (command == NAND_CMD_SEQIN) {
|
|
|
|
int readcmd;
|
|
|
|
|
2006-05-22 23:18:05 +02:00
|
|
|
if (column >= mtd->writesize) {
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
/* OOB area */
|
2006-05-22 23:18:05 +02:00
|
|
|
column -= mtd->writesize;
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
readcmd = NAND_CMD_READOOB;
|
|
|
|
} else if (column < 256) {
|
|
|
|
/* First 256 bytes --> READ0 */
|
|
|
|
readcmd = NAND_CMD_READ0;
|
|
|
|
} else {
|
|
|
|
column -= 256;
|
|
|
|
readcmd = NAND_CMD_READ1;
|
|
|
|
}
|
2006-05-23 23:28:48 +02:00
|
|
|
au1550_write_byte(mtd, readcmd);
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
}
|
2006-05-23 23:28:48 +02:00
|
|
|
au1550_write_byte(mtd, command);
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
|
|
|
|
/* Set ALE and clear CLE to start address cycle */
|
2006-05-23 23:25:53 +02:00
|
|
|
au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
|
|
|
|
if (column != -1 || page_addr != -1) {
|
2006-05-23 23:25:53 +02:00
|
|
|
au1550_hwcontrol(mtd, NAND_CTL_SETALE);
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
|
|
|
|
/* Serially input address */
|
|
|
|
if (column != -1) {
|
|
|
|
/* Adjust columns for 16 bit buswidth */
|
|
|
|
if (this->options & NAND_BUSWIDTH_16)
|
|
|
|
column >>= 1;
|
2006-05-23 23:28:48 +02:00
|
|
|
au1550_write_byte(mtd, column);
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
}
|
|
|
|
if (page_addr != -1) {
|
2006-05-23 23:28:48 +02:00
|
|
|
au1550_write_byte(mtd, (u8)(page_addr & 0xff));
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
|
|
|
|
if (command == NAND_CMD_READ0 ||
|
|
|
|
command == NAND_CMD_READ1 ||
|
|
|
|
command == NAND_CMD_READOOB) {
|
|
|
|
/*
|
|
|
|
* NAND controller will release -CE after
|
|
|
|
* the last address byte is written, so we'll
|
|
|
|
* have to forcibly assert it. No interrupts
|
|
|
|
* are allowed while we do this as we don't
|
|
|
|
* want the NOR flash or PCMCIA drivers to
|
|
|
|
* steal our precious bytes of data...
|
|
|
|
*/
|
|
|
|
ce_override = 1;
|
|
|
|
local_irq_save(flags);
|
2006-05-23 23:25:53 +02:00
|
|
|
au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
}
|
|
|
|
|
2006-05-23 23:28:48 +02:00
|
|
|
au1550_write_byte(mtd, (u8)(page_addr >> 8));
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
|
|
|
|
/* One more address cycle for devices > 32MiB */
|
|
|
|
if (this->chipsize > (32 << 20))
|
2006-05-23 23:28:48 +02:00
|
|
|
au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
}
|
|
|
|
/* Latch in address */
|
2006-05-23 23:25:53 +02:00
|
|
|
au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Program and erase have their own busy handlers.
|
|
|
|
* Status and sequential in need no delay.
|
|
|
|
*/
|
|
|
|
switch (command) {
|
|
|
|
|
|
|
|
case NAND_CMD_PAGEPROG:
|
|
|
|
case NAND_CMD_ERASE1:
|
|
|
|
case NAND_CMD_ERASE2:
|
|
|
|
case NAND_CMD_SEQIN:
|
|
|
|
case NAND_CMD_STATUS:
|
|
|
|
return;
|
|
|
|
|
|
|
|
case NAND_CMD_RESET:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case NAND_CMD_READ0:
|
|
|
|
case NAND_CMD_READ1:
|
|
|
|
case NAND_CMD_READOOB:
|
|
|
|
/* Check if we're really driving -CE low (just in case) */
|
|
|
|
if (unlikely(!ce_override))
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Apply a short delay always to ensure that we do wait tWB. */
|
|
|
|
ndelay(100);
|
|
|
|
/* Wait for a chip to become ready... */
|
|
|
|
for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
|
|
|
|
udelay(1);
|
|
|
|
|
|
|
|
/* Release -CE and re-enable interrupts. */
|
2006-05-23 23:25:53 +02:00
|
|
|
au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
local_irq_restore(flags);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/* Apply this short delay always to ensure that we do wait tWB. */
|
|
|
|
ndelay(100);
|
|
|
|
|
|
|
|
while(!this->dev_ready(mtd));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/*
|
|
|
|
* Main initialization routine
|
|
|
|
*/
|
2006-05-16 14:54:50 +02:00
|
|
|
static int __init au1xxx_nand_init(void)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
struct nand_chip *this;
|
2006-05-13 19:07:53 +02:00
|
|
|
u16 boot_swapboot = 0; /* default value */
|
2005-04-17 00:20:36 +02:00
|
|
|
int retval;
|
2005-09-23 03:44:58 +02:00
|
|
|
u32 mem_staddr;
|
|
|
|
u32 nand_phys;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* Allocate memory for MTD device structure and private data */
|
2009-12-14 22:04:07 +01:00
|
|
|
au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (!au1550_mtd) {
|
2006-05-13 19:07:53 +02:00
|
|
|
printk("Unable to allocate NAND MTD dev structure.\n");
|
2005-04-17 00:20:36 +02:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get pointer to private data */
|
2006-05-13 19:07:53 +02:00
|
|
|
this = (struct nand_chip *)(&au1550_mtd[1]);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* Link the private data with the MTD structure */
|
|
|
|
au1550_mtd->priv = this;
|
2006-05-14 02:20:46 +02:00
|
|
|
au1550_mtd->owner = THIS_MODULE;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-11-07 12:15:49 +01:00
|
|
|
|
2006-05-16 18:16:41 +02:00
|
|
|
/* MEM_STNDCTL: disable ints, disable nand boot */
|
|
|
|
au_writel(0, MEM_STNDCTL);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_MIPS_PB1550
|
|
|
|
/* set gpio206 high */
|
2006-05-13 19:07:53 +02:00
|
|
|
au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-10-04 14:55:24 +02:00
|
|
|
boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
switch (boot_swapboot) {
|
2006-05-13 19:07:53 +02:00
|
|
|
case 0:
|
|
|
|
case 2:
|
|
|
|
case 8:
|
|
|
|
case 0xC:
|
|
|
|
case 0xD:
|
|
|
|
/* x16 NAND Flash */
|
|
|
|
nand_width = 0;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
case 9:
|
|
|
|
case 3:
|
|
|
|
case 0xE:
|
|
|
|
case 0xF:
|
|
|
|
/* x8 NAND Flash */
|
|
|
|
nand_width = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printk("Pb1550 NAND: bad boot:swap\n");
|
|
|
|
retval = -EINVAL;
|
|
|
|
goto outmem;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-09-23 03:44:58 +02:00
|
|
|
/* Configure chip-select; normally done by boot code, e.g. YAMON */
|
|
|
|
#ifdef NAND_STCFG
|
|
|
|
if (NAND_CS == 0) {
|
|
|
|
au_writel(NAND_STCFG, MEM_STCFG0);
|
|
|
|
au_writel(NAND_STTIME, MEM_STTIME0);
|
|
|
|
au_writel(NAND_STADDR, MEM_STADDR0);
|
|
|
|
}
|
|
|
|
if (NAND_CS == 1) {
|
|
|
|
au_writel(NAND_STCFG, MEM_STCFG1);
|
|
|
|
au_writel(NAND_STTIME, MEM_STTIME1);
|
|
|
|
au_writel(NAND_STADDR, MEM_STADDR1);
|
|
|
|
}
|
|
|
|
if (NAND_CS == 2) {
|
|
|
|
au_writel(NAND_STCFG, MEM_STCFG2);
|
|
|
|
au_writel(NAND_STTIME, MEM_STTIME2);
|
|
|
|
au_writel(NAND_STADDR, MEM_STADDR2);
|
|
|
|
}
|
|
|
|
if (NAND_CS == 3) {
|
|
|
|
au_writel(NAND_STCFG, MEM_STCFG3);
|
|
|
|
au_writel(NAND_STTIME, MEM_STTIME3);
|
|
|
|
au_writel(NAND_STADDR, MEM_STADDR3);
|
|
|
|
}
|
|
|
|
#endif
|
2005-11-07 12:15:49 +01:00
|
|
|
|
2005-09-23 03:44:58 +02:00
|
|
|
/* Locate NAND chip-select in order to determine NAND phys address */
|
|
|
|
mem_staddr = 0x00000000;
|
|
|
|
if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
|
|
|
|
mem_staddr = au_readl(MEM_STADDR0);
|
|
|
|
else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
|
|
|
|
mem_staddr = au_readl(MEM_STADDR1);
|
|
|
|
else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
|
|
|
|
mem_staddr = au_readl(MEM_STADDR2);
|
|
|
|
else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
|
|
|
|
mem_staddr = au_readl(MEM_STADDR3);
|
|
|
|
|
|
|
|
if (mem_staddr == 0x00000000) {
|
|
|
|
printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
|
|
|
|
kfree(au1550_mtd);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
nand_phys = (mem_staddr << 4) & 0xFFFC0000;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2009-12-14 22:08:37 +01:00
|
|
|
p_nand = ioremap(nand_phys, 0x1000);
|
2005-09-23 03:44:58 +02:00
|
|
|
|
|
|
|
/* make controller and MTD agree */
|
|
|
|
if (NAND_CS == 0)
|
2006-05-13 19:07:53 +02:00
|
|
|
nand_width = au_readl(MEM_STCFG0) & (1 << 22);
|
2005-09-23 03:44:58 +02:00
|
|
|
if (NAND_CS == 1)
|
2006-05-13 19:07:53 +02:00
|
|
|
nand_width = au_readl(MEM_STCFG1) & (1 << 22);
|
2005-09-23 03:44:58 +02:00
|
|
|
if (NAND_CS == 2)
|
2006-05-13 19:07:53 +02:00
|
|
|
nand_width = au_readl(MEM_STCFG2) & (1 << 22);
|
2005-09-23 03:44:58 +02:00
|
|
|
if (NAND_CS == 3)
|
2006-05-13 19:07:53 +02:00
|
|
|
nand_width = au_readl(MEM_STCFG3) & (1 << 22);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* Set address of hardware control function */
|
|
|
|
this->dev_ready = au1550_device_ready;
|
NAND: Fix NAND ECC errors on AMD Au1550
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-05-16 18:52:06 +02:00
|
|
|
this->select_chip = au1550_select_chip;
|
|
|
|
this->cmdfunc = au1550_command;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/* 30 us command delay time */
|
2005-11-07 12:15:49 +01:00
|
|
|
this->chip_delay = 30;
|
2006-05-23 12:00:46 +02:00
|
|
|
this->ecc.mode = NAND_ECC_SOFT;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
this->options = NAND_NO_AUTOINCR;
|
|
|
|
|
|
|
|
if (!nand_width)
|
|
|
|
this->options |= NAND_BUSWIDTH_16;
|
|
|
|
|
|
|
|
this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
|
2006-05-23 23:28:48 +02:00
|
|
|
au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
|
2005-04-17 00:20:36 +02:00
|
|
|
this->read_word = au_read_word;
|
|
|
|
this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
|
|
|
|
this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
|
|
|
|
this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
|
|
|
|
|
|
|
|
/* Scan to find existence of the device */
|
2006-05-13 19:07:53 +02:00
|
|
|
if (nand_scan(au1550_mtd, 1)) {
|
2005-04-17 00:20:36 +02:00
|
|
|
retval = -ENXIO;
|
|
|
|
goto outio;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Register the partitions */
|
2006-03-31 12:29:45 +02:00
|
|
|
add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info));
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
outio:
|
2009-12-14 22:08:37 +01:00
|
|
|
iounmap(p_nand);
|
2005-11-07 12:15:49 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
outmem:
|
2006-05-13 19:07:53 +02:00
|
|
|
kfree(au1550_mtd);
|
2005-04-17 00:20:36 +02:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2005-09-23 03:44:58 +02:00
|
|
|
module_init(au1xxx_nand_init);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Clean up routine
|
|
|
|
*/
|
2006-05-13 19:07:53 +02:00
|
|
|
static void __exit au1550_cleanup(void)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
/* Release resources, unregister device */
|
2006-05-13 19:07:53 +02:00
|
|
|
nand_release(au1550_mtd);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* Free the MTD device structure */
|
2006-05-13 19:07:53 +02:00
|
|
|
kfree(au1550_mtd);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* Unmap */
|
2009-12-14 22:08:37 +01:00
|
|
|
iounmap(p_nand);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
2006-05-13 19:07:53 +02:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
module_exit(au1550_cleanup);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Embedded Edge, LLC");
|
|
|
|
MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
|