2008-02-08 13:19:31 +01:00
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/* MN10300 CPU core caching routines
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/smp.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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2010-10-27 18:28:45 +02:00
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#include <asm/irqflags.h>
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#include <asm/cacheflush.h>
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MN10300: The icache invalidate functions should disable the icache first
The icache invalidate functions should disable the icache on AM33 and wait for
it to quiesce before attempting to invalidate it, and should then wait for it
to quiesce again before reenabling it, but on AM34 they should invalidate
directly. The same goes for the dcache invalidation, but this isn't used much.
Whilst we're at it, this can be wrapped in assembler macros to remove duplicate
code.
The AM33 manual states that:
An operation that invalidates the cache, switches the writing mode, or
changes the way mode must be performed after disabling the cache,
checking the busy bit, and confirming that the cache is not in
operation.
for the dcache [sec 2.8.3.2.1]. This is not stated so for the icache [sec
2.8.3.1.1] but the example code there suggests that it is.
Whilst the AM34 manual states that the cache must be disabled for both the
icache [sec 1.8.3.2.1] and the dcache [sec 1.8.3.2.1], the Panasonic hardware
engineers say the manual is wrong and that disabling the caches for
invalidation is wrong.
Furthermore, they say that disabling the caches on the AM34 whilst running an
SMP kernel can lead to incoherency between the various CPU caches and should
thus be avoided.
Signed-off-by: David Howells <dhowells@redhat.com>
2011-03-18 17:54:29 +01:00
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#include "cache.inc"
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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#define mn10300_local_dcache_inv_range_intr_interval \
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2008-02-08 13:19:31 +01:00
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+((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1)
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2010-10-27 18:28:45 +02:00
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#if mn10300_local_dcache_inv_range_intr_interval > 0xff
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2008-02-08 13:19:31 +01:00
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#error MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL must be 8 or less
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#endif
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.am33_2
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2010-10-27 18:28:45 +02:00
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.globl mn10300_local_icache_inv_page
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.globl mn10300_local_icache_inv_range
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.globl mn10300_local_icache_inv_range2
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mn10300_local_icache_inv_page = mn10300_local_icache_inv
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mn10300_local_icache_inv_range = mn10300_local_icache_inv
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mn10300_local_icache_inv_range2 = mn10300_local_icache_inv
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#ifndef CONFIG_SMP
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.globl mn10300_icache_inv
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.globl mn10300_icache_inv_page
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.globl mn10300_icache_inv_range
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.globl mn10300_icache_inv_range2
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.globl mn10300_dcache_inv
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.globl mn10300_dcache_inv_page
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.globl mn10300_dcache_inv_range
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.globl mn10300_dcache_inv_range2
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mn10300_icache_inv = mn10300_local_icache_inv
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mn10300_icache_inv_page = mn10300_local_icache_inv_page
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mn10300_icache_inv_range = mn10300_local_icache_inv_range
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mn10300_icache_inv_range2 = mn10300_local_icache_inv_range2
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mn10300_dcache_inv = mn10300_local_dcache_inv
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mn10300_dcache_inv_page = mn10300_local_dcache_inv_page
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mn10300_dcache_inv_range = mn10300_local_dcache_inv_range
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mn10300_dcache_inv_range2 = mn10300_local_dcache_inv_range2
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#endif /* !CONFIG_SMP */
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2008-02-08 13:19:31 +01:00
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###############################################################################
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#
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2010-10-27 18:28:45 +02:00
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# void mn10300_local_icache_inv(void)
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2008-02-08 13:19:31 +01:00
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# Invalidate the entire icache
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#
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###############################################################################
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ALIGN
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2010-10-27 18:28:45 +02:00
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.globl mn10300_local_icache_inv
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.type mn10300_local_icache_inv,@function
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mn10300_local_icache_inv:
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2008-02-08 13:19:31 +01:00
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mov CHCTR,a0
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movhu (a0),d0
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btst CHCTR_ICEN,d0
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2010-10-27 18:28:45 +02:00
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beq mn10300_local_icache_inv_end
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2008-02-08 13:19:31 +01:00
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MN10300: The icache invalidate functions should disable the icache first
The icache invalidate functions should disable the icache on AM33 and wait for
it to quiesce before attempting to invalidate it, and should then wait for it
to quiesce again before reenabling it, but on AM34 they should invalidate
directly. The same goes for the dcache invalidation, but this isn't used much.
Whilst we're at it, this can be wrapped in assembler macros to remove duplicate
code.
The AM33 manual states that:
An operation that invalidates the cache, switches the writing mode, or
changes the way mode must be performed after disabling the cache,
checking the busy bit, and confirming that the cache is not in
operation.
for the dcache [sec 2.8.3.2.1]. This is not stated so for the icache [sec
2.8.3.1.1] but the example code there suggests that it is.
Whilst the AM34 manual states that the cache must be disabled for both the
icache [sec 1.8.3.2.1] and the dcache [sec 1.8.3.2.1], the Panasonic hardware
engineers say the manual is wrong and that disabling the caches for
invalidation is wrong.
Furthermore, they say that disabling the caches on the AM34 whilst running an
SMP kernel can lead to incoherency between the various CPU caches and should
thus be avoided.
Signed-off-by: David Howells <dhowells@redhat.com>
2011-03-18 17:54:29 +01:00
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invalidate_icache 1
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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mn10300_local_icache_inv_end:
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2008-02-08 13:19:31 +01:00
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ret [],0
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2010-10-27 18:28:45 +02:00
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.size mn10300_local_icache_inv,.-mn10300_local_icache_inv
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2008-02-08 13:19:31 +01:00
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###############################################################################
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#
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2010-10-27 18:28:45 +02:00
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# void mn10300_local_dcache_inv(void)
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2008-02-08 13:19:31 +01:00
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# Invalidate the entire dcache
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#
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###############################################################################
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ALIGN
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2010-10-27 18:28:45 +02:00
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.globl mn10300_local_dcache_inv
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.type mn10300_local_dcache_inv,@function
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mn10300_local_dcache_inv:
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2008-02-08 13:19:31 +01:00
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mov CHCTR,a0
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movhu (a0),d0
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btst CHCTR_DCEN,d0
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2010-10-27 18:28:45 +02:00
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beq mn10300_local_dcache_inv_end
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2008-02-08 13:19:31 +01:00
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MN10300: The icache invalidate functions should disable the icache first
The icache invalidate functions should disable the icache on AM33 and wait for
it to quiesce before attempting to invalidate it, and should then wait for it
to quiesce again before reenabling it, but on AM34 they should invalidate
directly. The same goes for the dcache invalidation, but this isn't used much.
Whilst we're at it, this can be wrapped in assembler macros to remove duplicate
code.
The AM33 manual states that:
An operation that invalidates the cache, switches the writing mode, or
changes the way mode must be performed after disabling the cache,
checking the busy bit, and confirming that the cache is not in
operation.
for the dcache [sec 2.8.3.2.1]. This is not stated so for the icache [sec
2.8.3.1.1] but the example code there suggests that it is.
Whilst the AM34 manual states that the cache must be disabled for both the
icache [sec 1.8.3.2.1] and the dcache [sec 1.8.3.2.1], the Panasonic hardware
engineers say the manual is wrong and that disabling the caches for
invalidation is wrong.
Furthermore, they say that disabling the caches on the AM34 whilst running an
SMP kernel can lead to incoherency between the various CPU caches and should
thus be avoided.
Signed-off-by: David Howells <dhowells@redhat.com>
2011-03-18 17:54:29 +01:00
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invalidate_dcache 1
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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mn10300_local_dcache_inv_end:
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2008-02-08 13:19:31 +01:00
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ret [],0
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2010-10-27 18:28:45 +02:00
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.size mn10300_local_dcache_inv,.-mn10300_local_dcache_inv
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2008-02-08 13:19:31 +01:00
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###############################################################################
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#
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2010-10-27 18:28:45 +02:00
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# void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end)
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# void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size)
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# void mn10300_local_dcache_inv_page(unsigned long start)
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2008-02-08 13:19:31 +01:00
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# Invalidate a range of addresses on a page in the dcache
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#
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###############################################################################
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ALIGN
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2010-10-27 18:28:45 +02:00
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.globl mn10300_local_dcache_inv_page
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.globl mn10300_local_dcache_inv_range
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.globl mn10300_local_dcache_inv_range2
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.type mn10300_local_dcache_inv_page,@function
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.type mn10300_local_dcache_inv_range,@function
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.type mn10300_local_dcache_inv_range2,@function
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mn10300_local_dcache_inv_page:
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and ~(PAGE_SIZE-1),d0
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2008-02-08 13:19:31 +01:00
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mov PAGE_SIZE,d1
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2010-10-27 18:28:45 +02:00
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mn10300_local_dcache_inv_range2:
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2008-02-08 13:19:31 +01:00
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add d0,d1
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2010-10-27 18:28:45 +02:00
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mn10300_local_dcache_inv_range:
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# If we are in writeback mode we check the start and end alignments,
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# and if they're not cacheline-aligned, we must flush any bits outside
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# the range that share cachelines with stuff inside the range
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#ifdef CONFIG_MN10300_CACHE_WBACK
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2011-03-18 17:54:30 +01:00
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btst ~L1_CACHE_TAG_MASK,d0
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2010-10-27 18:28:45 +02:00
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bne 1f
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2011-03-18 17:54:30 +01:00
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btst ~L1_CACHE_TAG_MASK,d1
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2010-10-27 18:28:45 +02:00
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beq 2f
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1:
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bra mn10300_local_dcache_flush_inv_range
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2:
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#endif /* CONFIG_MN10300_CACHE_WBACK */
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2008-02-08 13:19:31 +01:00
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movm [d2,d3,a2],(sp)
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2010-10-27 18:28:45 +02:00
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mov CHCTR,a2
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2008-02-08 13:19:31 +01:00
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movhu (a2),d2
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btst CHCTR_DCEN,d2
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2010-10-27 18:28:45 +02:00
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beq mn10300_local_dcache_inv_range_end
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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#ifndef CONFIG_MN10300_CACHE_WBACK
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2011-03-18 17:54:30 +01:00
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and L1_CACHE_TAG_MASK,d0 # round start addr down
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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add L1_CACHE_BYTES,d1 # round end addr up
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2011-03-18 17:54:30 +01:00
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and L1_CACHE_TAG_MASK,d1
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2010-10-27 18:28:45 +02:00
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#endif /* !CONFIG_MN10300_CACHE_WBACK */
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mov d0,a1
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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clr d2 # we're going to clear tag RAM
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2008-02-08 13:19:31 +01:00
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# entries
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# read the tags from the tag RAM, and if they indicate a valid dirty
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# cache line then invalidate that line
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mov DCACHE_TAG(0,0),a0
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mov a1,d0
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and L1_CACHE_TAG_ENTRY,d0
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add d0,a0 # starting dcache tag RAM
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# access address
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sub a1,d1
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lsr L1_CACHE_SHIFT,d1 # total number of entries to
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# examine
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and ~(L1_CACHE_DISPARITY-1),a1 # determine comparator base
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2010-10-27 18:28:45 +02:00
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mn10300_local_dcache_inv_range_outer_loop:
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LOCAL_CLI_SAVE(d3)
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2008-02-08 13:19:31 +01:00
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# disable the dcache
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movhu (a2),d0
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and ~CHCTR_DCEN,d0
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movhu d0,(a2)
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# and wait for it to calm down
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setlb
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movhu (a2),d0
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btst CHCTR_DCBUSY,d0
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lne
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2010-10-27 18:28:45 +02:00
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mn10300_local_dcache_inv_range_loop:
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2008-02-08 13:19:31 +01:00
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# process the way 0 slot
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mov (L1_CACHE_WAYDISP*0,a0),d0 # read the tag in the way 0 slot
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btst L1_CACHE_TAG_VALID,d0
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2010-10-27 18:28:45 +02:00
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beq mn10300_local_dcache_inv_range_skip_0 # jump if this cacheline
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# is not valid
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2008-02-08 13:19:31 +01:00
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xor a1,d0
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lsr 12,d0
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2010-10-27 18:28:45 +02:00
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bne mn10300_local_dcache_inv_range_skip_0 # jump if not this cacheline
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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mov d2,(L1_CACHE_WAYDISP*0,a0) # kill the tag
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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mn10300_local_dcache_inv_range_skip_0:
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2008-02-08 13:19:31 +01:00
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# process the way 1 slot
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mov (L1_CACHE_WAYDISP*1,a0),d0 # read the tag in the way 1 slot
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btst L1_CACHE_TAG_VALID,d0
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2010-10-27 18:28:45 +02:00
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beq mn10300_local_dcache_inv_range_skip_1 # jump if this cacheline
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# is not valid
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2008-02-08 13:19:31 +01:00
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xor a1,d0
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lsr 12,d0
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2010-10-27 18:28:45 +02:00
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bne mn10300_local_dcache_inv_range_skip_1 # jump if not this cacheline
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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mov d2,(L1_CACHE_WAYDISP*1,a0) # kill the tag
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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mn10300_local_dcache_inv_range_skip_1:
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2008-02-08 13:19:31 +01:00
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# process the way 2 slot
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mov (L1_CACHE_WAYDISP*2,a0),d0 # read the tag in the way 2 slot
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btst L1_CACHE_TAG_VALID,d0
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2010-10-27 18:28:45 +02:00
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beq mn10300_local_dcache_inv_range_skip_2 # jump if this cacheline
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# is not valid
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2008-02-08 13:19:31 +01:00
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xor a1,d0
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lsr 12,d0
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2010-10-27 18:28:45 +02:00
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bne mn10300_local_dcache_inv_range_skip_2 # jump if not this cacheline
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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mov d2,(L1_CACHE_WAYDISP*2,a0) # kill the tag
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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mn10300_local_dcache_inv_range_skip_2:
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2008-02-08 13:19:31 +01:00
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# process the way 3 slot
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mov (L1_CACHE_WAYDISP*3,a0),d0 # read the tag in the way 3 slot
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btst L1_CACHE_TAG_VALID,d0
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2010-10-27 18:28:45 +02:00
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beq mn10300_local_dcache_inv_range_skip_3 # jump if this cacheline
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# is not valid
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2008-02-08 13:19:31 +01:00
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xor a1,d0
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lsr 12,d0
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2010-10-27 18:28:45 +02:00
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bne mn10300_local_dcache_inv_range_skip_3 # jump if not this cacheline
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2008-02-08 13:19:31 +01:00
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2010-10-27 18:28:45 +02:00
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mov d2,(L1_CACHE_WAYDISP*3,a0) # kill the tag
|
2008-02-08 13:19:31 +01:00
|
|
|
|
2010-10-27 18:28:45 +02:00
|
|
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mn10300_local_dcache_inv_range_skip_3:
|
2008-02-08 13:19:31 +01:00
|
|
|
|
|
|
|
# approx every N steps we re-enable the cache and see if there are any
|
|
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|
# interrupts to be processed
|
|
|
|
# we also break out if we've reached the end of the loop
|
|
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# (the bottom nibble of the count is zero in both cases)
|
|
|
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add L1_CACHE_BYTES,a0
|
|
|
|
add L1_CACHE_BYTES,a1
|
2010-10-27 18:28:45 +02:00
|
|
|
and ~L1_CACHE_WAYDISP,a0
|
2008-02-08 13:19:31 +01:00
|
|
|
add -1,d1
|
2010-10-27 18:28:45 +02:00
|
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|
btst mn10300_local_dcache_inv_range_intr_interval,d1
|
|
|
|
bne mn10300_local_dcache_inv_range_loop
|
2008-02-08 13:19:31 +01:00
|
|
|
|
|
|
|
# wait for the cache to finish what it's doing
|
|
|
|
setlb
|
|
|
|
movhu (a2),d0
|
|
|
|
btst CHCTR_DCBUSY,d0
|
|
|
|
lne
|
|
|
|
|
|
|
|
# and reenable it
|
|
|
|
or CHCTR_DCEN,d0
|
|
|
|
movhu d0,(a2)
|
|
|
|
movhu (a2),d0
|
|
|
|
|
|
|
|
# re-enable interrupts
|
|
|
|
# - we don't bother with delay NOPs as we'll have enough instructions
|
|
|
|
# before we disable interrupts again to give the interrupts a chance
|
|
|
|
# to happen
|
2010-10-27 18:28:45 +02:00
|
|
|
LOCAL_IRQ_RESTORE(d3)
|
2008-02-08 13:19:31 +01:00
|
|
|
|
|
|
|
# go around again if the counter hasn't yet reached zero
|
|
|
|
add 0,d1
|
2010-10-27 18:28:45 +02:00
|
|
|
bne mn10300_local_dcache_inv_range_outer_loop
|
2008-02-08 13:19:31 +01:00
|
|
|
|
2010-10-27 18:28:45 +02:00
|
|
|
mn10300_local_dcache_inv_range_end:
|
2008-02-08 13:19:31 +01:00
|
|
|
ret [d2,d3,a2],12
|
2010-10-27 18:28:45 +02:00
|
|
|
.size mn10300_local_dcache_inv_page,.-mn10300_local_dcache_inv_page
|
|
|
|
.size mn10300_local_dcache_inv_range,.-mn10300_local_dcache_inv_range
|
|
|
|
.size mn10300_local_dcache_inv_range2,.-mn10300_local_dcache_inv_range2
|