1032 lines
24 KiB
C
1032 lines
24 KiB
C
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/*
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* Copyright 2017, Nicholas Piggin, IBM Corporation
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* Licensed under GPLv2.
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*/
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#define pr_fmt(fmt) "dt-cpu-ftrs: " fmt
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/jump_label.h>
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#include <linux/memblock.h>
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#include <linux/printk.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/threads.h>
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#include <asm/cputable.h>
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#include <asm/dt_cpu_ftrs.h>
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#include <asm/mmu.h>
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#include <asm/oprofile_impl.h>
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#include <asm/prom.h>
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#include <asm/setup.h>
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/* Device-tree visible constants follow */
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#define ISA_V2_07B 2070
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#define ISA_V3_0B 3000
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#define USABLE_PR (1U << 0)
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#define USABLE_OS (1U << 1)
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#define USABLE_HV (1U << 2)
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#define HV_SUPPORT_HFSCR (1U << 0)
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#define OS_SUPPORT_FSCR (1U << 0)
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/* For parsing, we define all bits set as "NONE" case */
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#define HV_SUPPORT_NONE 0xffffffffU
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#define OS_SUPPORT_NONE 0xffffffffU
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struct dt_cpu_feature {
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const char *name;
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uint32_t isa;
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uint32_t usable_privilege;
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uint32_t hv_support;
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uint32_t os_support;
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uint32_t hfscr_bit_nr;
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uint32_t fscr_bit_nr;
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uint32_t hwcap_bit_nr;
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/* fdt parsing */
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unsigned long node;
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int enabled;
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int disabled;
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};
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#define CPU_FTRS_BASE \
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(CPU_FTR_USE_TB | \
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CPU_FTR_LWSYNC | \
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CPU_FTR_FPU_UNAVAILABLE |\
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CPU_FTR_NODSISRALIGN |\
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CPU_FTR_NOEXECUTE |\
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CPU_FTR_COHERENT_ICACHE | \
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CPU_FTR_STCX_CHECKS_ADDRESS |\
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CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
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CPU_FTR_DAWR | \
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CPU_FTR_ARCH_206 |\
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CPU_FTR_ARCH_207S)
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#define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8)
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#define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \
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PPC_FEATURE_ARCH_2_06 |\
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PPC_FEATURE_ICACHE_SNOOP)
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#define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \
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PPC_FEATURE2_ISEL)
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/*
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* Set up the base CPU
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*/
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extern void __flush_tlb_power8(unsigned int action);
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extern void __flush_tlb_power9(unsigned int action);
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extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
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extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
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static int hv_mode;
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static struct {
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u64 lpcr;
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u64 hfscr;
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u64 fscr;
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} system_registers;
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static void (*init_pmu_registers)(void);
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static void cpufeatures_flush_tlb(void)
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{
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unsigned long rb;
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unsigned int i, num_sets;
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/*
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* This is a temporary measure to keep equivalent TLB flush as the
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* cputable based setup code.
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*/
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switch (PVR_VER(mfspr(SPRN_PVR))) {
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case PVR_POWER8:
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case PVR_POWER8E:
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case PVR_POWER8NVL:
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num_sets = POWER8_TLB_SETS;
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break;
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case PVR_POWER9:
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num_sets = POWER9_TLB_SETS_HASH;
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break;
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default:
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num_sets = 1;
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pr_err("unknown CPU version for boot TLB flush\n");
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break;
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}
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asm volatile("ptesync" : : : "memory");
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rb = TLBIEL_INVAL_SET;
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for (i = 0; i < num_sets; i++) {
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asm volatile("tlbiel %0" : : "r" (rb));
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rb += 1 << TLBIEL_INVAL_SET_SHIFT;
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}
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asm volatile("ptesync" : : : "memory");
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}
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static void __restore_cpu_cpufeatures(void)
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{
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/*
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* LPCR is restored by the power on engine already. It can be changed
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* after early init e.g., by radix enable, and we have no unified API
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* for saving and restoring such SPRs.
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*
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* This ->restore hook should really be removed from idle and register
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* restore moved directly into the idle restore code, because this code
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* doesn't know how idle is implemented or what it needs restored here.
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*
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* The best we can do to accommodate secondary boot and idle restore
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* for now is "or" LPCR with existing.
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*/
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mtspr(SPRN_LPCR, system_registers.lpcr | mfspr(SPRN_LPCR));
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if (hv_mode) {
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_HFSCR, system_registers.hfscr);
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}
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mtspr(SPRN_FSCR, system_registers.fscr);
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if (init_pmu_registers)
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init_pmu_registers();
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cpufeatures_flush_tlb();
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}
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static char dt_cpu_name[64];
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static struct cpu_spec __initdata base_cpu_spec = {
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.cpu_name = NULL,
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.cpu_features = CPU_FTRS_BASE,
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.cpu_user_features = COMMON_USER_BASE,
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.cpu_user_features2 = COMMON_USER2_BASE,
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.mmu_features = 0,
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.icache_bsize = 32, /* minimum block size, fixed by */
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.dcache_bsize = 32, /* cache info init. */
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.num_pmcs = 0,
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.pmc_type = PPC_PMC_DEFAULT,
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.oprofile_cpu_type = NULL,
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.oprofile_type = PPC_OPROFILE_INVALID,
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.cpu_setup = NULL,
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.cpu_restore = __restore_cpu_cpufeatures,
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.flush_tlb = NULL,
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.machine_check_early = NULL,
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.platform = NULL,
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};
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static void __init cpufeatures_setup_cpu(void)
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{
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set_cur_cpu_spec(&base_cpu_spec);
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cur_cpu_spec->pvr_mask = -1;
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cur_cpu_spec->pvr_value = mfspr(SPRN_PVR);
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/* Initialize the base environment -- clear FSCR/HFSCR. */
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hv_mode = !!(mfmsr() & MSR_HV);
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if (hv_mode) {
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/* CPU_FTR_HVMODE is used early in PACA setup */
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cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
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mtspr(SPRN_HFSCR, 0);
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}
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mtspr(SPRN_FSCR, 0);
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/*
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* LPCR does not get cleared, to match behaviour with secondaries
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* in __restore_cpu_cpufeatures. Once the idle code is fixed, this
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* could clear LPCR too.
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*/
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}
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static int __init feat_try_enable_unknown(struct dt_cpu_feature *f)
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{
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if (f->hv_support == HV_SUPPORT_NONE) {
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} else if (f->hv_support & HV_SUPPORT_HFSCR) {
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u64 hfscr = mfspr(SPRN_HFSCR);
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hfscr |= 1UL << f->hfscr_bit_nr;
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mtspr(SPRN_HFSCR, hfscr);
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} else {
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/* Does not have a known recipe */
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return 0;
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}
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if (f->os_support == OS_SUPPORT_NONE) {
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} else if (f->os_support & OS_SUPPORT_FSCR) {
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u64 fscr = mfspr(SPRN_FSCR);
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fscr |= 1UL << f->fscr_bit_nr;
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mtspr(SPRN_FSCR, fscr);
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} else {
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/* Does not have a known recipe */
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return 0;
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}
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if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
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uint32_t word = f->hwcap_bit_nr / 32;
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uint32_t bit = f->hwcap_bit_nr % 32;
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if (word == 0)
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cur_cpu_spec->cpu_user_features |= 1U << bit;
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else if (word == 1)
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cur_cpu_spec->cpu_user_features2 |= 1U << bit;
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else
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pr_err("%s could not advertise to user (no hwcap bits)\n", f->name);
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}
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return 1;
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}
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static int __init feat_enable(struct dt_cpu_feature *f)
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{
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if (f->hv_support != HV_SUPPORT_NONE) {
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if (f->hfscr_bit_nr != -1) {
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u64 hfscr = mfspr(SPRN_HFSCR);
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hfscr |= 1UL << f->hfscr_bit_nr;
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mtspr(SPRN_HFSCR, hfscr);
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}
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}
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if (f->os_support != OS_SUPPORT_NONE) {
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if (f->fscr_bit_nr != -1) {
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u64 fscr = mfspr(SPRN_FSCR);
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fscr |= 1UL << f->fscr_bit_nr;
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mtspr(SPRN_FSCR, fscr);
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}
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}
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if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
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uint32_t word = f->hwcap_bit_nr / 32;
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uint32_t bit = f->hwcap_bit_nr % 32;
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if (word == 0)
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cur_cpu_spec->cpu_user_features |= 1U << bit;
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else if (word == 1)
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cur_cpu_spec->cpu_user_features2 |= 1U << bit;
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else
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pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name);
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}
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return 1;
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}
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static int __init feat_disable(struct dt_cpu_feature *f)
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{
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return 0;
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}
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static int __init feat_enable_hv(struct dt_cpu_feature *f)
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{
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u64 lpcr;
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if (!hv_mode) {
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pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n");
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return 0;
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}
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mtspr(SPRN_LPID, 0);
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lpcr = mfspr(SPRN_LPCR);
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lpcr &= ~LPCR_LPES0; /* HV external interrupts */
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mtspr(SPRN_LPCR, lpcr);
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cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
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return 1;
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}
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static int __init feat_enable_le(struct dt_cpu_feature *f)
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{
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cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE;
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return 1;
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}
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static int __init feat_enable_smt(struct dt_cpu_feature *f)
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{
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cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
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cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT;
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return 1;
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}
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static int __init feat_enable_idle_nap(struct dt_cpu_feature *f)
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{
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u64 lpcr;
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/* Set PECE wakeup modes for ISA 207 */
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lpcr = mfspr(SPRN_LPCR);
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lpcr |= LPCR_PECE0;
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lpcr |= LPCR_PECE1;
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lpcr |= LPCR_PECE2;
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mtspr(SPRN_LPCR, lpcr);
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return 1;
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}
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static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f)
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{
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cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN;
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return 1;
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}
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static int __init feat_enable_idle_stop(struct dt_cpu_feature *f)
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{
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u64 lpcr;
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/* Set PECE wakeup modes for ISAv3.0B */
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lpcr = mfspr(SPRN_LPCR);
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lpcr |= LPCR_PECE0;
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lpcr |= LPCR_PECE1;
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lpcr |= LPCR_PECE2;
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mtspr(SPRN_LPCR, lpcr);
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return 1;
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}
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static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f)
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{
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u64 lpcr;
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lpcr = mfspr(SPRN_LPCR);
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lpcr &= ~LPCR_ISL;
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/* VRMASD */
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lpcr |= LPCR_VPM0;
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lpcr &= ~LPCR_VPM1;
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lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */
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mtspr(SPRN_LPCR, lpcr);
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cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
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cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
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return 1;
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}
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static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
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{
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u64 lpcr;
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lpcr = mfspr(SPRN_LPCR);
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lpcr &= ~LPCR_ISL;
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mtspr(SPRN_LPCR, lpcr);
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cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
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cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
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return 1;
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}
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static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f)
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{
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#ifdef CONFIG_PPC_RADIX_MMU
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cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
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cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
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cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
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return 1;
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#endif
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return 0;
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}
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static int __init feat_enable_dscr(struct dt_cpu_feature *f)
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{
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u64 lpcr;
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feat_enable(f);
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lpcr = mfspr(SPRN_LPCR);
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lpcr &= ~LPCR_DPFD;
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lpcr |= (4UL << LPCR_DPFD_SH);
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mtspr(SPRN_LPCR, lpcr);
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return 1;
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}
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static void hfscr_pmu_enable(void)
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{
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u64 hfscr = mfspr(SPRN_HFSCR);
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hfscr |= PPC_BIT(60);
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mtspr(SPRN_HFSCR, hfscr);
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}
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static void init_pmu_power8(void)
|
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{
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if (hv_mode) {
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||
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mtspr(SPRN_MMCRC, 0);
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||
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mtspr(SPRN_MMCRH, 0);
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||
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}
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mtspr(SPRN_MMCRA, 0);
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mtspr(SPRN_MMCR0, 0);
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mtspr(SPRN_MMCR1, 0);
|
||
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mtspr(SPRN_MMCR2, 0);
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||
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mtspr(SPRN_MMCRS, 0);
|
||
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}
|
||
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|
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static int __init feat_enable_mce_power8(struct dt_cpu_feature *f)
|
||
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{
|
||
|
cur_cpu_spec->platform = "power8";
|
||
|
cur_cpu_spec->flush_tlb = __flush_tlb_power8;
|
||
|
cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8;
|
||
|
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
hfscr_pmu_enable();
|
||
|
|
||
|
init_pmu_power8();
|
||
|
init_pmu_registers = init_pmu_power8;
|
||
|
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
|
||
|
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
|
||
|
if (pvr_version_is(PVR_POWER8E))
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG;
|
||
|
|
||
|
cur_cpu_spec->num_pmcs = 6;
|
||
|
cur_cpu_spec->pmc_type = PPC_PMC_IBM;
|
||
|
cur_cpu_spec->oprofile_cpu_type = "ppc64/power8";
|
||
|
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
static void init_pmu_power9(void)
|
||
|
{
|
||
|
if (hv_mode)
|
||
|
mtspr(SPRN_MMCRC, 0);
|
||
|
|
||
|
mtspr(SPRN_MMCRA, 0);
|
||
|
mtspr(SPRN_MMCR0, 0);
|
||
|
mtspr(SPRN_MMCR1, 0);
|
||
|
mtspr(SPRN_MMCR2, 0);
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_mce_power9(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
cur_cpu_spec->platform = "power9";
|
||
|
cur_cpu_spec->flush_tlb = __flush_tlb_power9;
|
||
|
cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9;
|
||
|
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
hfscr_pmu_enable();
|
||
|
|
||
|
init_pmu_power9();
|
||
|
init_pmu_registers = init_pmu_power9;
|
||
|
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
|
||
|
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
|
||
|
|
||
|
cur_cpu_spec->num_pmcs = 6;
|
||
|
cur_cpu_spec->pmc_type = PPC_PMC_IBM;
|
||
|
cur_cpu_spec->oprofile_cpu_type = "ppc64/power9";
|
||
|
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_tm(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||
|
feat_enable(f);
|
||
|
cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC;
|
||
|
return 1;
|
||
|
#endif
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_fp(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
feat_enable(f);
|
||
|
cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE;
|
||
|
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_vector(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
#ifdef CONFIG_ALTIVEC
|
||
|
feat_enable(f);
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY;
|
||
|
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
|
||
|
|
||
|
return 1;
|
||
|
#endif
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_vsx(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
#ifdef CONFIG_VSX
|
||
|
feat_enable(f);
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_VSX;
|
||
|
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX;
|
||
|
|
||
|
return 1;
|
||
|
#endif
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_purr(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR;
|
||
|
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_ebb(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
/*
|
||
|
* PPC_FEATURE2_EBB is enabled in PMU init code because it has
|
||
|
* historically been related to the PMU facility. This may have
|
||
|
* to be decoupled if EBB becomes more generic. For now, follow
|
||
|
* existing convention.
|
||
|
*/
|
||
|
f->hwcap_bit_nr = -1;
|
||
|
feat_enable(f);
|
||
|
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_dbell(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
u64 lpcr;
|
||
|
|
||
|
/* P9 has an HFSCR for privileged state */
|
||
|
feat_enable(f);
|
||
|
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_DBELL;
|
||
|
|
||
|
lpcr = mfspr(SPRN_LPCR);
|
||
|
lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */
|
||
|
mtspr(SPRN_LPCR, lpcr);
|
||
|
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_hvi(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
u64 lpcr;
|
||
|
|
||
|
/*
|
||
|
* POWER9 XIVE interrupts including in OPAL XICS compatibility
|
||
|
* are always delivered as hypervisor virtualization interrupts (HVI)
|
||
|
* rather than EE.
|
||
|
*
|
||
|
* However LPES0 is not set here, in the chance that an EE does get
|
||
|
* delivered to the host somehow, the EE handler would not expect it
|
||
|
* to be delivered in LPES0 mode (e.g., using SRR[01]). This could
|
||
|
* happen if there is a bug in interrupt controller code, or IC is
|
||
|
* misconfigured in systemsim.
|
||
|
*/
|
||
|
|
||
|
lpcr = mfspr(SPRN_LPCR);
|
||
|
lpcr |= LPCR_HVICE; /* enable hvi interrupts */
|
||
|
lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */
|
||
|
lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */
|
||
|
mtspr(SPRN_LPCR, lpcr);
|
||
|
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE;
|
||
|
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
struct dt_cpu_feature_match {
|
||
|
const char *name;
|
||
|
int (*enable)(struct dt_cpu_feature *f);
|
||
|
u64 cpu_ftr_bit_mask;
|
||
|
};
|
||
|
|
||
|
static struct dt_cpu_feature_match __initdata
|
||
|
dt_cpu_feature_match_table[] = {
|
||
|
{"hypervisor", feat_enable_hv, 0},
|
||
|
{"big-endian", feat_enable, 0},
|
||
|
{"little-endian", feat_enable_le, CPU_FTR_REAL_LE},
|
||
|
{"smt", feat_enable_smt, 0},
|
||
|
{"interrupt-facilities", feat_enable, 0},
|
||
|
{"timer-facilities", feat_enable, 0},
|
||
|
{"timer-facilities-v3", feat_enable, 0},
|
||
|
{"debug-facilities", feat_enable, 0},
|
||
|
{"come-from-address-register", feat_enable, CPU_FTR_CFAR},
|
||
|
{"branch-tracing", feat_enable, 0},
|
||
|
{"floating-point", feat_enable_fp, 0},
|
||
|
{"vector", feat_enable_vector, 0},
|
||
|
{"vector-scalar", feat_enable_vsx, 0},
|
||
|
{"vector-scalar-v3", feat_enable, 0},
|
||
|
{"decimal-floating-point", feat_enable, 0},
|
||
|
{"decimal-integer", feat_enable, 0},
|
||
|
{"quadword-load-store", feat_enable, 0},
|
||
|
{"vector-crypto", feat_enable, 0},
|
||
|
{"mmu-hash", feat_enable_mmu_hash, 0},
|
||
|
{"mmu-radix", feat_enable_mmu_radix, 0},
|
||
|
{"mmu-hash-v3", feat_enable_mmu_hash_v3, 0},
|
||
|
{"virtual-page-class-key-protection", feat_enable, 0},
|
||
|
{"transactional-memory", feat_enable_tm, CPU_FTR_TM},
|
||
|
{"transactional-memory-v3", feat_enable_tm, 0},
|
||
|
{"idle-nap", feat_enable_idle_nap, 0},
|
||
|
{"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0},
|
||
|
{"idle-stop", feat_enable_idle_stop, 0},
|
||
|
{"machine-check-power8", feat_enable_mce_power8, 0},
|
||
|
{"performance-monitor-power8", feat_enable_pmu_power8, 0},
|
||
|
{"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR},
|
||
|
{"event-based-branch", feat_enable_ebb, 0},
|
||
|
{"target-address-register", feat_enable, 0},
|
||
|
{"branch-history-rolling-buffer", feat_enable, 0},
|
||
|
{"control-register", feat_enable, CPU_FTR_CTRL},
|
||
|
{"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL},
|
||
|
{"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},
|
||
|
{"processor-utilization-of-resources-register", feat_enable_purr, 0},
|
||
|
{"subcore", feat_enable, CPU_FTR_SUBCORE},
|
||
|
{"no-execute", feat_enable, 0},
|
||
|
{"strong-access-ordering", feat_enable, CPU_FTR_SAO},
|
||
|
{"cache-inhibited-large-page", feat_enable_large_ci, 0},
|
||
|
{"coprocessor-icswx", feat_enable, CPU_FTR_ICSWX},
|
||
|
{"hypervisor-virtualization-interrupt", feat_enable_hvi, 0},
|
||
|
{"program-priority-register", feat_enable, CPU_FTR_HAS_PPR},
|
||
|
{"wait", feat_enable, 0},
|
||
|
{"atomic-memory-operations", feat_enable, 0},
|
||
|
{"branch-v3", feat_enable, 0},
|
||
|
{"copy-paste", feat_enable, 0},
|
||
|
{"decimal-floating-point-v3", feat_enable, 0},
|
||
|
{"decimal-integer-v3", feat_enable, 0},
|
||
|
{"fixed-point-v3", feat_enable, 0},
|
||
|
{"floating-point-v3", feat_enable, 0},
|
||
|
{"group-start-register", feat_enable, 0},
|
||
|
{"pc-relative-addressing", feat_enable, 0},
|
||
|
{"machine-check-power9", feat_enable_mce_power9, 0},
|
||
|
{"performance-monitor-power9", feat_enable_pmu_power9, 0},
|
||
|
{"event-based-branch-v3", feat_enable, 0},
|
||
|
{"random-number-generator", feat_enable, 0},
|
||
|
{"system-call-vectored", feat_disable, 0},
|
||
|
{"trace-interrupt-v3", feat_enable, 0},
|
||
|
{"vector-v3", feat_enable, 0},
|
||
|
{"vector-binary128", feat_enable, 0},
|
||
|
{"vector-binary16", feat_enable, 0},
|
||
|
{"wait-v3", feat_enable, 0},
|
||
|
};
|
||
|
|
||
|
/* XXX: how to configure this? Default + boot time? */
|
||
|
#ifdef CONFIG_PPC_CPUFEATURES_ENABLE_UNKNOWN
|
||
|
#define CPU_FEATURE_ENABLE_UNKNOWN 1
|
||
|
#else
|
||
|
#define CPU_FEATURE_ENABLE_UNKNOWN 0
|
||
|
#endif
|
||
|
|
||
|
static void __init cpufeatures_setup_start(u32 isa)
|
||
|
{
|
||
|
pr_info("setup for ISA %d\n", isa);
|
||
|
|
||
|
if (isa >= 3000) {
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300;
|
||
|
cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
const struct dt_cpu_feature_match *m;
|
||
|
bool known = false;
|
||
|
int i;
|
||
|
|
||
|
for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) {
|
||
|
m = &dt_cpu_feature_match_table[i];
|
||
|
if (!strcmp(f->name, m->name)) {
|
||
|
known = true;
|
||
|
if (m->enable(f))
|
||
|
break;
|
||
|
|
||
|
pr_info("not enabling: %s (disabled or unsupported by kernel)\n",
|
||
|
f->name);
|
||
|
return false;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (!known && CPU_FEATURE_ENABLE_UNKNOWN) {
|
||
|
if (!feat_try_enable_unknown(f)) {
|
||
|
pr_info("not enabling: %s (unknown and unsupported by kernel)\n",
|
||
|
f->name);
|
||
|
return false;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (m->cpu_ftr_bit_mask)
|
||
|
cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask;
|
||
|
|
||
|
if (known)
|
||
|
pr_debug("enabling: %s\n", f->name);
|
||
|
else
|
||
|
pr_debug("enabling: %s (unknown)\n", f->name);
|
||
|
|
||
|
return true;
|
||
|
}
|
||
|
|
||
|
static __init void cpufeatures_cpu_quirks(void)
|
||
|
{
|
||
|
int version = mfspr(SPRN_PVR);
|
||
|
|
||
|
/*
|
||
|
* Not all quirks can be derived from the cpufeatures device tree.
|
||
|
*/
|
||
|
if ((version & 0xffffff00) == 0x004e0100)
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD1;
|
||
|
}
|
||
|
|
||
|
static void __init cpufeatures_setup_finished(void)
|
||
|
{
|
||
|
cpufeatures_cpu_quirks();
|
||
|
|
||
|
if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) {
|
||
|
pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n");
|
||
|
cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
|
||
|
}
|
||
|
|
||
|
system_registers.lpcr = mfspr(SPRN_LPCR);
|
||
|
system_registers.hfscr = mfspr(SPRN_HFSCR);
|
||
|
system_registers.fscr = mfspr(SPRN_FSCR);
|
||
|
|
||
|
cpufeatures_flush_tlb();
|
||
|
|
||
|
pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
|
||
|
cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
|
||
|
}
|
||
|
|
||
|
static int __init fdt_find_cpu_features(unsigned long node, const char *uname,
|
||
|
int depth, void *data)
|
||
|
{
|
||
|
if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")
|
||
|
&& of_get_flat_dt_prop(node, "isa", NULL))
|
||
|
return 1;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static bool __initdata using_dt_cpu_ftrs = false;
|
||
|
|
||
|
bool __init dt_cpu_ftrs_in_use(void)
|
||
|
{
|
||
|
return using_dt_cpu_ftrs;
|
||
|
}
|
||
|
|
||
|
bool __init dt_cpu_ftrs_init(void *fdt)
|
||
|
{
|
||
|
/* Setup and verify the FDT, if it fails we just bail */
|
||
|
if (!early_init_dt_verify(fdt))
|
||
|
return false;
|
||
|
|
||
|
if (!of_scan_flat_dt(fdt_find_cpu_features, NULL))
|
||
|
return false;
|
||
|
|
||
|
cpufeatures_setup_cpu();
|
||
|
|
||
|
using_dt_cpu_ftrs = true;
|
||
|
return true;
|
||
|
}
|
||
|
|
||
|
static int nr_dt_cpu_features;
|
||
|
static struct dt_cpu_feature *dt_cpu_features;
|
||
|
|
||
|
static int __init process_cpufeatures_node(unsigned long node,
|
||
|
const char *uname, int i)
|
||
|
{
|
||
|
const __be32 *prop;
|
||
|
struct dt_cpu_feature *f;
|
||
|
int len;
|
||
|
|
||
|
f = &dt_cpu_features[i];
|
||
|
memset(f, 0, sizeof(struct dt_cpu_feature));
|
||
|
|
||
|
f->node = node;
|
||
|
|
||
|
f->name = uname;
|
||
|
|
||
|
prop = of_get_flat_dt_prop(node, "isa", &len);
|
||
|
if (!prop) {
|
||
|
pr_warn("%s: missing isa property\n", uname);
|
||
|
return 0;
|
||
|
}
|
||
|
f->isa = be32_to_cpup(prop);
|
||
|
|
||
|
prop = of_get_flat_dt_prop(node, "usable-privilege", &len);
|
||
|
if (!prop) {
|
||
|
pr_warn("%s: missing usable-privilege property", uname);
|
||
|
return 0;
|
||
|
}
|
||
|
f->usable_privilege = be32_to_cpup(prop);
|
||
|
|
||
|
prop = of_get_flat_dt_prop(node, "hv-support", &len);
|
||
|
if (prop)
|
||
|
f->hv_support = be32_to_cpup(prop);
|
||
|
else
|
||
|
f->hv_support = HV_SUPPORT_NONE;
|
||
|
|
||
|
prop = of_get_flat_dt_prop(node, "os-support", &len);
|
||
|
if (prop)
|
||
|
f->os_support = be32_to_cpup(prop);
|
||
|
else
|
||
|
f->os_support = OS_SUPPORT_NONE;
|
||
|
|
||
|
prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len);
|
||
|
if (prop)
|
||
|
f->hfscr_bit_nr = be32_to_cpup(prop);
|
||
|
else
|
||
|
f->hfscr_bit_nr = -1;
|
||
|
prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len);
|
||
|
if (prop)
|
||
|
f->fscr_bit_nr = be32_to_cpup(prop);
|
||
|
else
|
||
|
f->fscr_bit_nr = -1;
|
||
|
prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len);
|
||
|
if (prop)
|
||
|
f->hwcap_bit_nr = be32_to_cpup(prop);
|
||
|
else
|
||
|
f->hwcap_bit_nr = -1;
|
||
|
|
||
|
if (f->usable_privilege & USABLE_HV) {
|
||
|
if (!(mfmsr() & MSR_HV)) {
|
||
|
pr_warn("%s: HV feature passed to guest\n", uname);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) {
|
||
|
pr_warn("%s: unwanted hfscr_bit_nr\n", uname);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
if (f->hv_support == HV_SUPPORT_HFSCR) {
|
||
|
if (f->hfscr_bit_nr == -1) {
|
||
|
pr_warn("%s: missing hfscr_bit_nr\n", uname);
|
||
|
return 0;
|
||
|
}
|
||
|
}
|
||
|
} else {
|
||
|
if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) {
|
||
|
pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname);
|
||
|
return 0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (f->usable_privilege & USABLE_OS) {
|
||
|
if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) {
|
||
|
pr_warn("%s: unwanted fscr_bit_nr\n", uname);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
if (f->os_support == OS_SUPPORT_FSCR) {
|
||
|
if (f->fscr_bit_nr == -1) {
|
||
|
pr_warn("%s: missing fscr_bit_nr\n", uname);
|
||
|
return 0;
|
||
|
}
|
||
|
}
|
||
|
} else {
|
||
|
if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) {
|
||
|
pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname);
|
||
|
return 0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (!(f->usable_privilege & USABLE_PR)) {
|
||
|
if (f->hwcap_bit_nr != -1) {
|
||
|
pr_warn("%s: unwanted hwcap_bit_nr\n", uname);
|
||
|
return 0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* Do all the independent features in the first pass */
|
||
|
if (!of_get_flat_dt_prop(node, "dependencies", &len)) {
|
||
|
if (cpufeatures_process_feature(f))
|
||
|
f->enabled = 1;
|
||
|
else
|
||
|
f->disabled = 1;
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f)
|
||
|
{
|
||
|
const __be32 *prop;
|
||
|
int len;
|
||
|
int nr_deps;
|
||
|
int i;
|
||
|
|
||
|
if (f->enabled || f->disabled)
|
||
|
return;
|
||
|
|
||
|
prop = of_get_flat_dt_prop(f->node, "dependencies", &len);
|
||
|
if (!prop) {
|
||
|
pr_warn("%s: missing dependencies property", f->name);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
nr_deps = len / sizeof(int);
|
||
|
|
||
|
for (i = 0; i < nr_deps; i++) {
|
||
|
unsigned long phandle = be32_to_cpu(prop[i]);
|
||
|
int j;
|
||
|
|
||
|
for (j = 0; j < nr_dt_cpu_features; j++) {
|
||
|
struct dt_cpu_feature *d = &dt_cpu_features[j];
|
||
|
|
||
|
if (of_get_flat_dt_phandle(d->node) == phandle) {
|
||
|
cpufeatures_deps_enable(d);
|
||
|
if (d->disabled) {
|
||
|
f->disabled = 1;
|
||
|
return;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (cpufeatures_process_feature(f))
|
||
|
f->enabled = 1;
|
||
|
else
|
||
|
f->disabled = 1;
|
||
|
}
|
||
|
|
||
|
static int __init scan_cpufeatures_subnodes(unsigned long node,
|
||
|
const char *uname,
|
||
|
void *data)
|
||
|
{
|
||
|
int *count = data;
|
||
|
|
||
|
process_cpufeatures_node(node, uname, *count);
|
||
|
|
||
|
(*count)++;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int __init count_cpufeatures_subnodes(unsigned long node,
|
||
|
const char *uname,
|
||
|
void *data)
|
||
|
{
|
||
|
int *count = data;
|
||
|
|
||
|
(*count)++;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char
|
||
|
*uname, int depth, void *data)
|
||
|
{
|
||
|
const __be32 *prop;
|
||
|
int count, i;
|
||
|
u32 isa;
|
||
|
|
||
|
/* We are scanning "ibm,powerpc-cpu-features" nodes only */
|
||
|
if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features"))
|
||
|
return 0;
|
||
|
|
||
|
prop = of_get_flat_dt_prop(node, "isa", NULL);
|
||
|
if (!prop)
|
||
|
/* We checked before, "can't happen" */
|
||
|
return 0;
|
||
|
|
||
|
isa = be32_to_cpup(prop);
|
||
|
|
||
|
/* Count and allocate space for cpu features */
|
||
|
of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes,
|
||
|
&nr_dt_cpu_features);
|
||
|
dt_cpu_features = __va(
|
||
|
memblock_alloc(sizeof(struct dt_cpu_feature)*
|
||
|
nr_dt_cpu_features, PAGE_SIZE));
|
||
|
|
||
|
cpufeatures_setup_start(isa);
|
||
|
|
||
|
/* Scan nodes into dt_cpu_features and enable those without deps */
|
||
|
count = 0;
|
||
|
of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count);
|
||
|
|
||
|
/* Recursive enable remaining features with dependencies */
|
||
|
for (i = 0; i < nr_dt_cpu_features; i++) {
|
||
|
struct dt_cpu_feature *f = &dt_cpu_features[i];
|
||
|
|
||
|
cpufeatures_deps_enable(f);
|
||
|
}
|
||
|
|
||
|
prop = of_get_flat_dt_prop(node, "display-name", NULL);
|
||
|
if (prop && strlen((char *)prop) != 0) {
|
||
|
strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name));
|
||
|
cur_cpu_spec->cpu_name = dt_cpu_name;
|
||
|
}
|
||
|
|
||
|
cpufeatures_setup_finished();
|
||
|
|
||
|
memblock_free(__pa(dt_cpu_features),
|
||
|
sizeof(struct dt_cpu_feature)*nr_dt_cpu_features);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
void __init dt_cpu_ftrs_scan(void)
|
||
|
{
|
||
|
of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL);
|
||
|
}
|