2017-11-03 11:28:30 +01:00
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// SPDX-License-Identifier: GPL-2.0
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2012-05-11 16:25:46 +02:00
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/*
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* core.c - ChipIdea USB IP core family device controller
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*
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* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
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*
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* Author: David Lopo
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*/
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/*
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* Description: ChipIdea USB IP core family device controller
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*
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* This driver is composed of several blocks:
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* - HW: hardware interface
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* - DBG: debug facilities (optional)
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* - UTIL: utilities
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* - ISR: interrupts handling
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* - ENDPT: endpoint operations (Gadget API)
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* - GADGET: gadget operations (Gadget API)
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* - BUS: bus glue code, bus abstraction layer
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*
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* Compile Options
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* - STALL_IN: non-empty bulk-in pipes cannot be halted
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* if defined mass storage compliance succeeds but with warnings
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* => case 4: Hi > Dn
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* => case 5: Hi > Di
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* => case 8: Hi <> Do
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* if undefined usbtest 13 fails
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* - TRACE: enable function tracing (depends on DEBUG)
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*
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* Main Features
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* - Chapter 9 & Mass Storage Compliance with Gadget File Storage
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* - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
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* - Normal & LPM support
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*
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* USBTEST Report
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* - OK: 0-12, 13 (STALL_IN defined) & 14
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* - Not Supported: 15 & 16 (ISO)
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*
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* TODO List
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* - Suspend & Remote Wakeup
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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2015-09-07 13:45:25 +02:00
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#include <linux/extcon.h>
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2014-10-30 18:41:19 +01:00
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#include <linux/phy/phy.h>
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2012-05-11 16:25:46 +02:00
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#include <linux/platform_device.h>
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#include <linux/module.h>
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2012-07-07 16:56:42 +02:00
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#include <linux/idr.h>
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2012-05-11 16:25:46 +02:00
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/chipidea.h>
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2013-06-13 16:59:56 +02:00
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#include <linux/usb/of.h>
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2014-02-19 06:41:43 +01:00
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#include <linux/of.h>
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2013-08-14 11:44:03 +02:00
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#include <linux/regulator/consumer.h>
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usb: chipidea: define stream mode disable for both roles
The system bus and chipidea IP have different limitations for
both host and device mode.
For example, with below errata, we need to enable SDIS(Stream Disable
Mode) at host mode. But we don't want it for device mode at the
same system.
TAR 9000378958
Title: Non-Double Word Aligned Buffer Address Sometimes Causes Host to
Hang on OUT Retry
Impacted Configuration: Host mode, all transfer types
Description:
The host core operating in streaming mode may under run while sending
the data packet of an OUT transaction. This under run can occur if
there are unexpected system delays in fetching the remaining packet
data from memory. The host forces a bad CRC on the packet, the device
detects the error and discards the packet. The host then retries a Bulk,
Interrupt, or Control transfer if an under run occurs according to the
USB specification. During simulations, it was found that the host does
not issue the retry of the failed bulk OUT. It does not issue any other
transactions except SOF packets that have incorrect frame numbers.
The second failure mode occurs if the under run occurs on an ISO OUT
transaction and the next ISO transaction is a zero byte packet. The host
does not issue any transactions (including SOFs). The device detects a
Suspend condition, reverts to full speed, and waits for resume signaling.
A third failure mode occurs when the host under runs on an ISO OUT and
the next ISO in the schedule is an ISO OUT with two max packets of 1024
bytes each. The host should issue MDATA for the first OUT followed by
DATA1 for the second. However, it drops the MDATA transaction, and
issues the DATA1 transaction.
The system impact of this bug is the same regardless of the failure mode
observed. The host core hangs, the ehci_ctrl state machine waits for the
protocol engine to send the completion status for the corrupted
transaction, which never occurs. No indication is sent to the host
controller driver, no register bits change and no interrupts occur.
Eventually the requesting application times out.
Detailed internal behavior:
The EHCI control state machine (ehci_ctrl) in the DMA block is responsible
for parsing the schedules and initiating all transactions. The ehci_ctrl
state machine passes the transaction details to the protocol block by
writing the transaction information in to the TxFIFO. It then asserts
the pe_hst_run_pkt signal to inform the host protocol state machine
(pe_hst_state) that there is a packet in the TxFIFO.
A tag of 0x0 indicates a start of packet with the data providing the
following information:
35:32 Tag
31:30 Reserved
29:23 Endpoint (lowest 4 bits)
22:16 Address
15:10 Reserved
9:8 Endpoint speed
7:6 Endpoint type
5:6 Data Toggle
3:0 PID
The pe_hst_state reads the packet information and constructs the packet
and issues it to the PHY interface.
The ehci_ctrl state machine writes the start transaction information in
to the TxFIFO as 0x03002910c for the OUT packet that had the under run
error. However, it writes 0xC3002910C for the retry of the Out
transaction, which is incorrect.
The pe_hst_state enters a bus timeout state after sending the bad CRC
for the packet that under ran. It then purges any data that was back
filled in to the TxFIFO for the packet that under ran. The pe_hst_state
machine stops purging the TxFIFO when it is empty or if it reads a
location that has a tag of 0x0, indicating a start of packet command.
The pe_hst_state reads 0xC3002910C and discards it as it does not decode
to a start of packet command. It continues to purge the OUT data that
has been pre-buffered for the OUT retry . The pe_hst_state detects the
hst_packet_run signal and attempts to read the PID and address
information from the TxFIFO. This location has packet data and so does
not decode to a valid PID and so falls through to the PE_HST_SOF_LOAD
state where the frame_num_counter is updated. The frame_num_counter
is updated with the data in the TxFIFO. In this case, the data is
incorrect as the ehci_ctrl state machine did not initiate the load.
The hst_pe_state machine detects the SOF request signal and sends an
SOF with the bad frame number. Meanwhile, the ehci_ctrl state machine
waits indefinitely in the run_pkt state waiting for the completion
status from pe_hst_state machine, which will never happen.
The ISO failure case is similar except that there is no retry for ISO.
The ehci_ctrl state machine moves to the next transfer in the periodic
schedule. If the under run occurs on the last entry of the periodic
list then it moves to the Async schedule.
In the case of ISO OUT simulations, the next ISO is a zero byte OUT
and again the start of packet command gets corrupted. The TxFIFO is
empty when the hst_pe_state attempts to read the Address and PID
information as the transaction is a zero byte packet. This results
in the hst_pe_state machine staying in the GET_PID state, which means
that it does not issue any transactions (including SOFs). The device
detects a Suspend condition and reverts to full speed mode and waits
for a Resume or Reset signal.
The EHCI specification allows a Non-DoubleWord (32 bits) offset to
be used as a current offset for Buffer Pointer Page 0 of the qTD.
In Non-DoubleWord aligned cases, the core reads the packet data
from the AHB memory, performs the alignment operation before writing
it in to the TxFIFO as a 32 bit data word. An End Of Packet tag (EOP)
is written to the TxFIFO after all the packet data has been written
in to the TxFIFO. The alignment function is reset to Idle by the EOP
tag. The corruption of the start of packet command arises because the
packet buffer for the OUT transaction that under ran is not aligned
to a DoubleWord, and hence no EOP tag is written to the TxFIFO. The
alignment function is still active when the start packet information
is written in to the TxFIFO for the retry of the bulk packet or for
the next transaction in the case of an under run on an ISO. This
results in the corruption of the start tag and the transaction
information.
Click for waveform showing the command 0x 0000300291 being written in
to the TX FIFO for the Out that under ran.
Click for waveform showing the command 0xC3002910C written to the
TxFIFO instead of 0x 0000300291
Versions affected: Versions 2.10a and previous versions
How discovered: Customer simulation
Workaround:
1- The EHCI specification allows a non-DoubleWord offset to be used
as a current offset for Buffer Pointer Page 0 of the qTD. However,
if a DoubleWord offset is used then this issue does not arise.
2- Use non streaming mode to eliminate under runs.
Resolution:
The fix involves changes to the traffic state machine in the
vusb_hs_dma_traf block. The ehci_ctrl state machine updates the context
information by encoding the transaction results on the
hst_op_context_update signals at the end of a transaction. The signal
hst_op_context_update is added to the traffic state machine, and the
tx_fifo_under_ran_r signal is generated if the transaction results in
an under run error. Click for waveform
The traffic state machine then traverses to the do_eop states if the
tx_fifo_under_ran error is asserted. Thus an EOP tag is written in to
the TxFIFO as shown in this waveform .
The EOP tag resets the align state machine to the Idle state ensuring
that the next command written by the echi_ctrl state machine does not
get corrupted.
File(s) modified:
RTL code fixed: …..
Method of reproducing: This failure cannot be reproduced in the current
test bench.
Date Found: March 2010
Date Fixed: June 2010
Update information:
Added the RTL code fix
Signed-off-by: Peter Chen <peter.chen@freescale.com>
2014-10-30 02:15:15 +01:00
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#include <linux/usb/ehci_def.h>
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2012-05-11 16:25:46 +02:00
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#include "ci.h"
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#include "udc.h"
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#include "bits.h"
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2012-05-11 16:25:54 +02:00
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#include "host.h"
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2013-08-14 11:44:06 +02:00
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#include "otg.h"
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2014-04-23 09:56:50 +02:00
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#include "otg_fsm.h"
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2012-05-11 16:25:46 +02:00
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2012-05-11 16:25:47 +02:00
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/* Controller register map */
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2014-01-06 03:10:39 +01:00
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static const u8 ci_regs_nolpm[] = {
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[CAP_CAPLENGTH] = 0x00U,
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[CAP_HCCPARAMS] = 0x08U,
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[CAP_DCCPARAMS] = 0x24U,
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[CAP_TESTMODE] = 0x38U,
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[OP_USBCMD] = 0x00U,
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[OP_USBSTS] = 0x04U,
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[OP_USBINTR] = 0x08U,
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[OP_DEVICEADDR] = 0x14U,
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[OP_ENDPTLISTADDR] = 0x18U,
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usb: chipidea: add ttctrl.ttha control interface
The register of ttctrl.ttha describes like below:
- Internal TT Hub Address Representation
- RW
- Default = 0000000b
This field is used to match against the Hub Address field in QH & siTD
to determine if the packet is routed to the internal TT for directly
attached FS/LS devices. If the Hub Address in the QH or siTD does not
match this address then the packet will be broadcast on the High Speed
ports destined for a downstream High Speed hub with the address in the QH/siTD.
In silicon RTL, this entry only affects QH and siTD, and the hub.addr at
both QH and siTD are 0 in ehci core for chipidea (with hcd->has_tt = 1).
So, for QH, if the "usage_tt" flag at RTL is 0, set CI_HDRC_SET_NON_ZERO_TTHA
will not affect QH (with non-hs device); for siTD, set this flag
will change remaining space requirement for the last transaction from 1023
bytes to 188 bytes, it can increase the number of transactions within one
frame, ehci periodic schedule code will not queue the packet if the frame space
is full, so it is safe to set this flag for siTD.
With this flag, it can fix the problem Alan Stern reported below:
http://www.spinics.net/lists/linux-usb/msg123125.html
And may fix Michael Tessier's problem too.
http://www.spinics.net/lists/linux-usb/msg118679.html
CC: stern@rowland.harvard.edu
CC: michael.tessier@axiontech.ca
Signed-off-by: Peter Chen <peter.chen@freescale.com>
2015-06-18 05:51:53 +02:00
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[OP_TTCTRL] = 0x1CU,
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2015-03-17 10:32:45 +01:00
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[OP_BURSTSIZE] = 0x20U,
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2016-12-28 23:56:55 +01:00
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[OP_ULPI_VIEWPORT] = 0x30U,
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2014-01-06 03:10:39 +01:00
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[OP_PORTSC] = 0x44U,
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[OP_DEVLC] = 0x84U,
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[OP_OTGSC] = 0x64U,
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[OP_USBMODE] = 0x68U,
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[OP_ENDPTSETUPSTAT] = 0x6CU,
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[OP_ENDPTPRIME] = 0x70U,
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[OP_ENDPTFLUSH] = 0x74U,
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[OP_ENDPTSTAT] = 0x78U,
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[OP_ENDPTCOMPLETE] = 0x7CU,
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[OP_ENDPTCTRL] = 0x80U,
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2012-05-11 16:25:46 +02:00
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};
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2014-01-06 03:10:39 +01:00
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static const u8 ci_regs_lpm[] = {
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[CAP_CAPLENGTH] = 0x00U,
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[CAP_HCCPARAMS] = 0x08U,
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[CAP_DCCPARAMS] = 0x24U,
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[CAP_TESTMODE] = 0xFCU,
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[OP_USBCMD] = 0x00U,
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[OP_USBSTS] = 0x04U,
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[OP_USBINTR] = 0x08U,
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[OP_DEVICEADDR] = 0x14U,
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[OP_ENDPTLISTADDR] = 0x18U,
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usb: chipidea: add ttctrl.ttha control interface
The register of ttctrl.ttha describes like below:
- Internal TT Hub Address Representation
- RW
- Default = 0000000b
This field is used to match against the Hub Address field in QH & siTD
to determine if the packet is routed to the internal TT for directly
attached FS/LS devices. If the Hub Address in the QH or siTD does not
match this address then the packet will be broadcast on the High Speed
ports destined for a downstream High Speed hub with the address in the QH/siTD.
In silicon RTL, this entry only affects QH and siTD, and the hub.addr at
both QH and siTD are 0 in ehci core for chipidea (with hcd->has_tt = 1).
So, for QH, if the "usage_tt" flag at RTL is 0, set CI_HDRC_SET_NON_ZERO_TTHA
will not affect QH (with non-hs device); for siTD, set this flag
will change remaining space requirement for the last transaction from 1023
bytes to 188 bytes, it can increase the number of transactions within one
frame, ehci periodic schedule code will not queue the packet if the frame space
is full, so it is safe to set this flag for siTD.
With this flag, it can fix the problem Alan Stern reported below:
http://www.spinics.net/lists/linux-usb/msg123125.html
And may fix Michael Tessier's problem too.
http://www.spinics.net/lists/linux-usb/msg118679.html
CC: stern@rowland.harvard.edu
CC: michael.tessier@axiontech.ca
Signed-off-by: Peter Chen <peter.chen@freescale.com>
2015-06-18 05:51:53 +02:00
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[OP_TTCTRL] = 0x1CU,
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2015-03-17 10:32:45 +01:00
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[OP_BURSTSIZE] = 0x20U,
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2016-12-28 23:56:55 +01:00
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[OP_ULPI_VIEWPORT] = 0x30U,
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2014-01-06 03:10:39 +01:00
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[OP_PORTSC] = 0x44U,
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[OP_DEVLC] = 0x84U,
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[OP_OTGSC] = 0xC4U,
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[OP_USBMODE] = 0xC8U,
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[OP_ENDPTSETUPSTAT] = 0xD8U,
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[OP_ENDPTPRIME] = 0xDCU,
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[OP_ENDPTFLUSH] = 0xE0U,
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[OP_ENDPTSTAT] = 0xE4U,
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[OP_ENDPTCOMPLETE] = 0xE8U,
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[OP_ENDPTCTRL] = 0xECU,
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2012-05-11 16:25:46 +02:00
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};
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2015-06-27 06:34:48 +02:00
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static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
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2012-05-11 16:25:46 +02:00
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{
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int i;
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for (i = 0; i < OP_ENDPTCTRL; i++)
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2012-05-11 16:25:47 +02:00
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ci->hw_bank.regmap[i] =
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(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
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2012-05-11 16:25:46 +02:00
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(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
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for (; i <= OP_LAST; i++)
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2012-05-11 16:25:47 +02:00
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ci->hw_bank.regmap[i] = ci->hw_bank.op +
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2012-05-11 16:25:46 +02:00
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4 * (i - OP_ENDPTCTRL) +
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(is_lpm
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? ci_regs_lpm[OP_ENDPTCTRL]
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: ci_regs_nolpm[OP_ENDPTCTRL]);
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}
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2015-02-11 05:44:55 +01:00
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static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
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{
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int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
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enum ci_revision rev = CI_REVISION_UNKNOWN;
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if (ver == 0x2) {
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rev = hw_read_id_reg(ci, ID_ID, REVISION)
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>> __ffs(REVISION);
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rev += CI_REVISION_20;
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} else if (ver == 0x0) {
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rev = CI_REVISION_1X;
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}
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return rev;
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}
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2014-04-23 09:56:39 +02:00
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/**
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* hw_read_intr_enable: returns interrupt enable register
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*
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2014-09-22 02:14:17 +02:00
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* @ci: the controller
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*
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2014-04-23 09:56:39 +02:00
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* This function returns register data
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*/
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u32 hw_read_intr_enable(struct ci_hdrc *ci)
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{
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return hw_read(ci, OP_USBINTR, ~0);
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}
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/**
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* hw_read_intr_status: returns interrupt status register
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*
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2014-09-22 02:14:17 +02:00
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* @ci: the controller
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*
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2014-04-23 09:56:39 +02:00
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* This function returns register data
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*/
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u32 hw_read_intr_status(struct ci_hdrc *ci)
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{
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return hw_read(ci, OP_USBSTS, ~0);
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}
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2012-05-11 16:25:46 +02:00
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/**
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* hw_port_test_set: writes port test mode (execute without interruption)
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* @mode: new value
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*
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* This function returns an error code
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*/
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2013-06-24 13:46:36 +02:00
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int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
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2012-05-11 16:25:46 +02:00
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{
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const u8 TEST_MODE_MAX = 7;
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if (mode > TEST_MODE_MAX)
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return -EINVAL;
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2013-03-30 11:53:55 +01:00
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hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
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2012-05-11 16:25:46 +02:00
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return 0;
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}
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/**
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|
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* hw_port_test_get: reads port test mode value
|
|
|
|
*
|
2014-09-22 02:14:17 +02:00
|
|
|
* @ci: the controller
|
|
|
|
*
|
2012-05-11 16:25:46 +02:00
|
|
|
* This function returns port test mode value
|
|
|
|
*/
|
2013-06-24 13:46:36 +02:00
|
|
|
u8 hw_port_test_get(struct ci_hdrc *ci)
|
2012-05-11 16:25:46 +02:00
|
|
|
{
|
2013-03-30 11:53:55 +01:00
|
|
|
return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
|
2012-05-11 16:25:46 +02:00
|
|
|
}
|
|
|
|
|
2014-11-26 06:44:28 +01:00
|
|
|
static void hw_wait_phy_stable(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* The phy needs some delay to output the stable status from low
|
|
|
|
* power mode. And for OTGSC, the status inputs are debounced
|
|
|
|
* using a 1 ms time constant, so, delay 2ms for controller to get
|
|
|
|
* the stable status, like vbus and id when the phy leaves low power.
|
|
|
|
*/
|
|
|
|
usleep_range(2000, 2500);
|
|
|
|
}
|
|
|
|
|
2013-09-24 06:47:55 +02:00
|
|
|
/* The PHY enters/leaves low power mode */
|
|
|
|
static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
|
|
|
|
{
|
|
|
|
enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
|
|
|
|
bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
|
|
|
|
|
2014-11-26 06:44:27 +01:00
|
|
|
if (enable && !lpm)
|
2013-09-24 06:47:55 +02:00
|
|
|
hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
|
|
|
|
PORTSC_PHCD(ci->hw_bank.lpm));
|
2014-11-26 06:44:27 +01:00
|
|
|
else if (!enable && lpm)
|
2013-09-24 06:47:55 +02:00
|
|
|
hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
|
|
|
|
0);
|
|
|
|
}
|
|
|
|
|
2013-06-24 13:46:36 +02:00
|
|
|
static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
|
2012-05-11 16:25:46 +02:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/* bank is a module variable */
|
2012-05-11 16:25:47 +02:00
|
|
|
ci->hw_bank.abs = base;
|
2012-05-11 16:25:46 +02:00
|
|
|
|
2012-05-11 16:25:47 +02:00
|
|
|
ci->hw_bank.cap = ci->hw_bank.abs;
|
2012-06-29 11:48:53 +02:00
|
|
|
ci->hw_bank.cap += ci->platdata->capoffset;
|
2013-03-30 11:54:03 +01:00
|
|
|
ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
|
2012-05-11 16:25:46 +02:00
|
|
|
|
2012-05-11 16:25:47 +02:00
|
|
|
hw_alloc_regmap(ci, false);
|
|
|
|
reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
|
2013-03-30 11:53:55 +01:00
|
|
|
__ffs(HCCPARAMS_LEN);
|
2012-05-11 16:25:47 +02:00
|
|
|
ci->hw_bank.lpm = reg;
|
2013-12-06 09:35:12 +01:00
|
|
|
if (reg)
|
|
|
|
hw_alloc_regmap(ci, !!reg);
|
2012-05-11 16:25:47 +02:00
|
|
|
ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
|
|
|
|
ci->hw_bank.size += OP_LAST;
|
|
|
|
ci->hw_bank.size /= sizeof(u32);
|
2012-05-11 16:25:46 +02:00
|
|
|
|
2012-05-11 16:25:47 +02:00
|
|
|
reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
|
2013-03-30 11:53:55 +01:00
|
|
|
__ffs(DCCPARAMS_DEN);
|
2012-05-11 16:25:47 +02:00
|
|
|
ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
|
2012-05-11 16:25:46 +02:00
|
|
|
|
2012-05-15 15:58:18 +02:00
|
|
|
if (ci->hw_ep_max > ENDPT_MAX)
|
2012-05-11 16:25:46 +02:00
|
|
|
return -ENODEV;
|
|
|
|
|
2013-09-24 06:47:55 +02:00
|
|
|
ci_hdrc_enter_lpm(ci, false);
|
|
|
|
|
2013-08-14 11:44:09 +02:00
|
|
|
/* Disable all interrupts bits */
|
|
|
|
hw_write(ci, OP_USBINTR, 0xffffffff, 0);
|
|
|
|
|
|
|
|
/* Clear all interrupts status bits*/
|
|
|
|
hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
|
|
|
|
|
2015-02-11 05:44:55 +01:00
|
|
|
ci->rev = ci_get_revision(ci);
|
|
|
|
|
|
|
|
dev_dbg(ci->dev,
|
|
|
|
"ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
|
|
|
|
ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
|
2012-05-11 16:25:46 +02:00
|
|
|
|
|
|
|
/* setup lock mode ? */
|
|
|
|
|
|
|
|
/* ENDPTSETUPSTAT is '0' by default */
|
|
|
|
|
|
|
|
/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-12-28 23:56:55 +01:00
|
|
|
void hw_phymode_configure(struct ci_hdrc *ci)
|
2013-06-13 16:59:56 +02:00
|
|
|
{
|
2014-01-10 06:51:29 +01:00
|
|
|
u32 portsc, lpm, sts = 0;
|
2013-06-13 16:59:56 +02:00
|
|
|
|
|
|
|
switch (ci->platdata->phy_mode) {
|
|
|
|
case USBPHY_INTERFACE_MODE_UTMI:
|
|
|
|
portsc = PORTSC_PTS(PTS_UTMI);
|
|
|
|
lpm = DEVLC_PTS(PTS_UTMI);
|
|
|
|
break;
|
|
|
|
case USBPHY_INTERFACE_MODE_UTMIW:
|
|
|
|
portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
|
|
|
|
lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
|
|
|
|
break;
|
|
|
|
case USBPHY_INTERFACE_MODE_ULPI:
|
|
|
|
portsc = PORTSC_PTS(PTS_ULPI);
|
|
|
|
lpm = DEVLC_PTS(PTS_ULPI);
|
|
|
|
break;
|
|
|
|
case USBPHY_INTERFACE_MODE_SERIAL:
|
|
|
|
portsc = PORTSC_PTS(PTS_SERIAL);
|
|
|
|
lpm = DEVLC_PTS(PTS_SERIAL);
|
|
|
|
sts = 1;
|
|
|
|
break;
|
|
|
|
case USBPHY_INTERFACE_MODE_HSIC:
|
|
|
|
portsc = PORTSC_PTS(PTS_HSIC);
|
|
|
|
lpm = DEVLC_PTS(PTS_HSIC);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ci->hw_bank.lpm) {
|
|
|
|
hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
|
2014-01-10 06:51:29 +01:00
|
|
|
if (sts)
|
|
|
|
hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
|
2013-06-13 16:59:56 +02:00
|
|
|
} else {
|
|
|
|
hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
|
2014-01-10 06:51:29 +01:00
|
|
|
if (sts)
|
|
|
|
hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
|
2013-06-13 16:59:56 +02:00
|
|
|
}
|
|
|
|
}
|
2016-12-28 23:57:06 +01:00
|
|
|
EXPORT_SYMBOL_GPL(hw_phymode_configure);
|
2013-06-13 16:59:56 +02:00
|
|
|
|
2014-10-30 18:41:19 +01:00
|
|
|
/**
|
|
|
|
* _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
|
|
|
|
* interfaces
|
|
|
|
* @ci: the controller
|
|
|
|
*
|
|
|
|
* This function returns an error code if the phy failed to init
|
|
|
|
*/
|
|
|
|
static int _ci_usb_phy_init(struct ci_hdrc *ci)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (ci->phy) {
|
|
|
|
ret = phy_init(ci->phy);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = phy_power_on(ci->phy);
|
|
|
|
if (ret) {
|
|
|
|
phy_exit(ci->phy);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = usb_phy_init(ci->usb_phy);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
|
|
|
|
* interfaces
|
|
|
|
* @ci: the controller
|
|
|
|
*/
|
|
|
|
static void ci_usb_phy_exit(struct ci_hdrc *ci)
|
|
|
|
{
|
2016-12-28 23:56:52 +01:00
|
|
|
if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
|
|
|
|
return;
|
|
|
|
|
2014-10-30 18:41:19 +01:00
|
|
|
if (ci->phy) {
|
|
|
|
phy_power_off(ci->phy);
|
|
|
|
phy_exit(ci->phy);
|
|
|
|
} else {
|
|
|
|
usb_phy_shutdown(ci->usb_phy);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-23 09:56:37 +02:00
|
|
|
/**
|
|
|
|
* ci_usb_phy_init: initialize phy according to different phy type
|
|
|
|
* @ci: the controller
|
2014-09-22 02:14:17 +02:00
|
|
|
*
|
2014-04-23 09:56:37 +02:00
|
|
|
* This function returns an error code if usb_phy_init has failed
|
|
|
|
*/
|
|
|
|
static int ci_usb_phy_init(struct ci_hdrc *ci)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2016-12-28 23:56:52 +01:00
|
|
|
if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
|
|
|
|
return 0;
|
|
|
|
|
2014-04-23 09:56:37 +02:00
|
|
|
switch (ci->platdata->phy_mode) {
|
|
|
|
case USBPHY_INTERFACE_MODE_UTMI:
|
|
|
|
case USBPHY_INTERFACE_MODE_UTMIW:
|
|
|
|
case USBPHY_INTERFACE_MODE_HSIC:
|
2014-10-30 18:41:19 +01:00
|
|
|
ret = _ci_usb_phy_init(ci);
|
2014-11-26 06:44:28 +01:00
|
|
|
if (!ret)
|
|
|
|
hw_wait_phy_stable();
|
|
|
|
else
|
2014-04-23 09:56:37 +02:00
|
|
|
return ret;
|
|
|
|
hw_phymode_configure(ci);
|
|
|
|
break;
|
|
|
|
case USBPHY_INTERFACE_MODE_ULPI:
|
|
|
|
case USBPHY_INTERFACE_MODE_SERIAL:
|
|
|
|
hw_phymode_configure(ci);
|
2014-10-30 18:41:19 +01:00
|
|
|
ret = _ci_usb_phy_init(ci);
|
2014-04-23 09:56:37 +02:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
break;
|
|
|
|
default:
|
2014-10-30 18:41:19 +01:00
|
|
|
ret = _ci_usb_phy_init(ci);
|
2014-11-26 06:44:28 +01:00
|
|
|
if (!ret)
|
|
|
|
hw_wait_phy_stable();
|
2014-04-23 09:56:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-03-17 03:40:50 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* ci_platform_configure: do controller configure
|
|
|
|
* @ci: the controller
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
void ci_platform_configure(struct ci_hdrc *ci)
|
|
|
|
{
|
usb: chipidea: define stream mode disable for both roles
The system bus and chipidea IP have different limitations for
both host and device mode.
For example, with below errata, we need to enable SDIS(Stream Disable
Mode) at host mode. But we don't want it for device mode at the
same system.
TAR 9000378958
Title: Non-Double Word Aligned Buffer Address Sometimes Causes Host to
Hang on OUT Retry
Impacted Configuration: Host mode, all transfer types
Description:
The host core operating in streaming mode may under run while sending
the data packet of an OUT transaction. This under run can occur if
there are unexpected system delays in fetching the remaining packet
data from memory. The host forces a bad CRC on the packet, the device
detects the error and discards the packet. The host then retries a Bulk,
Interrupt, or Control transfer if an under run occurs according to the
USB specification. During simulations, it was found that the host does
not issue the retry of the failed bulk OUT. It does not issue any other
transactions except SOF packets that have incorrect frame numbers.
The second failure mode occurs if the under run occurs on an ISO OUT
transaction and the next ISO transaction is a zero byte packet. The host
does not issue any transactions (including SOFs). The device detects a
Suspend condition, reverts to full speed, and waits for resume signaling.
A third failure mode occurs when the host under runs on an ISO OUT and
the next ISO in the schedule is an ISO OUT with two max packets of 1024
bytes each. The host should issue MDATA for the first OUT followed by
DATA1 for the second. However, it drops the MDATA transaction, and
issues the DATA1 transaction.
The system impact of this bug is the same regardless of the failure mode
observed. The host core hangs, the ehci_ctrl state machine waits for the
protocol engine to send the completion status for the corrupted
transaction, which never occurs. No indication is sent to the host
controller driver, no register bits change and no interrupts occur.
Eventually the requesting application times out.
Detailed internal behavior:
The EHCI control state machine (ehci_ctrl) in the DMA block is responsible
for parsing the schedules and initiating all transactions. The ehci_ctrl
state machine passes the transaction details to the protocol block by
writing the transaction information in to the TxFIFO. It then asserts
the pe_hst_run_pkt signal to inform the host protocol state machine
(pe_hst_state) that there is a packet in the TxFIFO.
A tag of 0x0 indicates a start of packet with the data providing the
following information:
35:32 Tag
31:30 Reserved
29:23 Endpoint (lowest 4 bits)
22:16 Address
15:10 Reserved
9:8 Endpoint speed
7:6 Endpoint type
5:6 Data Toggle
3:0 PID
The pe_hst_state reads the packet information and constructs the packet
and issues it to the PHY interface.
The ehci_ctrl state machine writes the start transaction information in
to the TxFIFO as 0x03002910c for the OUT packet that had the under run
error. However, it writes 0xC3002910C for the retry of the Out
transaction, which is incorrect.
The pe_hst_state enters a bus timeout state after sending the bad CRC
for the packet that under ran. It then purges any data that was back
filled in to the TxFIFO for the packet that under ran. The pe_hst_state
machine stops purging the TxFIFO when it is empty or if it reads a
location that has a tag of 0x0, indicating a start of packet command.
The pe_hst_state reads 0xC3002910C and discards it as it does not decode
to a start of packet command. It continues to purge the OUT data that
has been pre-buffered for the OUT retry . The pe_hst_state detects the
hst_packet_run signal and attempts to read the PID and address
information from the TxFIFO. This location has packet data and so does
not decode to a valid PID and so falls through to the PE_HST_SOF_LOAD
state where the frame_num_counter is updated. The frame_num_counter
is updated with the data in the TxFIFO. In this case, the data is
incorrect as the ehci_ctrl state machine did not initiate the load.
The hst_pe_state machine detects the SOF request signal and sends an
SOF with the bad frame number. Meanwhile, the ehci_ctrl state machine
waits indefinitely in the run_pkt state waiting for the completion
status from pe_hst_state machine, which will never happen.
The ISO failure case is similar except that there is no retry for ISO.
The ehci_ctrl state machine moves to the next transfer in the periodic
schedule. If the under run occurs on the last entry of the periodic
list then it moves to the Async schedule.
In the case of ISO OUT simulations, the next ISO is a zero byte OUT
and again the start of packet command gets corrupted. The TxFIFO is
empty when the hst_pe_state attempts to read the Address and PID
information as the transaction is a zero byte packet. This results
in the hst_pe_state machine staying in the GET_PID state, which means
that it does not issue any transactions (including SOFs). The device
detects a Suspend condition and reverts to full speed mode and waits
for a Resume or Reset signal.
The EHCI specification allows a Non-DoubleWord (32 bits) offset to
be used as a current offset for Buffer Pointer Page 0 of the qTD.
In Non-DoubleWord aligned cases, the core reads the packet data
from the AHB memory, performs the alignment operation before writing
it in to the TxFIFO as a 32 bit data word. An End Of Packet tag (EOP)
is written to the TxFIFO after all the packet data has been written
in to the TxFIFO. The alignment function is reset to Idle by the EOP
tag. The corruption of the start of packet command arises because the
packet buffer for the OUT transaction that under ran is not aligned
to a DoubleWord, and hence no EOP tag is written to the TxFIFO. The
alignment function is still active when the start packet information
is written in to the TxFIFO for the retry of the bulk packet or for
the next transaction in the case of an under run on an ISO. This
results in the corruption of the start tag and the transaction
information.
Click for waveform showing the command 0x 0000300291 being written in
to the TX FIFO for the Out that under ran.
Click for waveform showing the command 0xC3002910C written to the
TxFIFO instead of 0x 0000300291
Versions affected: Versions 2.10a and previous versions
How discovered: Customer simulation
Workaround:
1- The EHCI specification allows a non-DoubleWord offset to be used
as a current offset for Buffer Pointer Page 0 of the qTD. However,
if a DoubleWord offset is used then this issue does not arise.
2- Use non streaming mode to eliminate under runs.
Resolution:
The fix involves changes to the traffic state machine in the
vusb_hs_dma_traf block. The ehci_ctrl state machine updates the context
information by encoding the transaction results on the
hst_op_context_update signals at the end of a transaction. The signal
hst_op_context_update is added to the traffic state machine, and the
tx_fifo_under_ran_r signal is generated if the transaction results in
an under run error. Click for waveform
The traffic state machine then traverses to the do_eop states if the
tx_fifo_under_ran error is asserted. Thus an EOP tag is written in to
the TxFIFO as shown in this waveform .
The EOP tag resets the align state machine to the Idle state ensuring
that the next command written by the echi_ctrl state machine does not
get corrupted.
File(s) modified:
RTL code fixed: …..
Method of reproducing: This failure cannot be reproduced in the current
test bench.
Date Found: March 2010
Date Fixed: June 2010
Update information:
Added the RTL code fix
Signed-off-by: Peter Chen <peter.chen@freescale.com>
2014-10-30 02:15:15 +01:00
|
|
|
bool is_device_mode, is_host_mode;
|
|
|
|
|
|
|
|
is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
|
|
|
|
is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
|
|
|
|
|
2017-01-25 23:32:43 +01:00
|
|
|
if (is_device_mode) {
|
|
|
|
phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
|
usb: chipidea: define stream mode disable for both roles
The system bus and chipidea IP have different limitations for
both host and device mode.
For example, with below errata, we need to enable SDIS(Stream Disable
Mode) at host mode. But we don't want it for device mode at the
same system.
TAR 9000378958
Title: Non-Double Word Aligned Buffer Address Sometimes Causes Host to
Hang on OUT Retry
Impacted Configuration: Host mode, all transfer types
Description:
The host core operating in streaming mode may under run while sending
the data packet of an OUT transaction. This under run can occur if
there are unexpected system delays in fetching the remaining packet
data from memory. The host forces a bad CRC on the packet, the device
detects the error and discards the packet. The host then retries a Bulk,
Interrupt, or Control transfer if an under run occurs according to the
USB specification. During simulations, it was found that the host does
not issue the retry of the failed bulk OUT. It does not issue any other
transactions except SOF packets that have incorrect frame numbers.
The second failure mode occurs if the under run occurs on an ISO OUT
transaction and the next ISO transaction is a zero byte packet. The host
does not issue any transactions (including SOFs). The device detects a
Suspend condition, reverts to full speed, and waits for resume signaling.
A third failure mode occurs when the host under runs on an ISO OUT and
the next ISO in the schedule is an ISO OUT with two max packets of 1024
bytes each. The host should issue MDATA for the first OUT followed by
DATA1 for the second. However, it drops the MDATA transaction, and
issues the DATA1 transaction.
The system impact of this bug is the same regardless of the failure mode
observed. The host core hangs, the ehci_ctrl state machine waits for the
protocol engine to send the completion status for the corrupted
transaction, which never occurs. No indication is sent to the host
controller driver, no register bits change and no interrupts occur.
Eventually the requesting application times out.
Detailed internal behavior:
The EHCI control state machine (ehci_ctrl) in the DMA block is responsible
for parsing the schedules and initiating all transactions. The ehci_ctrl
state machine passes the transaction details to the protocol block by
writing the transaction information in to the TxFIFO. It then asserts
the pe_hst_run_pkt signal to inform the host protocol state machine
(pe_hst_state) that there is a packet in the TxFIFO.
A tag of 0x0 indicates a start of packet with the data providing the
following information:
35:32 Tag
31:30 Reserved
29:23 Endpoint (lowest 4 bits)
22:16 Address
15:10 Reserved
9:8 Endpoint speed
7:6 Endpoint type
5:6 Data Toggle
3:0 PID
The pe_hst_state reads the packet information and constructs the packet
and issues it to the PHY interface.
The ehci_ctrl state machine writes the start transaction information in
to the TxFIFO as 0x03002910c for the OUT packet that had the under run
error. However, it writes 0xC3002910C for the retry of the Out
transaction, which is incorrect.
The pe_hst_state enters a bus timeout state after sending the bad CRC
for the packet that under ran. It then purges any data that was back
filled in to the TxFIFO for the packet that under ran. The pe_hst_state
machine stops purging the TxFIFO when it is empty or if it reads a
location that has a tag of 0x0, indicating a start of packet command.
The pe_hst_state reads 0xC3002910C and discards it as it does not decode
to a start of packet command. It continues to purge the OUT data that
has been pre-buffered for the OUT retry . The pe_hst_state detects the
hst_packet_run signal and attempts to read the PID and address
information from the TxFIFO. This location has packet data and so does
not decode to a valid PID and so falls through to the PE_HST_SOF_LOAD
state where the frame_num_counter is updated. The frame_num_counter
is updated with the data in the TxFIFO. In this case, the data is
incorrect as the ehci_ctrl state machine did not initiate the load.
The hst_pe_state machine detects the SOF request signal and sends an
SOF with the bad frame number. Meanwhile, the ehci_ctrl state machine
waits indefinitely in the run_pkt state waiting for the completion
status from pe_hst_state machine, which will never happen.
The ISO failure case is similar except that there is no retry for ISO.
The ehci_ctrl state machine moves to the next transfer in the periodic
schedule. If the under run occurs on the last entry of the periodic
list then it moves to the Async schedule.
In the case of ISO OUT simulations, the next ISO is a zero byte OUT
and again the start of packet command gets corrupted. The TxFIFO is
empty when the hst_pe_state attempts to read the Address and PID
information as the transaction is a zero byte packet. This results
in the hst_pe_state machine staying in the GET_PID state, which means
that it does not issue any transactions (including SOFs). The device
detects a Suspend condition and reverts to full speed mode and waits
for a Resume or Reset signal.
The EHCI specification allows a Non-DoubleWord (32 bits) offset to
be used as a current offset for Buffer Pointer Page 0 of the qTD.
In Non-DoubleWord aligned cases, the core reads the packet data
from the AHB memory, performs the alignment operation before writing
it in to the TxFIFO as a 32 bit data word. An End Of Packet tag (EOP)
is written to the TxFIFO after all the packet data has been written
in to the TxFIFO. The alignment function is reset to Idle by the EOP
tag. The corruption of the start of packet command arises because the
packet buffer for the OUT transaction that under ran is not aligned
to a DoubleWord, and hence no EOP tag is written to the TxFIFO. The
alignment function is still active when the start packet information
is written in to the TxFIFO for the retry of the bulk packet or for
the next transaction in the case of an under run on an ISO. This
results in the corruption of the start tag and the transaction
information.
Click for waveform showing the command 0x 0000300291 being written in
to the TX FIFO for the Out that under ran.
Click for waveform showing the command 0xC3002910C written to the
TxFIFO instead of 0x 0000300291
Versions affected: Versions 2.10a and previous versions
How discovered: Customer simulation
Workaround:
1- The EHCI specification allows a non-DoubleWord offset to be used
as a current offset for Buffer Pointer Page 0 of the qTD. However,
if a DoubleWord offset is used then this issue does not arise.
2- Use non streaming mode to eliminate under runs.
Resolution:
The fix involves changes to the traffic state machine in the
vusb_hs_dma_traf block. The ehci_ctrl state machine updates the context
information by encoding the transaction results on the
hst_op_context_update signals at the end of a transaction. The signal
hst_op_context_update is added to the traffic state machine, and the
tx_fifo_under_ran_r signal is generated if the transaction results in
an under run error. Click for waveform
The traffic state machine then traverses to the do_eop states if the
tx_fifo_under_ran error is asserted. Thus an EOP tag is written in to
the TxFIFO as shown in this waveform .
The EOP tag resets the align state machine to the Idle state ensuring
that the next command written by the echi_ctrl state machine does not
get corrupted.
File(s) modified:
RTL code fixed: …..
Method of reproducing: This failure cannot be reproduced in the current
test bench.
Date Found: March 2010
Date Fixed: June 2010
Update information:
Added the RTL code fix
Signed-off-by: Peter Chen <peter.chen@freescale.com>
2014-10-30 02:15:15 +01:00
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2017-01-25 23:32:43 +01:00
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if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
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hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
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USBMODE_CI_SDIS);
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}
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if (is_host_mode) {
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phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
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if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
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hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
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USBMODE_CI_SDIS);
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}
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2015-03-17 03:40:50 +01:00
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if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
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if (ci->hw_bank.lpm)
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hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
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else
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hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
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}
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if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
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hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
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usb: chipidea: introduce ITC tuning interface
ITC (Interrupt Threshold Control) is used to set the maximum rate at which
the host/device controller will issue interrupts. The default value is 8 (1ms)
for it. EHCI core will modify it to 1, but device mode keeps it as default
value.
In some use cases like Android ADB, it only has one usb request for each
direction, and maximum payload data is only 4KB, so the speed is 4MB/s
at most, it needs controller to trigger interrupt as fast as possible
to increase the speed. The USB performance will be better if the interrupt
can be triggered faster.
Reduce ITC value is benefit for USB performance, but the interrupt number
is increased at the same time, it may increase cpu utilization too.
Most of use case cares about performance, but some may care about
cpu utilization, so, we leave a platform interface for user.
We set ITC as 1 (1 micro-frame) as default value which is aligned
with ehci core default value.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
2014-09-22 10:45:39 +02:00
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hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
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2015-03-17 07:21:00 +01:00
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if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
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hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
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ci->platdata->ahb_burst_config);
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2015-03-17 10:32:45 +01:00
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/* override burst size, take effect only when ahb_burst_config is 0 */
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if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
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if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
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hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
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ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
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if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
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hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
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ci->platdata->rx_burst_size);
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}
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2015-03-17 03:40:50 +01:00
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}
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2012-05-11 16:25:46 +02:00
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/**
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2014-11-26 06:44:32 +01:00
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* hw_controller_reset: do controller reset
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2012-05-11 16:25:46 +02:00
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* @ci: the controller
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*
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* This function returns an error code
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*/
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2014-11-26 06:44:32 +01:00
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static int hw_controller_reset(struct ci_hdrc *ci)
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{
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int count = 0;
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hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
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while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
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udelay(10);
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if (count++ > 1000)
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return -ETIMEDOUT;
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}
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return 0;
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}
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/**
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* hw_device_reset: resets chip (execute without interruption)
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* @ci: the controller
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*
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* This function returns an error code
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*/
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2014-11-26 06:44:33 +01:00
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int hw_device_reset(struct ci_hdrc *ci)
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2012-05-11 16:25:46 +02:00
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{
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2014-11-26 06:44:32 +01:00
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int ret;
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2012-05-11 16:25:46 +02:00
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/* should flush & stop before reset */
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hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
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hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
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2014-11-26 06:44:32 +01:00
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ret = hw_controller_reset(ci);
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if (ret) {
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dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
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return ret;
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}
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2012-05-11 16:25:46 +02:00
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2016-12-28 23:57:06 +01:00
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if (ci->platdata->notify_event) {
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ret = ci->platdata->notify_event(ci,
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2013-06-24 13:46:36 +02:00
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CI_HDRC_CONTROLLER_RESET_EVENT);
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2016-12-28 23:57:06 +01:00
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if (ret)
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return ret;
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}
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2012-05-11 16:25:46 +02:00
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/* USBMODE should be configured step by step */
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hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
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2014-11-26 06:44:33 +01:00
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hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
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2012-05-11 16:25:46 +02:00
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/* HW >= 2.3 */
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hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
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2014-11-26 06:44:33 +01:00
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if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
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pr_err("cannot enter in %s device mode", ci_role(ci)->name);
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2012-05-11 16:25:46 +02:00
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pr_err("lpm = %i", ci->hw_bank.lpm);
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return -ENODEV;
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}
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2015-03-17 03:40:50 +01:00
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ci_platform_configure(ci);
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2012-05-11 16:25:46 +02:00
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return 0;
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}
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2012-05-11 16:25:47 +02:00
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static irqreturn_t ci_irq(int irq, void *data)
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{
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2013-06-24 13:46:36 +02:00
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struct ci_hdrc *ci = data;
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2012-05-11 16:25:47 +02:00
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irqreturn_t ret = IRQ_NONE;
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2012-09-12 13:58:11 +02:00
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u32 otgsc = 0;
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2012-05-11 16:25:47 +02:00
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2015-02-11 05:44:45 +01:00
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if (ci->in_lpm) {
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disable_irq_nosync(irq);
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ci->wakeup_int = true;
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pm_runtime_get(ci->dev);
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return IRQ_HANDLED;
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}
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2014-04-23 09:56:50 +02:00
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if (ci->is_otg) {
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2014-04-23 09:56:38 +02:00
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otgsc = hw_read_otgsc(ci, ~0);
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2014-04-23 09:56:50 +02:00
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if (ci_otg_is_fsm_mode(ci)) {
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ret = ci_otg_fsm_irq(ci);
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if (ret == IRQ_HANDLED)
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return ret;
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}
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}
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2012-05-11 16:25:47 +02:00
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2013-08-14 11:44:11 +02:00
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/*
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* Handle id change interrupt, it indicates device/host function
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* switch.
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*/
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if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
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ci->id_event = true;
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2014-04-23 09:56:38 +02:00
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/* Clear ID change irq status */
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hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
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2014-05-23 02:12:49 +02:00
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ci_otg_queue_work(ci);
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2013-08-14 11:44:11 +02:00
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return IRQ_HANDLED;
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}
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2012-09-12 13:58:11 +02:00
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2013-08-14 11:44:11 +02:00
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/*
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* Handle vbus change interrupt, it indicates device connection
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* and disconnection events.
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*/
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if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
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ci->b_sess_valid_event = true;
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2014-04-23 09:56:38 +02:00
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/* Clear BSV irq */
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hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
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2014-05-23 02:12:49 +02:00
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ci_otg_queue_work(ci);
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2013-08-14 11:44:11 +02:00
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return IRQ_HANDLED;
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2012-05-11 16:25:47 +02:00
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}
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2013-08-14 11:44:11 +02:00
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/* Handle device/host interrupt */
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if (ci->role != CI_ROLE_END)
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ret = ci_role(ci)->irq(ci);
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2012-09-12 13:58:11 +02:00
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return ret;
|
2012-05-11 16:25:47 +02:00
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}
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2017-01-20 08:11:55 +01:00
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static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
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void *ptr)
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2015-09-07 13:45:25 +02:00
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{
|
2017-01-20 08:11:55 +01:00
|
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struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
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struct ci_hdrc *ci = cbl->ci;
|
2015-09-07 13:45:25 +02:00
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2017-01-20 08:11:55 +01:00
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cbl->connected = event;
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cbl->changed = true;
|
2015-09-07 13:45:25 +02:00
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ci_irq(ci->irq, ci);
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return NOTIFY_DONE;
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}
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2013-08-14 11:44:03 +02:00
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static int ci_get_platdata(struct device *dev,
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struct ci_hdrc_platform_data *platdata)
|
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{
|
2015-09-07 13:45:25 +02:00
|
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struct extcon_dev *ext_vbus, *ext_id;
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struct ci_hdrc_cable *cable;
|
2015-07-09 09:18:45 +02:00
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int ret;
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2013-09-17 06:37:22 +02:00
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if (!platdata->phy_mode)
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platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
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if (!platdata->dr_mode)
|
2015-09-21 10:14:34 +02:00
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platdata->dr_mode = usb_get_dr_mode(dev);
|
2013-09-17 06:37:22 +02:00
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if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
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platdata->dr_mode = USB_DR_MODE_OTG;
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2013-10-30 02:19:29 +01:00
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if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
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/* Get the vbus regulator */
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platdata->reg_vbus = devm_regulator_get(dev, "vbus");
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if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
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return -EPROBE_DEFER;
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} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
|
2014-11-26 06:44:38 +01:00
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/* no vbus regulator is needed */
|
2013-10-30 02:19:29 +01:00
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platdata->reg_vbus = NULL;
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} else if (IS_ERR(platdata->reg_vbus)) {
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dev_err(dev, "Getting regulator error: %ld\n",
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PTR_ERR(platdata->reg_vbus));
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return PTR_ERR(platdata->reg_vbus);
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}
|
2014-08-19 03:51:56 +02:00
|
|
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/* Get TPL support */
|
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|
|
if (!platdata->tpl_support)
|
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|
platdata->tpl_support =
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of_usb_host_tpl_support(dev->of_node);
|
2013-10-30 02:19:29 +01:00
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}
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2015-07-09 09:18:45 +02:00
|
|
|
if (platdata->dr_mode == USB_DR_MODE_OTG) {
|
|
|
|
/* We can support HNP and SRP of OTG 2.0 */
|
|
|
|
platdata->ci_otg_caps.otg_rev = 0x0200;
|
|
|
|
platdata->ci_otg_caps.hnp_support = true;
|
|
|
|
platdata->ci_otg_caps.srp_support = true;
|
|
|
|
|
|
|
|
/* Update otg capabilities by DT properties */
|
|
|
|
ret = of_usb_update_otg_caps(dev->of_node,
|
|
|
|
&platdata->ci_otg_caps);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-09-21 10:14:32 +02:00
|
|
|
if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
|
2014-02-19 06:41:43 +01:00
|
|
|
platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
|
|
|
|
|
2015-11-18 05:10:12 +01:00
|
|
|
of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
|
2015-09-09 03:18:14 +02:00
|
|
|
&platdata->phy_clkgate_delay_us);
|
|
|
|
|
usb: chipidea: introduce ITC tuning interface
ITC (Interrupt Threshold Control) is used to set the maximum rate at which
the host/device controller will issue interrupts. The default value is 8 (1ms)
for it. EHCI core will modify it to 1, but device mode keeps it as default
value.
In some use cases like Android ADB, it only has one usb request for each
direction, and maximum payload data is only 4KB, so the speed is 4MB/s
at most, it needs controller to trigger interrupt as fast as possible
to increase the speed. The USB performance will be better if the interrupt
can be triggered faster.
Reduce ITC value is benefit for USB performance, but the interrupt number
is increased at the same time, it may increase cpu utilization too.
Most of use case cares about performance, but some may care about
cpu utilization, so, we leave a platform interface for user.
We set ITC as 1 (1 micro-frame) as default value which is aligned
with ehci core default value.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
2014-09-22 10:45:39 +02:00
|
|
|
platdata->itc_setting = 1;
|
|
|
|
|
2015-11-18 05:10:12 +01:00
|
|
|
of_property_read_u32(dev->of_node, "itc-setting",
|
|
|
|
&platdata->itc_setting);
|
|
|
|
|
|
|
|
ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
|
|
|
|
&platdata->ahb_burst_config);
|
|
|
|
if (!ret) {
|
2015-03-17 07:21:00 +01:00
|
|
|
platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
|
2015-11-18 05:10:12 +01:00
|
|
|
} else if (ret != -EINVAL) {
|
|
|
|
dev_err(dev, "failed to get ahb-burst-config\n");
|
|
|
|
return ret;
|
2015-03-17 07:21:00 +01:00
|
|
|
}
|
|
|
|
|
2015-11-18 05:10:12 +01:00
|
|
|
ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
|
|
|
|
&platdata->tx_burst_size);
|
|
|
|
if (!ret) {
|
2015-03-17 10:32:45 +01:00
|
|
|
platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
|
2015-11-18 05:10:12 +01:00
|
|
|
} else if (ret != -EINVAL) {
|
|
|
|
dev_err(dev, "failed to get tx-burst-size-dword\n");
|
|
|
|
return ret;
|
2015-03-17 10:32:45 +01:00
|
|
|
}
|
|
|
|
|
2015-11-18 05:10:12 +01:00
|
|
|
ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
|
|
|
|
&platdata->rx_burst_size);
|
|
|
|
if (!ret) {
|
2015-03-17 10:32:45 +01:00
|
|
|
platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
|
2015-11-18 05:10:12 +01:00
|
|
|
} else if (ret != -EINVAL) {
|
|
|
|
dev_err(dev, "failed to get rx-burst-size-dword\n");
|
|
|
|
return ret;
|
2015-03-17 10:32:45 +01:00
|
|
|
}
|
|
|
|
|
usb: chipidea: add system interface for ttctrl.ttha
In chipidea IP RTL, there is a very limited design for siTD, the detail
like below:
There is no Max Packet Size at siTD, so it uses one constant for both
Max Packet Size for packet and the packet size for the last transaction
when considering schedule.
If the ttctrl.ttha does not match against Hub Address field in siTD,
this constant is 188 bytes, else this constant is 1023 bytes.
If the ttctrl.ttha is non-zero value, RTL will use 188 as this constant,
so it will lose the data if the packet size is larger than 188 bytes, eg,
if we playback a wav which format is 48khz, 16 bits, 2 channels, the
packet size will be 192bytes, but the controller will only send 188 bytes
for this packet, the noise will be heared using USB audio card.
The use case is single transaction, but higher frame rate.
If the ttctr.ttha is zero value, we can send 1023 bytes within one
transaction, but the controller will not accept the coming tranaction
if it considers the schedule time is less than 1023 bytes. So the
limitation is we can't schedule as many as transactions within frame.
If the total bytes is already 256 bytes for previous transactions within
frame, it can't accept another transaction. The use case is multiple
transactions, but less frame rate.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
2016-02-01 07:23:44 +01:00
|
|
|
if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
|
|
|
|
platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
|
|
|
|
|
2015-09-07 13:45:25 +02:00
|
|
|
ext_id = ERR_PTR(-ENODEV);
|
|
|
|
ext_vbus = ERR_PTR(-ENODEV);
|
|
|
|
if (of_property_read_bool(dev->of_node, "extcon")) {
|
|
|
|
/* Each one of them is not mandatory */
|
|
|
|
ext_vbus = extcon_get_edev_by_phandle(dev, 0);
|
|
|
|
if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
|
|
|
|
return PTR_ERR(ext_vbus);
|
|
|
|
|
|
|
|
ext_id = extcon_get_edev_by_phandle(dev, 1);
|
|
|
|
if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
|
|
|
|
return PTR_ERR(ext_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
cable = &platdata->vbus_extcon;
|
2017-01-20 08:11:55 +01:00
|
|
|
cable->nb.notifier_call = ci_cable_notifier;
|
2015-09-07 13:45:25 +02:00
|
|
|
cable->edev = ext_vbus;
|
|
|
|
|
|
|
|
if (!IS_ERR(ext_vbus)) {
|
2016-11-30 06:57:33 +01:00
|
|
|
ret = extcon_get_state(cable->edev, EXTCON_USB);
|
2015-09-07 13:45:25 +02:00
|
|
|
if (ret)
|
2017-01-20 08:11:55 +01:00
|
|
|
cable->connected = true;
|
2015-09-07 13:45:25 +02:00
|
|
|
else
|
2017-01-20 08:11:55 +01:00
|
|
|
cable->connected = false;
|
2015-09-07 13:45:25 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
cable = &platdata->id_extcon;
|
2017-01-20 08:11:55 +01:00
|
|
|
cable->nb.notifier_call = ci_cable_notifier;
|
2015-09-07 13:45:25 +02:00
|
|
|
cable->edev = ext_id;
|
|
|
|
|
|
|
|
if (!IS_ERR(ext_id)) {
|
2016-11-30 06:57:33 +01:00
|
|
|
ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
|
2015-09-07 13:45:25 +02:00
|
|
|
if (ret)
|
2017-01-20 08:11:55 +01:00
|
|
|
cable->connected = true;
|
2015-09-07 13:45:25 +02:00
|
|
|
else
|
2017-01-20 08:11:55 +01:00
|
|
|
cable->connected = false;
|
2015-09-07 13:45:25 +02:00
|
|
|
}
|
2013-08-14 11:44:03 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-09-07 13:45:25 +02:00
|
|
|
static int ci_extcon_register(struct ci_hdrc *ci)
|
|
|
|
{
|
|
|
|
struct ci_hdrc_cable *id, *vbus;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
id = &ci->platdata->id_extcon;
|
|
|
|
id->ci = ci;
|
2017-06-23 08:39:27 +02:00
|
|
|
if (!IS_ERR_OR_NULL(id->edev)) {
|
2016-11-30 06:57:33 +01:00
|
|
|
ret = devm_extcon_register_notifier(ci->dev, id->edev,
|
|
|
|
EXTCON_USB_HOST, &id->nb);
|
2015-09-07 13:45:25 +02:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(ci->dev, "register ID failed\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
vbus = &ci->platdata->vbus_extcon;
|
|
|
|
vbus->ci = ci;
|
2017-06-23 08:39:27 +02:00
|
|
|
if (!IS_ERR_OR_NULL(vbus->edev)) {
|
2016-11-30 06:57:33 +01:00
|
|
|
ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
|
|
|
|
EXTCON_USB, &vbus->nb);
|
2015-09-07 13:45:25 +02:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(ci->dev, "register VBUS failed\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-08-14 11:44:03 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-07 16:56:42 +02:00
|
|
|
static DEFINE_IDA(ci_ida);
|
|
|
|
|
2013-06-24 13:46:36 +02:00
|
|
|
struct platform_device *ci_hdrc_add_device(struct device *dev,
|
2012-07-07 16:56:41 +02:00
|
|
|
struct resource *res, int nres,
|
2013-06-24 13:46:36 +02:00
|
|
|
struct ci_hdrc_platform_data *platdata)
|
2012-07-07 16:56:41 +02:00
|
|
|
{
|
|
|
|
struct platform_device *pdev;
|
2012-07-07 16:56:42 +02:00
|
|
|
int id, ret;
|
2012-07-07 16:56:41 +02:00
|
|
|
|
2013-08-14 11:44:03 +02:00
|
|
|
ret = ci_get_platdata(dev, platdata);
|
|
|
|
if (ret)
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
|
2012-07-07 16:56:42 +02:00
|
|
|
id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
|
|
|
|
if (id < 0)
|
|
|
|
return ERR_PTR(id);
|
|
|
|
|
|
|
|
pdev = platform_device_alloc("ci_hdrc", id);
|
|
|
|
if (!pdev) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto put_id;
|
|
|
|
}
|
2012-07-07 16:56:41 +02:00
|
|
|
|
|
|
|
pdev->dev.parent = dev;
|
|
|
|
|
|
|
|
ret = platform_device_add_resources(pdev, res, nres);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = platform_device_add(pdev);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
return pdev;
|
|
|
|
|
|
|
|
err:
|
|
|
|
platform_device_put(pdev);
|
2012-07-07 16:56:42 +02:00
|
|
|
put_id:
|
|
|
|
ida_simple_remove(&ci_ida, id);
|
2012-07-07 16:56:41 +02:00
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
2013-06-24 13:46:36 +02:00
|
|
|
EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
|
2012-07-07 16:56:41 +02:00
|
|
|
|
2013-06-24 13:46:36 +02:00
|
|
|
void ci_hdrc_remove_device(struct platform_device *pdev)
|
2012-07-07 16:56:41 +02:00
|
|
|
{
|
2012-11-22 10:11:25 +01:00
|
|
|
int id = pdev->id;
|
2012-07-07 16:56:41 +02:00
|
|
|
platform_device_unregister(pdev);
|
2012-11-22 10:11:25 +01:00
|
|
|
ida_simple_remove(&ci_ida, id);
|
2012-07-07 16:56:41 +02:00
|
|
|
}
|
2013-06-24 13:46:36 +02:00
|
|
|
EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
|
2012-07-07 16:56:41 +02:00
|
|
|
|
2013-08-14 11:44:07 +02:00
|
|
|
static inline void ci_role_destroy(struct ci_hdrc *ci)
|
|
|
|
{
|
|
|
|
ci_hdrc_gadget_destroy(ci);
|
|
|
|
ci_hdrc_host_destroy(ci);
|
2017-04-26 10:59:34 +02:00
|
|
|
if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
|
2013-08-14 11:44:10 +02:00
|
|
|
ci_hdrc_otg_destroy(ci);
|
2013-08-14 11:44:07 +02:00
|
|
|
}
|
|
|
|
|
2013-08-14 11:44:08 +02:00
|
|
|
static void ci_get_otg_capable(struct ci_hdrc *ci)
|
|
|
|
{
|
|
|
|
if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
|
|
|
|
ci->is_otg = false;
|
|
|
|
else
|
|
|
|
ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
|
|
|
|
DCCPARAMS_DC | DCCPARAMS_HC)
|
|
|
|
== (DCCPARAMS_DC | DCCPARAMS_HC));
|
2015-02-11 05:44:51 +01:00
|
|
|
if (ci->is_otg) {
|
2013-08-14 11:44:08 +02:00
|
|
|
dev_dbg(ci->dev, "It is OTG capable controller\n");
|
2015-02-11 05:44:51 +01:00
|
|
|
/* Disable and clear all OTG irq */
|
|
|
|
hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
|
|
|
|
OTGSC_INT_STATUS_BITS);
|
|
|
|
}
|
2013-08-14 11:44:08 +02:00
|
|
|
}
|
|
|
|
|
2017-03-27 04:54:27 +02:00
|
|
|
static ssize_t ci_role_show(struct device *dev, struct device_attribute *attr,
|
|
|
|
char *buf)
|
|
|
|
{
|
|
|
|
struct ci_hdrc *ci = dev_get_drvdata(dev);
|
|
|
|
|
2017-05-19 10:32:09 +02:00
|
|
|
if (ci->role != CI_ROLE_END)
|
|
|
|
return sprintf(buf, "%s\n", ci_role(ci)->name);
|
|
|
|
|
|
|
|
return 0;
|
2017-03-27 04:54:27 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t ci_role_store(struct device *dev,
|
|
|
|
struct device_attribute *attr, const char *buf, size_t n)
|
|
|
|
{
|
|
|
|
struct ci_hdrc *ci = dev_get_drvdata(dev);
|
|
|
|
enum ci_role role;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
|
|
|
|
dev_warn(dev, "Current configuration is not dual-role, quit\n");
|
|
|
|
return -EPERM;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
|
|
|
|
if (!strncmp(buf, ci->roles[role]->name,
|
|
|
|
strlen(ci->roles[role]->name)))
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (role == CI_ROLE_END || role == ci->role)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pm_runtime_get_sync(dev);
|
|
|
|
disable_irq(ci->irq);
|
|
|
|
ci_role_stop(ci);
|
|
|
|
ret = ci_role_start(ci, role);
|
|
|
|
if (!ret && ci->role == CI_ROLE_GADGET)
|
|
|
|
ci_handle_vbus_change(ci);
|
|
|
|
enable_irq(ci->irq);
|
|
|
|
pm_runtime_put_sync(dev);
|
|
|
|
|
|
|
|
return (ret == 0) ? n : ret;
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR(role, 0644, ci_role_show, ci_role_store);
|
|
|
|
|
|
|
|
static struct attribute *ci_attrs[] = {
|
|
|
|
&dev_attr_role.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
2017-08-04 14:06:38 +02:00
|
|
|
static const struct attribute_group ci_attr_group = {
|
2017-03-27 04:54:27 +02:00
|
|
|
.attrs = ci_attrs,
|
|
|
|
};
|
|
|
|
|
2012-11-19 19:21:48 +01:00
|
|
|
static int ci_hdrc_probe(struct platform_device *pdev)
|
2012-05-11 16:25:46 +02:00
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
2013-06-24 13:46:36 +02:00
|
|
|
struct ci_hdrc *ci;
|
2012-05-11 16:25:46 +02:00
|
|
|
struct resource *res;
|
|
|
|
void __iomem *base;
|
|
|
|
int ret;
|
2013-06-13 16:59:57 +02:00
|
|
|
enum usb_dr_mode dr_mode;
|
2012-05-11 16:25:46 +02:00
|
|
|
|
2014-02-19 06:41:42 +01:00
|
|
|
if (!dev_get_platdata(dev)) {
|
2012-05-11 16:25:46 +02:00
|
|
|
dev_err(dev, "platform data missing\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2013-03-30 01:46:27 +01:00
|
|
|
base = devm_ioremap_resource(dev, res);
|
|
|
|
if (IS_ERR(base))
|
|
|
|
return PTR_ERR(base);
|
2012-05-11 16:25:46 +02:00
|
|
|
|
2012-05-11 16:25:47 +02:00
|
|
|
ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
|
2014-11-26 06:44:23 +01:00
|
|
|
if (!ci)
|
2012-05-11 16:25:47 +02:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2016-11-15 11:05:33 +01:00
|
|
|
spin_lock_init(&ci->lock);
|
2012-05-11 16:25:47 +02:00
|
|
|
ci->dev = dev;
|
2014-02-19 06:41:42 +01:00
|
|
|
ci->platdata = dev_get_platdata(dev);
|
2014-01-10 06:51:27 +01:00
|
|
|
ci->imx28_write_fix = !!(ci->platdata->flags &
|
|
|
|
CI_HDRC_IMX28_WRITE_FIX);
|
2015-02-11 05:44:45 +01:00
|
|
|
ci->supports_runtime_pm = !!(ci->platdata->flags &
|
|
|
|
CI_HDRC_SUPPORTS_RUNTIME_PM);
|
2016-12-28 23:56:55 +01:00
|
|
|
platform_set_drvdata(pdev, ci);
|
2012-05-11 16:25:47 +02:00
|
|
|
|
|
|
|
ret = hw_device_init(ci, base);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev, "can't initialize hardware\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2012-05-11 16:25:46 +02:00
|
|
|
|
2016-12-28 23:56:55 +01:00
|
|
|
ret = ci_ulpi_init(ci);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-10-30 18:41:19 +01:00
|
|
|
if (ci->platdata->phy) {
|
|
|
|
ci->phy = ci->platdata->phy;
|
|
|
|
} else if (ci->platdata->usb_phy) {
|
2014-10-30 18:41:16 +01:00
|
|
|
ci->usb_phy = ci->platdata->usb_phy;
|
2014-10-30 18:41:19 +01:00
|
|
|
} else {
|
2014-11-26 06:44:35 +01:00
|
|
|
ci->phy = devm_phy_get(dev->parent, "usb-phy");
|
|
|
|
ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
|
2014-02-19 06:41:40 +01:00
|
|
|
|
2014-10-30 18:41:19 +01:00
|
|
|
/* if both generic PHY and USB PHY layers aren't enabled */
|
|
|
|
if (PTR_ERR(ci->phy) == -ENOSYS &&
|
2016-12-28 23:56:55 +01:00
|
|
|
PTR_ERR(ci->usb_phy) == -ENXIO) {
|
|
|
|
ret = -ENXIO;
|
|
|
|
goto ulpi_exit;
|
|
|
|
}
|
2014-10-30 18:41:19 +01:00
|
|
|
|
2016-12-28 23:56:55 +01:00
|
|
|
if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) {
|
|
|
|
ret = -EPROBE_DEFER;
|
|
|
|
goto ulpi_exit;
|
|
|
|
}
|
2014-02-19 06:41:40 +01:00
|
|
|
|
2014-10-30 18:41:19 +01:00
|
|
|
if (IS_ERR(ci->phy))
|
|
|
|
ci->phy = NULL;
|
|
|
|
else if (IS_ERR(ci->usb_phy))
|
|
|
|
ci->usb_phy = NULL;
|
2014-02-19 06:41:40 +01:00
|
|
|
}
|
|
|
|
|
2014-04-23 09:56:37 +02:00
|
|
|
ret = ci_usb_phy_init(ci);
|
2013-09-24 06:47:53 +02:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "unable to init phy: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-05-11 16:25:54 +02:00
|
|
|
ci->hw_bank.phys = res->start;
|
|
|
|
|
2012-05-11 16:25:47 +02:00
|
|
|
ci->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (ci->irq < 0) {
|
2012-05-11 16:25:46 +02:00
|
|
|
dev_err(dev, "missing IRQ\n");
|
2014-02-19 06:41:44 +01:00
|
|
|
ret = ci->irq;
|
2014-02-19 06:41:40 +01:00
|
|
|
goto deinit_phy;
|
2012-05-11 16:25:47 +02:00
|
|
|
}
|
|
|
|
|
2013-08-14 11:44:08 +02:00
|
|
|
ci_get_otg_capable(ci);
|
|
|
|
|
2013-06-13 16:59:57 +02:00
|
|
|
dr_mode = ci->platdata->dr_mode;
|
2012-05-11 16:25:47 +02:00
|
|
|
/* initialize role(s) before the interrupt is requested */
|
2013-06-13 16:59:57 +02:00
|
|
|
if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
|
|
|
|
ret = ci_hdrc_host_init(ci);
|
2017-04-26 10:59:34 +02:00
|
|
|
if (ret) {
|
|
|
|
if (ret == -ENXIO)
|
|
|
|
dev_info(dev, "doesn't support host\n");
|
|
|
|
else
|
|
|
|
goto deinit_phy;
|
|
|
|
}
|
2013-06-13 16:59:57 +02:00
|
|
|
}
|
2012-05-11 16:25:54 +02:00
|
|
|
|
2013-06-13 16:59:57 +02:00
|
|
|
if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
|
|
|
|
ret = ci_hdrc_gadget_init(ci);
|
2017-04-26 10:59:34 +02:00
|
|
|
if (ret) {
|
|
|
|
if (ret == -ENXIO)
|
|
|
|
dev_info(dev, "doesn't support gadget\n");
|
|
|
|
else
|
|
|
|
goto deinit_host;
|
|
|
|
}
|
2013-06-13 16:59:57 +02:00
|
|
|
}
|
2012-05-11 16:25:47 +02:00
|
|
|
|
|
|
|
if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
|
|
|
|
dev_err(dev, "no supported roles\n");
|
2013-09-24 06:47:53 +02:00
|
|
|
ret = -ENODEV;
|
2017-04-26 10:59:34 +02:00
|
|
|
goto deinit_gadget;
|
2013-08-14 11:44:10 +02:00
|
|
|
}
|
|
|
|
|
2014-09-22 02:14:16 +02:00
|
|
|
if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
|
2013-08-14 11:44:10 +02:00
|
|
|
ret = ci_hdrc_otg_init(ci);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "init otg fails, ret = %d\n", ret);
|
2017-04-26 10:59:34 +02:00
|
|
|
goto deinit_gadget;
|
2013-08-14 11:44:10 +02:00
|
|
|
}
|
2012-05-11 16:25:47 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
|
2013-08-14 11:44:08 +02:00
|
|
|
if (ci->is_otg) {
|
|
|
|
ci->role = ci_otg_role(ci);
|
2014-04-23 09:56:38 +02:00
|
|
|
/* Enable ID change irq */
|
|
|
|
hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
|
2013-08-14 11:44:08 +02:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* If the controller is not OTG capable, but support
|
|
|
|
* role switch, the defalt role is gadget, and the
|
|
|
|
* user can switch it through debugfs.
|
|
|
|
*/
|
|
|
|
ci->role = CI_ROLE_GADGET;
|
|
|
|
}
|
2012-05-11 16:25:47 +02:00
|
|
|
} else {
|
|
|
|
ci->role = ci->roles[CI_ROLE_HOST]
|
|
|
|
? CI_ROLE_HOST
|
|
|
|
: CI_ROLE_GADGET;
|
|
|
|
}
|
|
|
|
|
2014-04-23 09:56:50 +02:00
|
|
|
if (!ci_otg_is_fsm_mode(ci)) {
|
2015-02-11 05:45:03 +01:00
|
|
|
/* only update vbus status for peripheral */
|
|
|
|
if (ci->role == CI_ROLE_GADGET)
|
|
|
|
ci_handle_vbus_change(ci);
|
|
|
|
|
2014-04-23 09:56:50 +02:00
|
|
|
ret = ci_role_start(ci, ci->role);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "can't start %s role\n",
|
|
|
|
ci_role(ci)->name);
|
|
|
|
goto stop;
|
|
|
|
}
|
2012-05-11 16:25:46 +02:00
|
|
|
}
|
|
|
|
|
2014-11-26 06:44:22 +01:00
|
|
|
ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
|
|
|
|
ci->platdata->name, ci);
|
2012-05-11 16:25:47 +02:00
|
|
|
if (ret)
|
|
|
|
goto stop;
|
2012-05-11 16:25:46 +02:00
|
|
|
|
2015-09-07 13:45:25 +02:00
|
|
|
ret = ci_extcon_register(ci);
|
|
|
|
if (ret)
|
|
|
|
goto stop;
|
|
|
|
|
2015-02-11 05:44:45 +01:00
|
|
|
if (ci->supports_runtime_pm) {
|
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
|
|
|
|
pm_runtime_mark_last_busy(ci->dev);
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
|
}
|
|
|
|
|
2014-04-23 09:56:50 +02:00
|
|
|
if (ci_otg_is_fsm_mode(ci))
|
|
|
|
ci_hdrc_otg_fsm_start(ci);
|
|
|
|
|
2015-02-11 05:44:48 +01:00
|
|
|
device_set_wakeup_capable(&pdev->dev, true);
|
2013-03-30 11:53:53 +01:00
|
|
|
ret = dbg_create_files(ci);
|
2017-03-27 04:54:27 +02:00
|
|
|
if (ret)
|
|
|
|
goto stop;
|
|
|
|
|
|
|
|
ret = sysfs_create_group(&dev->kobj, &ci_attr_group);
|
|
|
|
if (ret)
|
|
|
|
goto remove_debug;
|
2012-05-11 16:25:47 +02:00
|
|
|
|
2017-03-27 04:54:27 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
remove_debug:
|
|
|
|
dbg_remove_files(ci);
|
2012-05-11 16:25:47 +02:00
|
|
|
stop:
|
2017-04-26 10:59:34 +02:00
|
|
|
if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
|
|
|
|
ci_hdrc_otg_destroy(ci);
|
|
|
|
deinit_gadget:
|
|
|
|
ci_hdrc_gadget_destroy(ci);
|
|
|
|
deinit_host:
|
|
|
|
ci_hdrc_host_destroy(ci);
|
2014-02-19 06:41:40 +01:00
|
|
|
deinit_phy:
|
2014-10-30 18:41:19 +01:00
|
|
|
ci_usb_phy_exit(ci);
|
2016-12-28 23:56:55 +01:00
|
|
|
ulpi_exit:
|
|
|
|
ci_ulpi_exit(ci);
|
2012-05-11 16:25:46 +02:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-19 19:26:20 +01:00
|
|
|
static int ci_hdrc_remove(struct platform_device *pdev)
|
2012-05-11 16:25:46 +02:00
|
|
|
{
|
2013-06-24 13:46:36 +02:00
|
|
|
struct ci_hdrc *ci = platform_get_drvdata(pdev);
|
2012-05-11 16:25:46 +02:00
|
|
|
|
2015-02-11 05:44:45 +01:00
|
|
|
if (ci->supports_runtime_pm) {
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
}
|
|
|
|
|
2013-03-30 11:53:53 +01:00
|
|
|
dbg_remove_files(ci);
|
2017-03-27 04:54:27 +02:00
|
|
|
sysfs_remove_group(&ci->dev->kobj, &ci_attr_group);
|
2013-08-14 11:44:07 +02:00
|
|
|
ci_role_destroy(ci);
|
2013-09-24 06:47:55 +02:00
|
|
|
ci_hdrc_enter_lpm(ci, true);
|
2014-10-30 18:41:19 +01:00
|
|
|
ci_usb_phy_exit(ci);
|
2016-12-28 23:56:55 +01:00
|
|
|
ci_ulpi_exit(ci);
|
2012-05-11 16:25:46 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-02-11 05:44:45 +01:00
|
|
|
#ifdef CONFIG_PM
|
2015-02-11 05:45:03 +01:00
|
|
|
/* Prepare wakeup by SRP before suspend */
|
|
|
|
static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
|
|
|
|
{
|
|
|
|
if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
|
|
|
|
!hw_read_otgsc(ci, OTGSC_ID)) {
|
|
|
|
hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
|
|
|
|
PORTSC_PP);
|
|
|
|
hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
|
|
|
|
PORTSC_WKCN);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Handle SRP when wakeup by data pulse */
|
|
|
|
static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
|
|
|
|
{
|
|
|
|
if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
|
|
|
|
(ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
|
|
|
|
if (!hw_read_otgsc(ci, OTGSC_ID)) {
|
|
|
|
ci->fsm.a_srp_det = 1;
|
|
|
|
ci->fsm.a_bus_drop = 0;
|
|
|
|
} else {
|
|
|
|
ci->fsm.id = 1;
|
|
|
|
}
|
|
|
|
ci_otg_queue_work(ci);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-26 06:44:29 +01:00
|
|
|
static void ci_controller_suspend(struct ci_hdrc *ci)
|
|
|
|
{
|
2015-02-11 05:44:45 +01:00
|
|
|
disable_irq(ci->irq);
|
2014-11-26 06:44:29 +01:00
|
|
|
ci_hdrc_enter_lpm(ci, true);
|
2015-09-09 03:18:14 +02:00
|
|
|
if (ci->platdata->phy_clkgate_delay_us)
|
|
|
|
usleep_range(ci->platdata->phy_clkgate_delay_us,
|
|
|
|
ci->platdata->phy_clkgate_delay_us + 50);
|
2015-02-11 05:44:45 +01:00
|
|
|
usb_phy_set_suspend(ci->usb_phy, 1);
|
|
|
|
ci->in_lpm = true;
|
|
|
|
enable_irq(ci->irq);
|
2014-11-26 06:44:29 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static int ci_controller_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct ci_hdrc *ci = dev_get_drvdata(dev);
|
2016-12-28 23:56:55 +01:00
|
|
|
int ret;
|
2014-11-26 06:44:29 +01:00
|
|
|
|
|
|
|
dev_dbg(dev, "at %s\n", __func__);
|
|
|
|
|
2015-02-11 05:44:45 +01:00
|
|
|
if (!ci->in_lpm) {
|
|
|
|
WARN_ON(1);
|
|
|
|
return 0;
|
|
|
|
}
|
2014-11-26 06:44:29 +01:00
|
|
|
|
2015-02-11 05:44:45 +01:00
|
|
|
ci_hdrc_enter_lpm(ci, false);
|
2016-12-28 23:56:55 +01:00
|
|
|
|
|
|
|
ret = ci_ulpi_resume(ci);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-11-26 06:44:29 +01:00
|
|
|
if (ci->usb_phy) {
|
|
|
|
usb_phy_set_suspend(ci->usb_phy, 0);
|
|
|
|
usb_phy_set_wakeup(ci->usb_phy, false);
|
|
|
|
hw_wait_phy_stable();
|
|
|
|
}
|
|
|
|
|
2015-02-11 05:44:45 +01:00
|
|
|
ci->in_lpm = false;
|
|
|
|
if (ci->wakeup_int) {
|
|
|
|
ci->wakeup_int = false;
|
|
|
|
pm_runtime_mark_last_busy(ci->dev);
|
|
|
|
pm_runtime_put_autosuspend(ci->dev);
|
|
|
|
enable_irq(ci->irq);
|
2015-02-11 05:45:03 +01:00
|
|
|
if (ci_otg_is_fsm_mode(ci))
|
|
|
|
ci_otg_fsm_wakeup_by_srp(ci);
|
2015-02-11 05:44:45 +01:00
|
|
|
}
|
|
|
|
|
2014-11-26 06:44:29 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-02-11 05:44:45 +01:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2014-11-26 06:44:29 +01:00
|
|
|
static int ci_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct ci_hdrc *ci = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
if (ci->wq)
|
|
|
|
flush_workqueue(ci->wq);
|
2015-02-11 05:44:45 +01:00
|
|
|
/*
|
|
|
|
* Controller needs to be active during suspend, otherwise the core
|
|
|
|
* may run resume when the parent is at suspend if other driver's
|
|
|
|
* suspend fails, it occurs before parent's suspend has not started,
|
|
|
|
* but the core suspend has finished.
|
|
|
|
*/
|
|
|
|
if (ci->in_lpm)
|
|
|
|
pm_runtime_resume(dev);
|
|
|
|
|
|
|
|
if (ci->in_lpm) {
|
|
|
|
WARN_ON(1);
|
|
|
|
return 0;
|
|
|
|
}
|
2014-11-26 06:44:29 +01:00
|
|
|
|
2015-02-11 05:44:48 +01:00
|
|
|
if (device_may_wakeup(dev)) {
|
2015-02-11 05:45:03 +01:00
|
|
|
if (ci_otg_is_fsm_mode(ci))
|
|
|
|
ci_otg_fsm_suspend_for_srp(ci);
|
|
|
|
|
2015-02-11 05:44:48 +01:00
|
|
|
usb_phy_set_wakeup(ci->usb_phy, true);
|
|
|
|
enable_irq_wake(ci->irq);
|
|
|
|
}
|
|
|
|
|
2014-11-26 06:44:29 +01:00
|
|
|
ci_controller_suspend(ci);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ci_resume(struct device *dev)
|
|
|
|
{
|
2015-02-11 05:44:45 +01:00
|
|
|
struct ci_hdrc *ci = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
2015-02-11 05:44:48 +01:00
|
|
|
if (device_may_wakeup(dev))
|
|
|
|
disable_irq_wake(ci->irq);
|
|
|
|
|
2015-02-11 05:44:45 +01:00
|
|
|
ret = ci_controller_resume(dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (ci->supports_runtime_pm) {
|
|
|
|
pm_runtime_disable(dev);
|
|
|
|
pm_runtime_set_active(dev);
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
2014-11-26 06:44:29 +01:00
|
|
|
}
|
|
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
|
2015-02-11 05:44:45 +01:00
|
|
|
static int ci_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct ci_hdrc *ci = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
dev_dbg(dev, "at %s\n", __func__);
|
|
|
|
|
|
|
|
if (ci->in_lpm) {
|
|
|
|
WARN_ON(1);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-02-11 05:45:03 +01:00
|
|
|
if (ci_otg_is_fsm_mode(ci))
|
|
|
|
ci_otg_fsm_suspend_for_srp(ci);
|
|
|
|
|
2015-02-11 05:44:45 +01:00
|
|
|
usb_phy_set_wakeup(ci->usb_phy, true);
|
|
|
|
ci_controller_suspend(ci);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ci_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
return ci_controller_resume(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_PM */
|
2014-11-26 06:44:29 +01:00
|
|
|
static const struct dev_pm_ops ci_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
|
2015-02-11 05:44:45 +01:00
|
|
|
SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
|
2014-11-26 06:44:29 +01:00
|
|
|
};
|
2015-02-11 05:44:45 +01:00
|
|
|
|
2012-05-11 16:25:47 +02:00
|
|
|
static struct platform_driver ci_hdrc_driver = {
|
|
|
|
.probe = ci_hdrc_probe,
|
2012-11-19 19:21:08 +01:00
|
|
|
.remove = ci_hdrc_remove,
|
2012-05-11 16:25:46 +02:00
|
|
|
.driver = {
|
2012-05-11 16:25:47 +02:00
|
|
|
.name = "ci_hdrc",
|
2014-11-26 06:44:29 +01:00
|
|
|
.pm = &ci_pm_ops,
|
2012-05-11 16:25:46 +02:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
usb: chipidea: ehci_init_driver is intended to call one time
The ehci_init_driver is used to initialize hcd APIs for each
ehci controller driver, it is designed to be called only one time
and before driver register is called. The current design will
cause ehci_init_driver is called multiple times at probe process,
it will cause hc_driver's initialization affect current running hcd.
We run out NULL pointer dereference problem when one hcd is started
by module_init, and the other is started by otg thread at SMP platform.
The reason for this problem is ehci_init_driver will do memory copy
for current uniform hc_driver, and this memory copy will do memset (as 0)
first, so when the first hcd is running usb_add_hcd, and the second
hcd may clear the uniform hc_driver's space (at ehci_init_driver),
then the first hcd will meet NULL pointer at the same time.
See below two logs:
LOG_1:
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.1: doesn't support gadget
Unable to handle kernel NULL pointer dereference at virtual address 00000014
pgd = 80004000
[00000014] *pgd=00000000
Internal error: Oops: 805 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 PID: 108 Comm: kworker/u8:2 Not tainted 3.14.38-222193-g24b2734-dirty #25
Workqueue: ci_otg ci_otg_work
task: d839ec00 ti: d8400000 task.ti: d8400000
PC is at ehci_run+0x4c/0x284
LR is at _raw_spin_unlock_irqrestore+0x28/0x54
pc : [<8041f9a0>] lr : [<8070ea84>] psr: 60000113
sp : d8401e30 ip : 00000000 fp : d8004400
r10: 00000001 r9 : 00000001 r8 : 00000000
r7 : 00000000 r6 : d8419940 r5 : 80dd24c0 r4 : d8419800
r3 : 8001d060 r2 : 00000000 r1 : 00000001 r0 : 00000000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 1000404a DAC: 00000015
Process kworker/u8:2 (pid: 108, stack limit = 0xd8400238)
Stack: (0xd8401e30 to 0xd8402000)
1e20: d87523c0 d8401e48 66667562 d8419800
1e40: 00000000 00000000 d8419800 00000000 00000000 00000000 d84198b0 8040fcdc
1e60: 00000000 80dd320c d8477610 d8419c00 d803d010 d8419800 00000000 00000000
1e80: d8004400 00000000 d8400008 80431494 80431374 d803d100 d803d010 d803d1ac
1ea0: 00000000 80432428 804323d4 d803d100 00000001 80435eb8 80e0d0bc d803d100
1ec0: 00000006 80436458 00000000 d803d100 80e92ec8 80436f44 d803d010 d803d100
1ee0: d83fde00 8043292c d8752710 d803d1f4 d803d010 8042ddfc 8042ddb8 d83f3b00
1f00: d803d1f4 80042b60 00000000 00000003 00000001 00000001 80054598 d83f3b00
1f20: d8004400 d83f3b18 d8004414 d8400000 80e3957b 00000089 d8004400 80043814
1f40: d839ec00 00000000 d83fcd80 d83f3b00 800436e4 00000000 00000000 00000000
1f60: 00000000 80048f34 00000000 00000000 00000000 d83f3b00 00000000 00000000
1f80: d8401f80 d8401f80 00000000 00000000 d8401f90 d8401f90 d8401fac d83fcd80
1fa0: 80048e68 00000000 00000000 8000e538 00000000 00000000 00000000 00000000
1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
[<8041f9a0>] (ehci_run) from [<8040fcdc>] (usb_add_hcd+0x248/0x6e8)
[<8040fcdc>] (usb_add_hcd) from [<80431494>] (host_start+0x120/0x2e4)
[<80431494>] (host_start) from [<80432428>] (ci_otg_start_host+0x54/0xbc)
[<80432428>] (ci_otg_start_host) from [<80435eb8>] (otg_set_protocol+0xa4/0xd0)
[<80435eb8>] (otg_set_protocol) from [<80436458>] (otg_set_state+0x574/0xc58)
[<80436458>] (otg_set_state) from [<80436f44>] (otg_statemachine+0x408/0x46c)
[<80436f44>] (otg_statemachine) from [<8043292c>] (ci_otg_fsm_work+0x3c/0x190)
[<8043292c>] (ci_otg_fsm_work) from [<8042ddfc>] (ci_otg_work+0x44/0x1c4)
[<8042ddfc>] (ci_otg_work) from [<80042b60>] (process_one_work+0xf4/0x35c)
[<80042b60>] (process_one_work) from [<80043814>] (worker_thread+0x130/0x3bc)
[<80043814>] (worker_thread) from [<80048f34>] (kthread+0xcc/0xe4)
[<80048f34>] (kthread) from [<8000e538>] (ret_from_fork+0x14/0x3c)
Code: e5953018 e3530000 0a000000 e12fff33 (e5878014)
LOG_2:
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.1: doesn't support gadget
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = 80004000
[00000000] *pgd=00000000
In Online 00:00ternal e Offline rror: Oops: 80000005 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 PID: 108 Comm: kworker/u8:2 Not tainted 3.14.38-02007-g24b2734-dirty #127
Workque Online 00:00ue: ci_o Offline tg ci_otg_work
Online 00:00task: d8 Offline 39ec00 ti: d83ea000 task.ti: d83ea000
PC is at 0x0
LR is at usb_add_hcd+0x248/0x6e8
pc : [<00000000>] lr : [<8040f644>] psr: 60000113
sp : d83ebe60 ip : 00000000 fp : d8004400
r10: 00000001 r9 : 00000001 r8 : d85fd4b0
r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : d85fd400
r3 : 00000000 r2 : d85fd4f4 r1 : 80410178 r0 : d85fd400
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 1000404a DAC: 00000015
Process kworker/u8:2 (pid: 108, stack limit = 0xd83ea238)
Stack: (0xd83ebe60 to 0xd83ec000)
be60: 00000000 80dd920c d8654e10 d85fd800 d803e010 d85fd400 00000000 00000000
be80: d8004400 00000000 d83ea008 80430e34 80430d14 d803e100 d803e010 d803e1ac
bea0: 00000000 80431dc8 80431d74 d803e100 00000001 80435858 80e130bc d803e100
bec0: 00000006 80435df8 00000000 d803e100 80e98ec8 804368e4 d803e010 d803e100
bee0: d86e8100 804322cc d86cf050 d803e1f4 d803e010 8042d79c 8042d758 d83cf900
bf00: d803e1f4 80042b78 00000000 00000003 00000001 00000001 800545e8 d83cf900
bf20: d8004400 d83cf918 d8004414 d83ea000 80e3f57b 00000089 d8004400 8004382c
bf40: d839ec00 00000000 d8393780 d83cf900 800436fc 00000000 00000000 00000000
bf60: 00000000 80048f50 80e019f4 00000000 0000264c d83cf900 00000000 00000000
bf80: d83ebf80 d83ebf80 00000000 00000000 d83ebf90 d83ebf90 d83ebfac d8393780
bfa0: 80048e84 00000000 00000000 8000e538 00000000 00000000 00000000 00000000
bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 ee66e85d 133ebd03
[<804 Online 00:000f644>] Offline (usb_add_hcd) from [<80430e34>] (host_start+0x120/0x2e4)
[<80430e34>] (host_start) from [<80431dc8>] (ci_otg_start_host+0x54/0xbc)
[<80431dc8>] (ci_otg_start_host) from [<80435858>] (otg_set_protocol+0xa4/0xd0)
[<80435858>] (otg_set_protocol) from [<80435df8>] (otg_set_state+0x574/0xc58)
[<80435df8>] (otg_set_state) from [<804368e4>] (otg_statemachine+0x408/0x46c)
[<804368e4>] (otg_statemachine) from [<804322cc>] (ci_otg_fsm_work+0x3c/0x190)
[<804322cc>] (ci_otg_fsm_work) from [<8042d79c>] (ci_otg_work+0x44/0x1c4)
[<8042d79c>] (ci_otg_work) from [<80042b78>] (process_one_work+0xf4/0x35c)
[<80042b78>] (process_one_work) from [<8004382c>] (worker_thread+0x130/0x3bc)
[<8004382c>] (worker_thread) from [<80048f50>] (kthread+0xcc/0xe4)
[<80048f50>] (kthread) from [<8000e538>] (ret_from_fork+0x14/0x3c)
Code: bad PC value
Cc: Jun Li <jun.li@freescale.com>
Cc: <stable@vger.kernel.org>
Cc: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
2015-07-21 03:51:29 +02:00
|
|
|
static int __init ci_hdrc_platform_register(void)
|
|
|
|
{
|
|
|
|
ci_hdrc_host_driver_init();
|
|
|
|
return platform_driver_register(&ci_hdrc_driver);
|
|
|
|
}
|
|
|
|
module_init(ci_hdrc_platform_register);
|
|
|
|
|
|
|
|
static void __exit ci_hdrc_platform_unregister(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&ci_hdrc_driver);
|
|
|
|
}
|
|
|
|
module_exit(ci_hdrc_platform_unregister);
|
2012-05-11 16:25:46 +02:00
|
|
|
|
2012-05-11 16:25:47 +02:00
|
|
|
MODULE_ALIAS("platform:ci_hdrc");
|
2012-05-11 16:25:46 +02:00
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
|
2012-05-11 16:25:47 +02:00
|
|
|
MODULE_DESCRIPTION("ChipIdea HDRC Driver");
|