2012-05-16 12:26:10 +02:00
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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#include <asm/dpmc.h>
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#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
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.section .l1.text
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ENTRY(_enter_hibernate)
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/* switch stack to L1 scratch, prepare for ddr srfr */
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P0.H = HI(PM_STACK);
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P0.L = LO(PM_STACK);
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SP = P0;
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call _bf609_ddr_sr;
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call _bfin_hibernate_syscontrol;
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P0.H = HI(DPM0_RESTORE4);
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P0.L = LO(DPM0_RESTORE4);
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P1.H = _bf609_pm_data;
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P1.L = _bf609_pm_data;
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[P0] = P1;
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P0.H = HI(DPM0_CTL);
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P0.L = LO(DPM0_CTL);
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R3.H = HI(0x00000010);
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R3.L = LO(0x00000010);
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2012-05-17 11:33:00 +02:00
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bfin_init_pm_bench_cycles;
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2012-05-16 12:26:10 +02:00
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[P0] = R3;
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SSYNC;
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ENDPROC(_enter_hibernate_mode)
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.section .text
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ENTRY(_bf609_hibernate)
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bfin_cpu_reg_save;
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bfin_core_mmr_save;
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P0.H = _bf609_pm_data;
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P0.L = _bf609_pm_data;
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R1.H = 0xDEAD;
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R1.L = 0xBEEF;
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R2.H = .Lpm_resume_here;
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R2.L = .Lpm_resume_here;
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[P0++] = R1;
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[P0++] = R2;
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[P0++] = SP;
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P1.H = _enter_hibernate;
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P1.L = _enter_hibernate;
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call (P1);
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.Lpm_resume_here:
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bfin_core_mmr_restore;
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bfin_cpu_reg_restore;
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[--sp] = RETI; /* Clear Global Interrupt Disable */
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SP += 4;
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RTS;
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ENDPROC(_bf609_hibernate)
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