2011-08-24 02:00:42 +02:00
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/******************************************************************************
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* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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******************************************************************************/
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#include "rtl_core.h"
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#include "r8192E_hw.h"
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#include "r8192E_phyreg.h"
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#include "r8190P_rtl8256.h"
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#include "r8192E_phy.h"
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#include "rtl_dm.h"
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#include "dot11d.h"
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#include "r8192E_hwimg.h"
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static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
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0,
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0x085c,
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0x08dc,
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0x095c,
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0x09dc,
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0x0a5c,
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0x0adc,
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0x0b5c,
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0x0bdc,
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0x0c5c,
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0x0cdc,
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0x0d5c,
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0x0ddc,
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0x0e5c,
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0x0f72,
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};
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/*************************Define local function prototype**********************/
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2011-08-25 18:48:16 +02:00
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static u32 phy_FwRFSerialRead(struct net_device *dev,
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enum rf90_radio_path eRFPath,
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u32 Offset);
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static void phy_FwRFSerialWrite(struct net_device *dev,
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enum rf90_radio_path eRFPath,
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u32 Offset, u32 Data);
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2011-08-25 21:07:05 +02:00
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static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
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2011-08-24 02:00:42 +02:00
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{
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u32 i;
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2011-08-25 18:48:16 +02:00
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for (i = 0; i <= 31; i++) {
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if (((dwBitMask >> i) & 0x1) == 1)
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2011-08-24 02:00:42 +02:00
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break;
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}
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return i;
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}
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2011-08-25 18:48:16 +02:00
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u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
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2011-08-24 02:00:42 +02:00
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{
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u8 ret = 1;
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struct r8192_priv *priv = rtllib_priv(dev);
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if (priv->rf_type == RF_2T4R)
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ret = 0;
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2011-08-25 18:48:16 +02:00
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else if (priv->rf_type == RF_1T2R) {
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2011-08-24 02:00:42 +02:00
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if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
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ret = 1;
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else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
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ret = 0;
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}
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return ret;
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}
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2011-08-25 18:48:16 +02:00
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void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
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u32 dwData)
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2011-08-24 02:00:42 +02:00
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{
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u32 OriginalValue, BitShift, NewValue;
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2011-08-25 18:48:16 +02:00
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if (dwBitMask != bMaskDWord) {
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2011-08-24 02:00:42 +02:00
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OriginalValue = read_nic_dword(dev, dwRegAddr);
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BitShift = rtl8192_CalculateBitShift(dwBitMask);
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2011-08-25 18:48:16 +02:00
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NewValue = (((OriginalValue) & (~dwBitMask)) |
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(dwData << BitShift));
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2011-08-24 02:00:42 +02:00
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write_nic_dword(dev, dwRegAddr, NewValue);
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2011-08-25 18:48:16 +02:00
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} else
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2011-08-24 02:00:42 +02:00
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write_nic_dword(dev, dwRegAddr, dwData);
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return;
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}
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2011-08-25 18:48:16 +02:00
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u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
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2011-08-24 02:00:42 +02:00
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{
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u32 Ret = 0, OriginalValue, BitShift;
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OriginalValue = read_nic_dword(dev, dwRegAddr);
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BitShift = rtl8192_CalculateBitShift(dwBitMask);
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Ret = (OriginalValue & dwBitMask) >> BitShift;
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2011-08-25 18:48:16 +02:00
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return Ret;
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2011-08-24 02:00:42 +02:00
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}
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2011-08-25 21:07:05 +02:00
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static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
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enum rf90_radio_path eRFPath, u32 Offset)
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2011-08-24 02:00:42 +02:00
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{
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struct r8192_priv *priv = rtllib_priv(dev);
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u32 ret = 0;
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u32 NewOffset = 0;
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2011-08-25 18:48:16 +02:00
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struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
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2011-08-24 02:00:42 +02:00
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Offset &= 0x3f;
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2011-08-25 18:48:16 +02:00
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if (priv->rf_chip == RF_8256) {
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2011-08-24 02:00:42 +02:00
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rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
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2011-08-25 18:48:16 +02:00
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if (Offset >= 31) {
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2011-08-24 02:00:42 +02:00
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priv->RfReg0Value[eRFPath] |= 0x140;
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2011-08-25 18:48:16 +02:00
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
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bMaskDWord,
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(priv->RfReg0Value[eRFPath]<<16));
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NewOffset = Offset - 30;
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} else if (Offset >= 16) {
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2011-08-24 02:00:42 +02:00
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priv->RfReg0Value[eRFPath] |= 0x100;
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priv->RfReg0Value[eRFPath] &= (~0x40);
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2011-08-25 18:48:16 +02:00
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
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bMaskDWord,
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(priv->RfReg0Value[eRFPath]<<16));
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2011-08-24 02:00:42 +02:00
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NewOffset = Offset - 15;
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2011-08-25 18:48:16 +02:00
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} else
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2011-08-24 02:00:42 +02:00
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NewOffset = Offset;
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2011-08-25 18:48:16 +02:00
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} else {
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RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need"
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" to be 8256\n");
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2011-08-24 02:00:42 +02:00
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NewOffset = Offset;
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}
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2011-08-25 18:48:16 +02:00
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rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
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NewOffset);
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2011-08-24 02:00:42 +02:00
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rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
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rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
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2011-08-25 18:48:16 +02:00
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mdelay(1);
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
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bLSSIReadBackData);
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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if (priv->rf_chip == RF_8256) {
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2011-08-24 02:00:42 +02:00
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priv->RfReg0Value[eRFPath] &= 0xebf;
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2011-08-25 18:48:16 +02:00
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
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(priv->RfReg0Value[eRFPath] << 16));
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2011-08-24 02:00:42 +02:00
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rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
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}
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return ret;
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}
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2011-08-25 21:07:05 +02:00
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static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
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enum rf90_radio_path eRFPath, u32 Offset,
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u32 Data)
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2011-08-24 02:00:42 +02:00
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{
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struct r8192_priv *priv = rtllib_priv(dev);
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u32 DataAndAddr = 0, NewOffset = 0;
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2011-07-19 04:16:51 +02:00
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struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
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2011-08-24 02:00:42 +02:00
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Offset &= 0x3f;
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2011-08-25 18:48:16 +02:00
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if (priv->rf_chip == RF_8256) {
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2011-08-24 02:00:42 +02:00
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rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
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2011-08-25 18:48:16 +02:00
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if (Offset >= 31) {
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2011-08-24 02:00:42 +02:00
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priv->RfReg0Value[eRFPath] |= 0x140;
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2011-08-25 18:48:16 +02:00
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
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bMaskDWord,
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(priv->RfReg0Value[eRFPath] << 16));
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2011-08-24 02:00:42 +02:00
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NewOffset = Offset - 30;
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2011-08-25 18:48:16 +02:00
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} else if (Offset >= 16) {
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2011-08-24 02:00:42 +02:00
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priv->RfReg0Value[eRFPath] |= 0x100;
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priv->RfReg0Value[eRFPath] &= (~0x40);
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2011-08-25 18:48:16 +02:00
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
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bMaskDWord,
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(priv->RfReg0Value[eRFPath] << 16));
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2011-08-24 02:00:42 +02:00
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NewOffset = Offset - 15;
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2011-08-25 18:48:16 +02:00
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} else
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2011-08-24 02:00:42 +02:00
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NewOffset = Offset;
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2011-08-25 18:48:16 +02:00
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} else {
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RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be"
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" 8256\n");
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2011-08-24 02:00:42 +02:00
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NewOffset = Offset;
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}
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DataAndAddr = (Data<<16) | (NewOffset&0x3f);
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
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2011-08-25 18:48:16 +02:00
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if (Offset == 0x0)
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2011-08-24 02:00:42 +02:00
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priv->RfReg0Value[eRFPath] = Data;
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2011-08-25 18:48:16 +02:00
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if (priv->rf_chip == RF_8256) {
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if (Offset != 0) {
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2011-08-24 02:00:42 +02:00
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priv->RfReg0Value[eRFPath] &= 0xebf;
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rtl8192_setBBreg(
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dev,
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pPhyReg->rf3wireOffset,
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bMaskDWord,
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(priv->RfReg0Value[eRFPath] << 16));
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}
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rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
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}
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return;
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}
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2011-08-25 18:48:16 +02:00
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void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
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u32 RegAddr, u32 BitMask, u32 Data)
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2011-08-24 02:00:42 +02:00
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{
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struct r8192_priv *priv = rtllib_priv(dev);
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u32 Original_Value, BitShift, New_Value;
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if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
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return;
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if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
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return;
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RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
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2011-08-25 18:48:16 +02:00
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if (priv->Rf_Mode == RF_OP_By_FW) {
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if (BitMask != bMask12Bits) {
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Original_Value = phy_FwRFSerialRead(dev, eRFPath,
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RegAddr);
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2011-08-24 02:00:42 +02:00
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BitShift = rtl8192_CalculateBitShift(BitMask);
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2011-08-25 18:48:16 +02:00
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New_Value = (((Original_Value) & (~BitMask)) |
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(Data << BitShift));
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2011-08-24 02:00:42 +02:00
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phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
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2011-08-25 18:48:16 +02:00
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} else
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2011-08-24 02:00:42 +02:00
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phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
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udelay(200);
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2011-08-25 18:48:16 +02:00
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} else {
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if (BitMask != bMask12Bits) {
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Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
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RegAddr);
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2011-08-24 02:00:42 +02:00
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BitShift = rtl8192_CalculateBitShift(BitMask);
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2011-08-25 18:48:16 +02:00
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New_Value = (((Original_Value) & (~BitMask)) |
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(Data << BitShift));
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr,
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New_Value);
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} else
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2011-08-24 02:00:42 +02:00
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rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
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}
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return;
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}
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2011-08-25 18:48:16 +02:00
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u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
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u32 RegAddr, u32 BitMask)
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2011-08-24 02:00:42 +02:00
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{
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u32 Original_Value, Readback_Value, BitShift;
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struct r8192_priv *priv = rtllib_priv(dev);
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if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
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return 0;
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if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
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return 0;
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down(&priv->rf_sem);
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2011-08-25 18:48:16 +02:00
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if (priv->Rf_Mode == RF_OP_By_FW) {
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2011-08-24 02:00:42 +02:00
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Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
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udelay(200);
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2011-08-25 18:48:16 +02:00
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} else {
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Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
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RegAddr);
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2011-08-24 02:00:42 +02:00
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}
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BitShift = rtl8192_CalculateBitShift(BitMask);
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Readback_Value = (Original_Value & BitMask) >> BitShift;
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up(&priv->rf_sem);
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2011-08-25 18:48:16 +02:00
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return Readback_Value;
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2011-08-24 02:00:42 +02:00
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}
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2011-08-25 18:48:16 +02:00
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static u32 phy_FwRFSerialRead(struct net_device *dev,
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enum rf90_radio_path eRFPath, u32 Offset)
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2011-08-24 02:00:42 +02:00
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{
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u32 retValue = 0;
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u32 Data = 0;
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u8 time = 0;
|
2011-08-25 18:48:16 +02:00
|
|
|
Data |= ((Offset & 0xFF) << 12);
|
|
|
|
Data |= ((eRFPath & 0x3) << 20);
|
2011-08-24 02:00:42 +02:00
|
|
|
Data |= 0x80000000;
|
2011-08-25 18:48:16 +02:00
|
|
|
while (read_nic_dword(dev, QPNR)&0x80000000) {
|
2011-08-24 02:00:42 +02:00
|
|
|
if (time++ < 100)
|
|
|
|
udelay(10);
|
|
|
|
else
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
write_nic_dword(dev, QPNR, Data);
|
2011-08-25 18:48:16 +02:00
|
|
|
while (read_nic_dword(dev, QPNR) & 0x80000000) {
|
2011-08-24 02:00:42 +02:00
|
|
|
if (time++ < 100)
|
|
|
|
udelay(10);
|
|
|
|
else
|
2011-08-25 18:48:16 +02:00
|
|
|
return 0;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
retValue = read_nic_dword(dev, RF_DATA);
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
return retValue;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
} /* phy_FwRFSerialRead */
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
static void phy_FwRFSerialWrite(struct net_device *dev,
|
|
|
|
enum rf90_radio_path eRFPath,
|
|
|
|
u32 Offset, u32 Data)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
u8 time = 0;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
Data |= ((Offset & 0xFF) << 12);
|
|
|
|
Data |= ((eRFPath & 0x3) << 20);
|
2011-08-24 02:00:42 +02:00
|
|
|
Data |= 0x400000;
|
|
|
|
Data |= 0x80000000;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
while (read_nic_dword(dev, QPNR) & 0x80000000) {
|
2011-08-24 02:00:42 +02:00
|
|
|
if (time++ < 100)
|
|
|
|
udelay(10);
|
|
|
|
else
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
write_nic_dword(dev, QPNR, Data);
|
|
|
|
|
|
|
|
} /* phy_FwRFSerialWrite */
|
|
|
|
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
void rtl8192_phy_configmac(struct net_device *dev)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
u32 dwArrayLen = 0, i = 0;
|
2011-08-25 18:48:16 +02:00
|
|
|
u32 *pdwArray = NULL;
|
2011-08-24 02:00:42 +02:00
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
2011-08-25 18:48:16 +02:00
|
|
|
|
|
|
|
if (priv->bTXPowerDataReadFromEEPORM) {
|
2011-08-24 02:00:42 +02:00
|
|
|
RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
|
|
|
|
dwArrayLen = MACPHY_Array_PGLength;
|
|
|
|
pdwArray = Rtl819XMACPHY_Array_PG;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
} else {
|
|
|
|
RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
|
2011-08-24 02:00:42 +02:00
|
|
|
dwArrayLen = MACPHY_ArrayLength;
|
|
|
|
pdwArray = Rtl819XMACPHY_Array;
|
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
for (i = 0; i < dwArrayLen; i += 3) {
|
|
|
|
RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MAC"
|
|
|
|
"PHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
|
|
|
|
pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
|
2011-08-24 02:00:42 +02:00
|
|
|
if (pdwArray[i] == 0x318)
|
|
|
|
pdwArray[i+2] = 0x00000800;
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
|
|
|
|
pdwArray[i+2]);
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
int i;
|
2011-08-25 18:48:16 +02:00
|
|
|
u32 *Rtl819XPHY_REGArray_Table = NULL;
|
|
|
|
u32 *Rtl819XAGCTAB_Array_Table = NULL;
|
|
|
|
u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
|
2011-08-24 02:00:42 +02:00
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
2011-08-25 18:48:16 +02:00
|
|
|
|
|
|
|
AGCTAB_ArrayLen = AGCTAB_ArrayLength;
|
|
|
|
Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
|
|
|
|
if (priv->rf_type == RF_2T4R) {
|
|
|
|
PHY_REGArrayLen = PHY_REGArrayLength;
|
|
|
|
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
|
|
|
|
} else if (priv->rf_type == RF_1T2R) {
|
|
|
|
PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
|
|
|
|
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (ConfigType == BaseBand_Config_PHY_REG) {
|
|
|
|
for (i = 0; i < PHY_REGArrayLen; i += 2) {
|
|
|
|
rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i],
|
|
|
|
bMaskDWord,
|
|
|
|
Rtl819XPHY_REGArray_Table[i+1]);
|
|
|
|
RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray"
|
|
|
|
"[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
|
|
|
|
i, Rtl819XPHY_REGArray_Table[i],
|
|
|
|
Rtl819XPHY_REGArray_Table[i+1]);
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
} else if (ConfigType == BaseBand_Config_AGC_TAB) {
|
|
|
|
for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
|
|
|
|
rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i],
|
|
|
|
bMaskDWord,
|
|
|
|
Rtl819XAGCTAB_Array_Table[i+1]);
|
|
|
|
RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] "
|
|
|
|
"is %x rtl819XAGCTAB_Array[1] is %x\n", i,
|
|
|
|
Rtl819XAGCTAB_Array_Table[i],
|
|
|
|
Rtl819XAGCTAB_Array_Table[i+1]);
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
|
2011-08-25 21:07:05 +02:00
|
|
|
static void rtl8192_InitBBRFRegDef(struct net_device *dev)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
2011-08-25 18:48:16 +02:00
|
|
|
|
2011-08-24 02:00:42 +02:00
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
|
|
|
|
|
|
|
|
priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
|
|
|
|
priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
|
|
|
|
priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
|
|
|
|
priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
|
|
|
|
|
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
|
|
|
|
bool rtl8192_phy_checkBBAndRF(struct net_device *dev,
|
|
|
|
enum hw90_block CheckBlock,
|
|
|
|
enum rf90_radio_path eRFPath)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
bool ret = true;
|
|
|
|
u32 i, CheckTimes = 4, dwRegRead = 0;
|
|
|
|
u32 WriteAddr[4];
|
|
|
|
u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
|
2011-08-25 18:48:16 +02:00
|
|
|
|
2011-08-24 02:00:42 +02:00
|
|
|
WriteAddr[HW90_BLOCK_MAC] = 0x100;
|
|
|
|
WriteAddr[HW90_BLOCK_PHY0] = 0x900;
|
|
|
|
WriteAddr[HW90_BLOCK_PHY1] = 0x800;
|
|
|
|
WriteAddr[HW90_BLOCK_RF] = 0x3;
|
2011-08-25 18:48:16 +02:00
|
|
|
RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
|
|
|
|
CheckBlock);
|
|
|
|
for (i = 0; i < CheckTimes; i++) {
|
|
|
|
switch (CheckBlock) {
|
2011-08-24 02:00:42 +02:00
|
|
|
case HW90_BLOCK_MAC:
|
2011-08-25 18:48:16 +02:00
|
|
|
RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write "
|
|
|
|
"0x100 here!");
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case HW90_BLOCK_PHY0:
|
|
|
|
case HW90_BLOCK_PHY1:
|
2011-08-25 18:48:16 +02:00
|
|
|
write_nic_dword(dev, WriteAddr[CheckBlock],
|
|
|
|
WriteData[i]);
|
2011-08-24 02:00:42 +02:00
|
|
|
dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HW90_BLOCK_RF:
|
|
|
|
WriteData[i] &= 0xfff;
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_phy_SetRFReg(dev, eRFPath,
|
|
|
|
WriteAddr[HW90_BLOCK_RF],
|
|
|
|
bMask12Bits, WriteData[i]);
|
2011-08-24 02:00:42 +02:00
|
|
|
mdelay(10);
|
2011-08-25 18:48:16 +02:00
|
|
|
dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath,
|
|
|
|
WriteAddr[HW90_BLOCK_RF],
|
|
|
|
bMaskDWord);
|
2011-08-24 02:00:42 +02:00
|
|
|
mdelay(10);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
ret = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (dwRegRead != WriteData[i]) {
|
|
|
|
RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, "
|
|
|
|
"WriteData: %x\n", dwRegRead, WriteData[i]);
|
2011-08-24 02:00:42 +02:00
|
|
|
ret = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-08-25 21:07:05 +02:00
|
|
|
static bool rtl8192_BB_Config_ParaFile(struct net_device *dev)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
|
|
|
bool rtStatus = true;
|
|
|
|
u8 bRegValue = 0, eCheckItem = 0;
|
|
|
|
u32 dwRegValue = 0;
|
|
|
|
|
|
|
|
bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
|
2011-08-25 18:48:16 +02:00
|
|
|
write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
dwRegValue = read_nic_dword(dev, CPU_GEN);
|
|
|
|
write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
|
|
|
|
eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
|
|
|
|
rtStatus = rtl8192_phy_checkBBAndRF(dev,
|
|
|
|
(enum hw90_block)eCheckItem,
|
|
|
|
(enum rf90_radio_path)0);
|
|
|
|
if (rtStatus != true) {
|
|
|
|
RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():"
|
|
|
|
"Check PHY%d Fail!!\n", eCheckItem-1);
|
2011-08-24 02:00:42 +02:00
|
|
|
return rtStatus;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
|
|
|
|
rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
|
|
|
|
|
|
|
|
dwRegValue = read_nic_dword(dev, CPU_GEN);
|
|
|
|
write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
|
|
|
|
|
|
|
|
rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (priv->IC_Cut > VERSION_8190_BD) {
|
2011-08-24 02:00:42 +02:00
|
|
|
if (priv->rf_type == RF_2T4R)
|
2011-08-25 18:48:16 +02:00
|
|
|
dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
|
|
|
|
priv->AntennaTxPwDiff[1]<<4 |
|
|
|
|
priv->AntennaTxPwDiff[0]);
|
2011-08-24 02:00:42 +02:00
|
|
|
else
|
|
|
|
dwRegValue = 0x0;
|
|
|
|
rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
|
|
|
|
(bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
|
|
|
|
|
|
|
|
|
|
|
|
dwRegValue = priv->CrystalCap;
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
|
|
|
|
dwRegValue);
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return rtStatus;
|
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
bool rtl8192_BBConfig(struct net_device *dev)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
bool rtStatus = true;
|
2011-08-25 18:48:16 +02:00
|
|
|
|
2011-08-24 02:00:42 +02:00
|
|
|
rtl8192_InitBBRFRegDef(dev);
|
|
|
|
rtStatus = rtl8192_BB_Config_ParaFile(dev);
|
|
|
|
return rtStatus;
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
void rtl8192_phy_getTxPower(struct net_device *dev)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
2011-08-25 18:48:16 +02:00
|
|
|
|
2011-08-24 02:00:42 +02:00
|
|
|
priv->MCSTxPowerLevelOriginalOffset[0] =
|
|
|
|
read_nic_dword(dev, rTxAGC_Rate18_06);
|
|
|
|
priv->MCSTxPowerLevelOriginalOffset[1] =
|
|
|
|
read_nic_dword(dev, rTxAGC_Rate54_24);
|
|
|
|
priv->MCSTxPowerLevelOriginalOffset[2] =
|
|
|
|
read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
|
|
|
|
priv->MCSTxPowerLevelOriginalOffset[3] =
|
|
|
|
read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
|
|
|
|
priv->MCSTxPowerLevelOriginalOffset[4] =
|
|
|
|
read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
|
|
|
|
priv->MCSTxPowerLevelOriginalOffset[5] =
|
|
|
|
read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
|
|
|
|
|
|
|
|
priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
|
|
|
|
priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
|
|
|
|
priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
|
|
|
|
priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
|
2011-08-25 18:48:16 +02:00
|
|
|
RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, "
|
|
|
|
"c60=0x%x, c68=0x%x)\n",
|
2011-08-24 02:00:42 +02:00
|
|
|
priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
|
|
|
|
priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
|
|
|
|
|
|
|
|
priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
|
|
|
|
priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
|
2011-08-25 18:48:16 +02:00
|
|
|
RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
|
2011-08-24 02:00:42 +02:00
|
|
|
rOFDM0_RxDetector3, priv->framesync);
|
|
|
|
priv->SifsTime = read_nic_word(dev, SIFS);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
2011-08-25 18:48:16 +02:00
|
|
|
u8 powerlevel = 0, powerlevelOFDM24G = 0;
|
2011-08-24 02:00:42 +02:00
|
|
|
char ant_pwr_diff;
|
|
|
|
u32 u4RegValue;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (priv->epromtype == EEPROM_93C46) {
|
2011-08-24 02:00:42 +02:00
|
|
|
powerlevel = priv->TxPowerLevelCCK[channel-1];
|
|
|
|
powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
|
2011-08-25 18:48:16 +02:00
|
|
|
} else if (priv->epromtype == EEPROM_93C56) {
|
|
|
|
if (priv->rf_type == RF_1T2R) {
|
2011-08-24 02:00:42 +02:00
|
|
|
powerlevel = priv->TxPowerLevelCCK_C[channel-1];
|
|
|
|
powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
|
2011-08-25 18:48:16 +02:00
|
|
|
} else if (priv->rf_type == RF_2T4R) {
|
2011-08-24 02:00:42 +02:00
|
|
|
powerlevel = priv->TxPowerLevelCCK_A[channel-1];
|
|
|
|
powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
|
|
|
|
|
|
|
|
ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
|
2011-08-25 18:48:16 +02:00
|
|
|
- priv->TxPowerLevelOFDM24G_A[channel-1];
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
priv->RF_C_TxPwDiff = ant_pwr_diff;
|
|
|
|
|
|
|
|
ant_pwr_diff &= 0xf;
|
|
|
|
|
|
|
|
priv->AntennaTxPwDiff[2] = 0;
|
|
|
|
priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
|
|
|
|
priv->AntennaTxPwDiff[0] = 0;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
u4RegValue = (priv->AntennaTxPwDiff[2]<<8 |
|
|
|
|
priv->AntennaTxPwDiff[1]<<4 |
|
|
|
|
priv->AntennaTxPwDiff[0]);
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
|
|
|
|
(bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
|
|
|
|
}
|
|
|
|
}
|
2011-07-11 01:56:20 +02:00
|
|
|
switch (priv->rf_chip) {
|
2011-08-24 02:00:42 +02:00
|
|
|
case RF_8225:
|
|
|
|
break;
|
|
|
|
case RF_8256:
|
|
|
|
PHY_SetRF8256CCKTxPower(dev, powerlevel);
|
|
|
|
PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
|
|
|
|
break;
|
|
|
|
case RF_8258:
|
|
|
|
break;
|
|
|
|
default:
|
2011-08-25 18:48:16 +02:00
|
|
|
RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n",
|
|
|
|
__func__);
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
bool rtl8192_phy_RFConfig(struct net_device *dev)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
|
|
|
bool rtStatus = true;
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (priv->rf_chip) {
|
|
|
|
case RF_8225:
|
|
|
|
break;
|
|
|
|
case RF_8256:
|
|
|
|
rtStatus = PHY_RF8256_Config(dev);
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
case RF_8258:
|
|
|
|
break;
|
|
|
|
case RF_PSEUDO_11N:
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
default:
|
|
|
|
RT_TRACE(COMP_ERR, "error chip id\n");
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
return rtStatus;
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
void rtl8192_phy_updateInitGain(struct net_device *dev)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
|
|
|
|
enum rf90_radio_path eRFPath)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
|
|
|
|
int i;
|
|
|
|
u8 ret = 0;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (eRFPath) {
|
|
|
|
case RF90_PATH_A:
|
|
|
|
for (i = 0; i < RadioA_ArrayLength; i += 2) {
|
|
|
|
if (Rtl819XRadioA_Array[i] == 0xfe) {
|
|
|
|
msleep(100);
|
|
|
|
continue;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_phy_SetRFReg(dev, eRFPath,
|
|
|
|
Rtl819XRadioA_Array[i],
|
|
|
|
bMask12Bits,
|
|
|
|
Rtl819XRadioA_Array[i+1]);
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RF90_PATH_B:
|
|
|
|
for (i = 0; i < RadioB_ArrayLength; i += 2) {
|
|
|
|
if (Rtl819XRadioB_Array[i] == 0xfe) {
|
|
|
|
msleep(100);
|
|
|
|
continue;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_phy_SetRFReg(dev, eRFPath,
|
|
|
|
Rtl819XRadioB_Array[i],
|
|
|
|
bMask12Bits,
|
|
|
|
Rtl819XRadioB_Array[i+1]);
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RF90_PATH_C:
|
|
|
|
for (i = 0; i < RadioC_ArrayLength; i += 2) {
|
|
|
|
if (Rtl819XRadioC_Array[i] == 0xfe) {
|
|
|
|
msleep(100);
|
|
|
|
continue;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_phy_SetRFReg(dev, eRFPath,
|
|
|
|
Rtl819XRadioC_Array[i],
|
|
|
|
bMask12Bits,
|
|
|
|
Rtl819XRadioC_Array[i+1]);
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RF90_PATH_D:
|
|
|
|
for (i = 0; i < RadioD_ArrayLength; i += 2) {
|
|
|
|
if (Rtl819XRadioD_Array[i] == 0xfe) {
|
|
|
|
msleep(100);
|
|
|
|
continue;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_phy_SetRFReg(dev, eRFPath,
|
|
|
|
Rtl819XRadioD_Array[i], bMask12Bits,
|
|
|
|
Rtl819XRadioD_Array[i+1]);
|
|
|
|
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
return ret;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
}
|
2011-08-25 21:07:05 +02:00
|
|
|
static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
|
|
|
u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
|
|
|
|
u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (priv->rf_chip) {
|
2011-08-24 02:00:42 +02:00
|
|
|
case RF_8225:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RF_8256:
|
|
|
|
PHY_SetRF8256CCKTxPower(dev, powerlevel);
|
|
|
|
PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RF_8258:
|
|
|
|
break;
|
|
|
|
default:
|
2011-08-25 18:48:16 +02:00
|
|
|
RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPower"
|
|
|
|
"Level()\n");
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
|
2011-08-25 21:07:05 +02:00
|
|
|
static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable,
|
|
|
|
u32 CmdTableIdx, u32 CmdTableSz,
|
|
|
|
enum sw_chnl_cmd_id CmdID,
|
|
|
|
u32 Para1, u32 Para2, u32 msDelay)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
2011-08-25 18:48:16 +02:00
|
|
|
struct sw_chnl_cmd *pCmd;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (CmdTable == NULL) {
|
|
|
|
RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot "
|
|
|
|
"be NULL.\n");
|
2011-08-24 02:00:42 +02:00
|
|
|
return false;
|
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
if (CmdTableIdx >= CmdTableSz) {
|
|
|
|
RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid"
|
|
|
|
" index, please check size of the table, CmdTableIdx:"
|
|
|
|
"%d, CmdTableSz:%d\n",
|
2011-08-24 02:00:42 +02:00
|
|
|
CmdTableIdx, CmdTableSz);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
pCmd = CmdTable + CmdTableIdx;
|
|
|
|
pCmd->CmdID = CmdID;
|
|
|
|
pCmd->Para1 = Para1;
|
|
|
|
pCmd->Para2 = Para2;
|
|
|
|
pCmd->msDelay = msDelay;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
|
2011-08-25 21:07:05 +02:00
|
|
|
static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
|
|
|
|
u8 *stage, u8 *step, u32 *delay)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
2011-07-19 06:12:54 +02:00
|
|
|
struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT];
|
2011-08-24 02:00:42 +02:00
|
|
|
u32 PreCommonCmdCnt;
|
2011-07-19 06:12:54 +02:00
|
|
|
struct sw_chnl_cmd PostCommonCmd[MAX_POSTCMD_CNT];
|
2011-08-24 02:00:42 +02:00
|
|
|
u32 PostCommonCmdCnt;
|
2011-07-19 06:12:54 +02:00
|
|
|
struct sw_chnl_cmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
|
2011-08-24 02:00:42 +02:00
|
|
|
u32 RfDependCmdCnt;
|
2011-07-19 06:12:54 +02:00
|
|
|
struct sw_chnl_cmd *CurrentCmd = NULL;
|
2011-08-24 02:00:42 +02:00
|
|
|
u8 eRFPath;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
|
|
|
|
__func__, *stage, *step, channel);
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (!IsLegalChannel(priv->rtllib, channel)) {
|
|
|
|
RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n",
|
|
|
|
channel);
|
2011-08-24 02:00:42 +02:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
{
|
|
|
|
PreCommonCmdCnt = 0;
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
|
|
|
|
MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
|
|
|
|
0, 0, 0);
|
|
|
|
rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
|
|
|
|
MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
PostCommonCmdCnt = 0;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
|
|
|
|
MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
RfDependCmdCnt = 0;
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (priv->rf_chip) {
|
2011-08-24 02:00:42 +02:00
|
|
|
case RF_8225:
|
2011-08-25 18:48:16 +02:00
|
|
|
if (!(channel >= 1 && channel <= 14)) {
|
|
|
|
RT_TRACE(COMP_ERR, "illegal channel for Zebra "
|
|
|
|
"8225: %d\n", channel);
|
2011-08-24 02:00:42 +02:00
|
|
|
return false;
|
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
|
|
|
|
RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
|
|
|
|
CmdID_RF_WriteReg, rZebra1_Channel,
|
|
|
|
RF_CHANNEL_TABLE_ZEBRA[channel], 10);
|
|
|
|
rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
|
|
|
|
RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
|
2011-08-24 02:00:42 +02:00
|
|
|
CmdID_End, 0, 0, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RF_8256:
|
2011-08-25 18:48:16 +02:00
|
|
|
if (!(channel >= 1 && channel <= 14)) {
|
|
|
|
RT_TRACE(COMP_ERR, "illegal channel for Zebra"
|
|
|
|
" 8256: %d\n", channel);
|
2011-08-24 02:00:42 +02:00
|
|
|
return false;
|
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
|
|
|
|
RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
|
|
|
|
CmdID_RF_WriteReg, rZebra1_Channel, channel,
|
|
|
|
10);
|
|
|
|
rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
|
|
|
|
RfDependCmdCnt++,
|
|
|
|
MAX_RFDEPENDCMD_CNT,
|
2011-08-24 02:00:42 +02:00
|
|
|
CmdID_End, 0, 0, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RF_8258:
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2011-08-25 18:48:16 +02:00
|
|
|
RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n",
|
|
|
|
priv->rf_chip);
|
2011-08-24 02:00:42 +02:00
|
|
|
return false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
do {
|
|
|
|
switch (*stage) {
|
2011-08-24 02:00:42 +02:00
|
|
|
case 0:
|
2011-08-25 18:48:16 +02:00
|
|
|
CurrentCmd = &PreCommonCmd[*step];
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
case 1:
|
2011-08-25 18:48:16 +02:00
|
|
|
CurrentCmd = &RfDependCmd[*step];
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2011-08-25 18:48:16 +02:00
|
|
|
CurrentCmd = &PostCommonCmd[*step];
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (CurrentCmd->CmdID == CmdID_End) {
|
|
|
|
if ((*stage) == 2) {
|
2011-08-24 02:00:42 +02:00
|
|
|
return true;
|
2011-08-25 18:48:16 +02:00
|
|
|
} else {
|
2011-08-24 02:00:42 +02:00
|
|
|
(*stage)++;
|
2011-08-25 18:48:16 +02:00
|
|
|
(*step) = 0;
|
2011-08-24 02:00:42 +02:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (CurrentCmd->CmdID) {
|
2011-08-24 02:00:42 +02:00
|
|
|
case CmdID_SetTxPowerLevel:
|
|
|
|
if (priv->IC_Cut > (u8)VERSION_8190_BD)
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_SetTxPowerLevel(dev, channel);
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
case CmdID_WritePortUlong:
|
2011-08-25 18:48:16 +02:00
|
|
|
write_nic_dword(dev, CurrentCmd->Para1,
|
|
|
|
CurrentCmd->Para2);
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
case CmdID_WritePortUshort:
|
2011-08-25 18:48:16 +02:00
|
|
|
write_nic_word(dev, CurrentCmd->Para1,
|
|
|
|
(u16)CurrentCmd->Para2);
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
case CmdID_WritePortUchar:
|
2011-08-25 18:48:16 +02:00
|
|
|
write_nic_byte(dev, CurrentCmd->Para1,
|
|
|
|
(u8)CurrentCmd->Para2);
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
case CmdID_RF_WriteReg:
|
2011-08-25 18:48:16 +02:00
|
|
|
for (eRFPath = 0; eRFPath <
|
|
|
|
priv->NumTotalRFPath; eRFPath++)
|
|
|
|
rtl8192_phy_SetRFReg(dev,
|
|
|
|
(enum rf90_radio_path)eRFPath,
|
|
|
|
CurrentCmd->Para1, bMask12Bits,
|
|
|
|
CurrentCmd->Para2<<7);
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
2011-08-25 18:48:16 +02:00
|
|
|
} while (true);
|
|
|
|
} /*for (Number of RF paths)*/
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
(*delay) = CurrentCmd->msDelay;
|
2011-08-24 02:00:42 +02:00
|
|
|
(*step)++;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2011-08-25 21:07:05 +02:00
|
|
|
static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
2011-08-25 18:48:16 +02:00
|
|
|
u32 delay = 0;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
|
|
|
|
&priv->SwChnlStep, &delay)) {
|
|
|
|
if (delay > 0)
|
2011-08-24 02:00:42 +02:00
|
|
|
msleep(delay);
|
|
|
|
if (IS_NIC_DOWN(priv))
|
2011-08-25 18:48:16 +02:00
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
void rtl8192_SwChnl_WorkItem(struct net_device *dev)
|
|
|
|
{
|
|
|
|
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
|
|
|
|
|
|
|
RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
|
|
|
|
priv->chan, priv);
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
|
|
|
|
|
|
|
|
RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
|
|
|
RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
|
2011-08-25 18:48:16 +02:00
|
|
|
if (IS_NIC_DOWN(priv)) {
|
|
|
|
RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__);
|
2011-08-24 02:00:42 +02:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (priv->SwChnlInProgress)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (priv->rtllib->mode) {
|
2011-08-24 02:00:42 +02:00
|
|
|
case WIRELESS_MODE_A:
|
|
|
|
case WIRELESS_MODE_N_5G:
|
2011-08-25 18:48:16 +02:00
|
|
|
if (channel <= 14) {
|
2011-08-24 02:00:42 +02:00
|
|
|
RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case WIRELESS_MODE_B:
|
2011-08-25 18:48:16 +02:00
|
|
|
if (channel > 14) {
|
2011-08-24 02:00:42 +02:00
|
|
|
RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case WIRELESS_MODE_G:
|
|
|
|
case WIRELESS_MODE_N_24G:
|
2011-08-25 18:48:16 +02:00
|
|
|
if (channel > 14) {
|
2011-08-24 02:00:42 +02:00
|
|
|
RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->SwChnlInProgress = true;
|
|
|
|
if (channel == 0)
|
|
|
|
channel = 1;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
priv->chan = channel;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
priv->SwChnlStage = 0;
|
|
|
|
priv->SwChnlStep = 0;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (!IS_NIC_DOWN(priv))
|
2011-08-24 02:00:42 +02:00
|
|
|
rtl8192_SwChnl_WorkItem(dev);
|
|
|
|
priv->SwChnlInProgress = false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (priv->CurrentChannelBW) {
|
|
|
|
case HT_CHANNEL_WIDTH_20:
|
|
|
|
priv->CCKPresentAttentuation =
|
|
|
|
priv->CCKPresentAttentuation_20Mdefault +
|
|
|
|
priv->CCKPresentAttentuation_difference;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (priv->CCKPresentAttentuation >
|
|
|
|
(CCKTxBBGainTableLength-1))
|
|
|
|
priv->CCKPresentAttentuation =
|
|
|
|
CCKTxBBGainTableLength-1;
|
|
|
|
if (priv->CCKPresentAttentuation < 0)
|
|
|
|
priv->CCKPresentAttentuation = 0;
|
|
|
|
|
|
|
|
RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresent"
|
|
|
|
"Attentuation = %d\n",
|
|
|
|
priv->CCKPresentAttentuation);
|
|
|
|
|
|
|
|
if (priv->rtllib->current_network.channel == 14 &&
|
|
|
|
!priv->bcck_in_ch14) {
|
|
|
|
priv->bcck_in_ch14 = true;
|
|
|
|
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
|
|
|
|
} else if (priv->rtllib->current_network.channel !=
|
|
|
|
14 && priv->bcck_in_ch14) {
|
|
|
|
priv->bcck_in_ch14 = false;
|
|
|
|
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
|
|
|
|
} else {
|
|
|
|
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
|
|
|
|
}
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
case HT_CHANNEL_WIDTH_20_40:
|
|
|
|
priv->CCKPresentAttentuation =
|
|
|
|
priv->CCKPresentAttentuation_40Mdefault +
|
|
|
|
priv->CCKPresentAttentuation_difference;
|
|
|
|
|
|
|
|
RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresent"
|
|
|
|
"Attentuation = %d\n",
|
|
|
|
priv->CCKPresentAttentuation);
|
|
|
|
if (priv->CCKPresentAttentuation >
|
|
|
|
(CCKTxBBGainTableLength - 1))
|
2011-08-24 02:00:42 +02:00
|
|
|
priv->CCKPresentAttentuation =
|
2011-08-25 18:48:16 +02:00
|
|
|
CCKTxBBGainTableLength-1;
|
|
|
|
if (priv->CCKPresentAttentuation < 0)
|
|
|
|
priv->CCKPresentAttentuation = 0;
|
|
|
|
|
|
|
|
if (priv->rtllib->current_network.channel == 14 &&
|
|
|
|
!priv->bcck_in_ch14) {
|
|
|
|
priv->bcck_in_ch14 = true;
|
|
|
|
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
|
|
|
|
} else if (priv->rtllib->current_network.channel != 14
|
|
|
|
&& priv->bcck_in_ch14) {
|
|
|
|
priv->bcck_in_ch14 = false;
|
|
|
|
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
|
|
|
|
} else {
|
|
|
|
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
|
|
|
|
}
|
2011-08-24 02:00:42 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
|
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (priv->rtllib->current_network.channel == 14 &&
|
|
|
|
!priv->bcck_in_ch14)
|
2011-08-24 02:00:42 +02:00
|
|
|
priv->bcck_in_ch14 = true;
|
2011-08-25 18:48:16 +02:00
|
|
|
else if (priv->rtllib->current_network.channel != 14 &&
|
|
|
|
priv->bcck_in_ch14)
|
2011-08-24 02:00:42 +02:00
|
|
|
priv->bcck_in_ch14 = false;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (priv->CurrentChannelBW) {
|
|
|
|
case HT_CHANNEL_WIDTH_20:
|
|
|
|
if (priv->Record_CCK_20Mindex == 0)
|
|
|
|
priv->Record_CCK_20Mindex = 6;
|
|
|
|
priv->CCK_index = priv->Record_CCK_20Mindex;
|
|
|
|
RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_"
|
|
|
|
"Switch_ThermalMeter(),CCK_index = %d\n",
|
|
|
|
priv->CCK_index);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HT_CHANNEL_WIDTH_20_40:
|
|
|
|
priv->CCK_index = priv->Record_CCK_40Mindex;
|
|
|
|
RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_"
|
|
|
|
"Switch_ThermalMeter(), CCK_index = %d\n",
|
|
|
|
priv->CCK_index);
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
|
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
|
|
|
|
|
|
|
if (priv->IC_Cut >= IC_VersionCut_D)
|
|
|
|
CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
|
|
|
|
else
|
|
|
|
CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
void rtl8192_SetBWModeWorkItem(struct net_device *dev)
|
|
|
|
{
|
|
|
|
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
|
|
|
u8 regBwOpMode;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s "
|
|
|
|
"bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
|
|
|
|
"20MHz" : "40MHz")
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (priv->rf_chip == RF_PSEUDO_11N) {
|
|
|
|
priv->SetBWModeInProgress = false;
|
2011-08-24 02:00:42 +02:00
|
|
|
return;
|
|
|
|
}
|
2011-08-25 18:48:16 +02:00
|
|
|
if (IS_NIC_DOWN(priv)) {
|
|
|
|
RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__);
|
2011-08-24 02:00:42 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
regBwOpMode = read_nic_byte(dev, BW_OPMODE);
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (priv->CurrentChannelBW) {
|
|
|
|
case HT_CHANNEL_WIDTH_20:
|
|
|
|
regBwOpMode |= BW_OPMODE_20MHZ;
|
|
|
|
write_nic_byte(dev, BW_OPMODE, regBwOpMode);
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
case HT_CHANNEL_WIDTH_20_40:
|
|
|
|
regBwOpMode &= ~BW_OPMODE_20MHZ;
|
|
|
|
write_nic_byte(dev, BW_OPMODE, regBwOpMode);
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
default:
|
|
|
|
RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
|
|
|
|
"Bandwidth: %#X\n", priv->CurrentChannelBW);
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (priv->CurrentChannelBW) {
|
|
|
|
case HT_CHANNEL_WIDTH_20:
|
|
|
|
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
|
|
|
|
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
|
|
|
|
|
|
|
|
if (!priv->btxpower_tracking) {
|
|
|
|
write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
|
|
|
|
write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
|
|
|
|
write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
|
|
|
|
} else {
|
|
|
|
CCK_Tx_Power_Track_BW_Switch(dev);
|
|
|
|
}
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
break;
|
|
|
|
case HT_CHANNEL_WIDTH_20_40:
|
|
|
|
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
|
|
|
|
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
|
|
|
|
|
|
|
|
if (!priv->btxpower_tracking) {
|
|
|
|
write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
|
|
|
|
write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
|
|
|
|
write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
|
|
|
|
} else {
|
|
|
|
CCK_Tx_Power_Track_BW_Switch(dev);
|
|
|
|
}
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
|
|
|
|
(priv->nCur40MhzPrimeSC>>1));
|
|
|
|
rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
|
|
|
|
priv->nCur40MhzPrimeSC);
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
|
|
|
|
"Bandwidth: %#X\n", priv->CurrentChannelBW);
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
switch (priv->rf_chip) {
|
|
|
|
case RF_8225:
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
case RF_8256:
|
|
|
|
PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
case RF_8258:
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
case RF_PSEUDO_11N:
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
default:
|
|
|
|
RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
2011-07-11 01:56:20 +02:00
|
|
|
|
2011-08-24 02:00:42 +02:00
|
|
|
atomic_dec(&(priv->rtllib->atm_swbw));
|
2011-08-25 18:48:16 +02:00
|
|
|
priv->SetBWModeInProgress = false;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth,
|
|
|
|
enum ht_extchnl_offset Offset)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
|
|
|
|
|
|
|
|
|
|
|
if (priv->SetBWModeInProgress)
|
|
|
|
return;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
atomic_inc(&(priv->rtllib->atm_swbw));
|
|
|
|
priv->SetBWModeInProgress = true;
|
2011-08-24 02:00:42 +02:00
|
|
|
|
|
|
|
priv->CurrentChannelBW = Bandwidth;
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
if (Offset == HT_EXTCHNL_OFFSET_LOWER)
|
2011-08-24 02:00:42 +02:00
|
|
|
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
|
2011-08-25 18:48:16 +02:00
|
|
|
else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
|
2011-08-24 02:00:42 +02:00
|
|
|
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
|
|
|
|
else
|
|
|
|
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
|
|
|
|
|
|
|
|
rtl8192_SetBWModeWorkItem(dev);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
void InitialGain819xPci(struct net_device *dev, u8 Operation)
|
|
|
|
{
|
|
|
|
#define SCAN_RX_INITIAL_GAIN 0x17
|
|
|
|
#define POWER_DETECTION_TH 0x08
|
|
|
|
struct r8192_priv *priv = rtllib_priv(dev);
|
2011-08-25 18:48:16 +02:00
|
|
|
u32 BitMask;
|
|
|
|
u8 initial_gain;
|
|
|
|
|
|
|
|
if (!IS_NIC_DOWN(priv)) {
|
|
|
|
switch (Operation) {
|
|
|
|
case IG_Backup:
|
|
|
|
RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial"
|
|
|
|
" gain.\n");
|
|
|
|
initial_gain = SCAN_RX_INITIAL_GAIN;
|
|
|
|
BitMask = bMaskByte0;
|
|
|
|
if (dm_digtable.dig_algorithm ==
|
|
|
|
DIG_ALGO_BY_FALSE_ALARM)
|
|
|
|
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
|
|
|
|
priv->initgain_backup.xaagccore1 =
|
|
|
|
(u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1,
|
|
|
|
BitMask);
|
|
|
|
priv->initgain_backup.xbagccore1 =
|
|
|
|
(u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1,
|
|
|
|
BitMask);
|
|
|
|
priv->initgain_backup.xcagccore1 =
|
|
|
|
(u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1,
|
|
|
|
BitMask);
|
|
|
|
priv->initgain_backup.xdagccore1 =
|
|
|
|
(u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1,
|
|
|
|
BitMask);
|
|
|
|
BitMask = bMaskByte2;
|
|
|
|
priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev,
|
|
|
|
rCCK0_CCA, BitMask);
|
|
|
|
|
|
|
|
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is"
|
|
|
|
" %x\n", priv->initgain_backup.xaagccore1);
|
|
|
|
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is"
|
|
|
|
" %x\n", priv->initgain_backup.xbagccore1);
|
|
|
|
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is"
|
|
|
|
" %x\n", priv->initgain_backup.xcagccore1);
|
|
|
|
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is"
|
|
|
|
" %x\n", priv->initgain_backup.xdagccore1);
|
|
|
|
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is"
|
|
|
|
" %x\n", priv->initgain_backup.cca);
|
|
|
|
|
|
|
|
RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
|
|
|
|
initial_gain);
|
|
|
|
write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
|
|
|
|
write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
|
|
|
|
write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
|
|
|
|
write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
|
|
|
|
RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
|
|
|
|
POWER_DETECTION_TH);
|
|
|
|
write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
|
|
|
|
break;
|
|
|
|
case IG_Restore:
|
|
|
|
RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial "
|
|
|
|
"gain.\n");
|
|
|
|
BitMask = 0x7f;
|
|
|
|
if (dm_digtable.dig_algorithm ==
|
|
|
|
DIG_ALGO_BY_FALSE_ALARM)
|
|
|
|
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
|
|
|
|
|
|
|
|
rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask,
|
|
|
|
(u32)priv->initgain_backup.xaagccore1);
|
|
|
|
rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask,
|
|
|
|
(u32)priv->initgain_backup.xbagccore1);
|
|
|
|
rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask,
|
|
|
|
(u32)priv->initgain_backup.xcagccore1);
|
|
|
|
rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask,
|
|
|
|
(u32)priv->initgain_backup.xdagccore1);
|
|
|
|
BitMask = bMaskByte2;
|
|
|
|
rtl8192_setBBreg(dev, rCCK0_CCA, BitMask,
|
|
|
|
(u32)priv->initgain_backup.cca);
|
|
|
|
|
|
|
|
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50"
|
|
|
|
" is %x\n", priv->initgain_backup.xaagccore1);
|
|
|
|
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58"
|
|
|
|
" is %x\n", priv->initgain_backup.xbagccore1);
|
|
|
|
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60"
|
|
|
|
" is %x\n", priv->initgain_backup.xcagccore1);
|
|
|
|
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68"
|
|
|
|
" is %x\n", priv->initgain_backup.xdagccore1);
|
|
|
|
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a"
|
|
|
|
" is %x\n", priv->initgain_backup.cca);
|
|
|
|
|
|
|
|
rtl8192_phy_setTxPower(dev,
|
|
|
|
priv->rtllib->current_network.channel);
|
|
|
|
|
|
|
|
if (dm_digtable.dig_algorithm ==
|
|
|
|
DIG_ALGO_BY_FALSE_ALARM)
|
|
|
|
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
|
|
|
|
break;
|
2011-08-24 02:00:42 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-25 18:48:16 +02:00
|
|
|
void PHY_SetRtl8192eRfOff(struct net_device *dev)
|
2011-08-24 02:00:42 +02:00
|
|
|
{
|
|
|
|
|
|
|
|
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
|
|
|
|
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
|
|
|
|
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
|
|
|
|
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
|
|
|
|
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
|
|
|
|
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
|
|
|
|
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
|
|
|
|
write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2011-08-25 21:07:05 +02:00
|
|
|
static bool SetRFPowerState8190(struct net_device *dev,
|
|
|
|
enum rt_rf_power_state eRFPowerState)
|
2011-08-24 02:00:42 +02:00
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{
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struct r8192_priv *priv = rtllib_priv(dev);
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2011-08-25 18:48:16 +02:00
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struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
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(&(priv->rtllib->PowerSaveControl));
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2011-08-24 02:00:42 +02:00
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bool bResult = true;
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u8 i = 0, QueueID = 0;
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struct rtl8192_tx_ring *ring = NULL;
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if (priv->SetRFPowerStateInProgress == true)
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return false;
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RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
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priv->SetRFPowerStateInProgress = true;
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2011-08-25 18:48:16 +02:00
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switch (priv->rf_chip) {
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case RF_8256:
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switch (eRFPowerState) {
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case eRfOn:
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RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n");
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if ((priv->rtllib->eRFPowerState == eRfOff) &&
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RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
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bool rtstatus = true;
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u32 InitilizeCount = 3;
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do {
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InitilizeCount--;
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priv->RegRfOff = false;
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rtstatus = NicIFEnableNIC(dev);
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} while ((rtstatus != true) &&
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(InitilizeCount > 0));
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if (rtstatus != true) {
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RT_TRACE(COMP_ERR, "%s():Initialize Ada"
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"pter fail,return\n",
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__func__);
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priv->SetRFPowerStateInProgress = false;
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return false;
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}
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RT_CLEAR_PS_LEVEL(pPSC,
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RT_RF_OFF_LEVL_HALT_NIC);
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} else {
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2011-08-24 02:00:42 +02:00
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write_nic_byte(dev, ANAPAR, 0x37);
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mdelay(1);
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2011-08-25 18:48:16 +02:00
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rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
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0x4, 0x1);
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2011-08-24 02:00:42 +02:00
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priv->bHwRfOffAction = 0;
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2011-08-25 18:48:16 +02:00
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rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE,
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BIT4, 0x1);
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rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4,
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0x300, 0x3);
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rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
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0x18, 0x3);
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rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3,
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0x3);
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rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3,
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0x3);
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rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
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0x60, 0x3);
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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}
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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break;
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case eRfSleep:
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if (priv->rtllib->eRFPowerState == eRfOff)
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break;
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
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ring = &priv->tx_ring[QueueID];
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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if (skb_queue_len(&ring->queue) == 0) {
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QueueID++;
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continue;
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} else {
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RT_TRACE((COMP_POWER|COMP_RF), "eRf Off"
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"/Sleep: %d times TcbBusyQueue"
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"[%d] !=0 before doze!\n",
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(i+1), QueueID);
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udelay(10);
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i++;
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2011-08-24 02:00:42 +02:00
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}
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2011-08-25 18:48:16 +02:00
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if (i >= MAX_DOZE_WAITING_TIMES_9x) {
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RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! "
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"SetRFPowerState8190(): eRfOff"
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": %d times TcbBusyQueue[%d] "
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"!= 0 !!!\n",
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MAX_DOZE_WAITING_TIMES_9x,
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QueueID);
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break;
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2011-08-24 02:00:42 +02:00
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}
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}
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2011-08-25 18:48:16 +02:00
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PHY_SetRtl8192eRfOff(dev);
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break;
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case eRfOff:
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RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/"
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"Sleep !\n");
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for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
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ring = &priv->tx_ring[QueueID];
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if (skb_queue_len(&ring->queue) == 0) {
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QueueID++;
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continue;
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} else {
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RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d"
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" times TcbBusyQueue[%d] !=0 b"
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"efore doze!\n", (i+1),
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QueueID);
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udelay(10);
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i++;
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2011-08-24 02:00:42 +02:00
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}
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2011-08-25 18:48:16 +02:00
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if (i >= MAX_DOZE_WAITING_TIMES_9x) {
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RT_TRACE(COMP_POWER, "\n\n\n SetZebra: "
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"RFPowerState8185B(): eRfOff:"
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" %d times TcbBusyQueue[%d] "
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"!= 0 !!!\n",
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MAX_DOZE_WAITING_TIMES_9x,
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QueueID);
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2011-08-24 02:00:42 +02:00
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break;
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2011-08-25 18:48:16 +02:00
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}
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}
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
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!RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
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NicIFDisableNIC(dev);
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RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
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} else if (!(pPSC->RegRfPsLevel &
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RT_RF_OFF_LEVL_HALT_NIC)) {
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PHY_SetRtl8192eRfOff(dev);
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}
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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break;
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2011-08-24 02:00:42 +02:00
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default:
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2011-08-25 18:48:16 +02:00
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bResult = false;
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RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state"
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" to set: 0x%X!!!\n", eRFPowerState);
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2011-08-24 02:00:42 +02:00
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break;
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2011-08-25 18:48:16 +02:00
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}
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break;
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default:
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RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
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break;
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2011-08-24 02:00:42 +02:00
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}
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if (bResult) {
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priv->rtllib->eRFPowerState = eRFPowerState;
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2011-07-13 05:08:32 +02:00
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switch (priv->rf_chip) {
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case RF_8256:
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2011-08-24 02:00:42 +02:00
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break;
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2011-07-13 05:08:32 +02:00
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default:
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2011-08-25 18:48:16 +02:00
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RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown "
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"RF type\n");
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2011-07-13 05:08:32 +02:00
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break;
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2011-08-24 02:00:42 +02:00
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}
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}
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priv->SetRFPowerStateInProgress = false;
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2011-08-25 18:48:16 +02:00
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RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n",
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bResult);
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2011-08-24 02:00:42 +02:00
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return bResult;
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}
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2011-08-25 18:48:16 +02:00
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bool SetRFPowerState(struct net_device *dev,
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enum rt_rf_power_state eRFPowerState)
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2011-08-24 02:00:42 +02:00
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{
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struct r8192_priv *priv = rtllib_priv(dev);
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bool bResult = false;
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2011-08-25 18:48:16 +02:00
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RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n",
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eRFPowerState);
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if (eRFPowerState == priv->rtllib->eRFPowerState &&
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priv->bHwRfOffAction == 0) {
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RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the "
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"request for eRFPowerState(%d) is the same.\n",
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eRFPowerState);
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2011-08-24 02:00:42 +02:00
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return bResult;
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}
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bResult = SetRFPowerState8190(dev, eRFPowerState);
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2011-08-25 18:48:16 +02:00
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RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n",
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bResult);
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2011-08-24 02:00:42 +02:00
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return bResult;
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}
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2011-08-25 21:07:05 +02:00
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void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation)
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2011-08-24 02:00:42 +02:00
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{
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struct r8192_priv *priv = rtllib_priv(dev);
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if (priv->up) {
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switch (Operation) {
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2011-08-25 18:48:16 +02:00
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case SCAN_OPT_BACKUP:
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priv->rtllib->InitialGainHandler(dev, IG_Backup);
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break;
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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case SCAN_OPT_RESTORE:
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priv->rtllib->InitialGainHandler(dev, IG_Restore);
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break;
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2011-08-24 02:00:42 +02:00
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2011-08-25 18:48:16 +02:00
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default:
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RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");
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break;
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2011-08-24 02:00:42 +02:00
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}
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}
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}
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