2009-05-28 22:23:52 +02:00
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/*
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* linux/arch/arm/mach-omap2/gpmc-onenand.c
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*
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* Copyright (C) 2006 - 2009 Nokia Corporation
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* Contacts: Juha Yrjola
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* Tony Lindgren
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2011-07-31 16:52:44 +02:00
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#include <linux/string.h>
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2009-05-28 22:23:52 +02:00
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/onenand_regs.h>
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#include <linux/io.h>
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2012-08-24 15:21:06 +02:00
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#include <linux/platform_data/mtd-onenand-omap2.h>
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2009-05-28 22:23:52 +02:00
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#include <asm/mach/flash.h>
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2009-10-20 18:40:47 +02:00
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#include <plat/gpmc.h>
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2009-05-28 22:23:52 +02:00
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2012-08-31 19:59:07 +02:00
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#include "soc.h"
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2012-08-30 21:53:23 +02:00
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#define ONENAND_IO_SIZE SZ_128K
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2009-05-28 22:23:52 +02:00
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static struct omap_onenand_platform_data *gpmc_onenand_data;
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2012-08-30 21:53:23 +02:00
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static struct resource gpmc_onenand_resource = {
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.flags = IORESOURCE_MEM,
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};
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2009-05-28 22:23:52 +02:00
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static struct platform_device gpmc_onenand_device = {
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.name = "omap2-onenand",
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.id = -1,
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2012-08-30 21:53:23 +02:00
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.num_resources = 1,
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.resource = &gpmc_onenand_resource,
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2009-05-28 22:23:52 +02:00
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};
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static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
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{
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struct gpmc_timings t;
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2009-06-23 12:30:24 +02:00
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u32 reg;
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int err;
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2009-05-28 22:23:52 +02:00
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const int t_cer = 15;
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const int t_avdp = 12;
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const int t_aavdh = 7;
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const int t_ce = 76;
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const int t_aa = 76;
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const int t_oe = 20;
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const int t_cez = 20; /* max of t_cez, t_oez */
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const int t_ds = 30;
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const int t_wpl = 40;
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const int t_wph = 30;
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2009-06-23 12:30:24 +02:00
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/* Ensure sync read and sync write are disabled */
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reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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2009-05-28 22:23:52 +02:00
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memset(&t, 0, sizeof(t));
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t.sync_clk = 0;
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t.cs_on = 0;
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t.adv_on = 0;
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/* Read */
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t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
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t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
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t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
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t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
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t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
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t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
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t.cs_rd_off = t.oe_off;
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t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
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/* Write */
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t.adv_wr_off = t.adv_rd_off;
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t.we_on = t.oe_on;
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if (cpu_is_omap34xx()) {
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t.wr_data_mux_bus = t.we_on;
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t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
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}
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t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
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t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
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t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
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/* Configure GPMC for asynchronous read */
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
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GPMC_CONFIG1_DEVICESIZE_16 |
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GPMC_CONFIG1_MUXADDDATA);
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2009-06-23 12:30:24 +02:00
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err = gpmc_cs_set_timings(cs, &t);
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if (err)
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return err;
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/* Ensure sync read and sync write are disabled */
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reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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return 0;
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2009-05-28 22:23:52 +02:00
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}
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static void set_onenand_cfg(void __iomem *onenand_base, int latency,
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2011-02-07 09:46:58 +01:00
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int sync_read, int sync_write, int hf, int vhf)
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2009-05-28 22:23:52 +02:00
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{
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u32 reg;
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reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
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reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
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reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
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ONENAND_SYS_CFG1_BL_16;
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if (sync_read)
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reg |= ONENAND_SYS_CFG1_SYNC_READ;
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else
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
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if (sync_write)
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reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
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else
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reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
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if (hf)
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reg |= ONENAND_SYS_CFG1_HF;
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else
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reg &= ~ONENAND_SYS_CFG1_HF;
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2011-02-07 09:46:58 +01:00
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if (vhf)
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reg |= ONENAND_SYS_CFG1_VHF;
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else
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reg &= ~ONENAND_SYS_CFG1_VHF;
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2009-05-28 22:23:52 +02:00
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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}
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2011-02-07 09:47:00 +01:00
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static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
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void __iomem *onenand_base, bool *clk_dep)
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{
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u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
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int freq = 0;
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if (cfg->get_freq) {
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struct onenand_freq_info fi;
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fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
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fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
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fi.ver_id = ver;
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freq = cfg->get_freq(&fi, clk_dep);
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if (freq)
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return freq;
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}
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switch ((ver >> 4) & 0xf) {
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case 0:
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freq = 40;
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break;
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case 1:
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freq = 54;
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break;
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case 2:
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freq = 66;
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break;
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case 3:
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freq = 83;
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break;
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case 4:
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freq = 104;
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break;
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default:
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freq = 54;
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break;
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}
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return freq;
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}
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2009-05-28 22:23:52 +02:00
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static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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void __iomem *onenand_base,
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2011-02-07 09:46:59 +01:00
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int *freq_ptr)
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2009-05-28 22:23:52 +02:00
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{
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struct gpmc_timings t;
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const int t_cer = 15;
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const int t_avdp = 12;
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const int t_cez = 20; /* max of t_cez, t_oez */
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const int t_ds = 30;
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const int t_wpl = 40;
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const int t_wph = 30;
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int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
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2012-04-13 14:34:32 +02:00
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int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
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2011-02-07 09:46:58 +01:00
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int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
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2009-05-28 22:23:52 +02:00
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int err, ticks_cez;
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2011-02-07 09:46:59 +01:00
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int cs = cfg->cs, freq = *freq_ptr;
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2009-05-28 22:23:52 +02:00
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u32 reg;
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2011-02-07 09:47:00 +01:00
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bool clk_dep = false;
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2009-05-28 22:23:52 +02:00
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if (cfg->flags & ONENAND_SYNC_READ) {
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sync_read = 1;
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} else if (cfg->flags & ONENAND_SYNC_READWRITE) {
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sync_read = 1;
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sync_write = 1;
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2009-06-23 12:30:24 +02:00
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} else
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return omap2_onenand_set_async_mode(cs, onenand_base);
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2009-05-28 22:23:52 +02:00
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if (!freq) {
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/* Very first call freq is not known */
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err = omap2_onenand_set_async_mode(cs, onenand_base);
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if (err)
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return err;
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2011-02-07 09:47:00 +01:00
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freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
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2009-05-28 22:23:52 +02:00
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first_time = 1;
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}
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switch (freq) {
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2010-12-09 10:22:50 +01:00
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case 104:
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min_gpmc_clk_period = 9600; /* 104 MHz */
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t_ces = 3;
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t_avds = 4;
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t_avdh = 2;
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t_ach = 3;
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t_aavdh = 6;
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2011-02-07 09:46:58 +01:00
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t_rdyo = 6;
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2010-12-09 10:22:50 +01:00
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break;
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2009-05-28 22:23:52 +02:00
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case 83:
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2010-12-09 09:48:27 +01:00
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min_gpmc_clk_period = 12000; /* 83 MHz */
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2009-05-28 22:23:52 +02:00
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t_ces = 5;
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t_avds = 4;
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t_avdh = 2;
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t_ach = 6;
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t_aavdh = 6;
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t_rdyo = 9;
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break;
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case 66:
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2010-12-09 09:48:27 +01:00
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min_gpmc_clk_period = 15000; /* 66 MHz */
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2009-05-28 22:23:52 +02:00
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t_ces = 6;
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t_avds = 5;
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t_avdh = 2;
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t_ach = 6;
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t_aavdh = 6;
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t_rdyo = 11;
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break;
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default:
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2010-12-09 09:48:27 +01:00
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min_gpmc_clk_period = 18500; /* 54 MHz */
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2009-05-28 22:23:52 +02:00
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t_ces = 7;
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t_avds = 7;
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t_avdh = 7;
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t_ach = 9;
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t_aavdh = 7;
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t_rdyo = 15;
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sync_write = 0;
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break;
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}
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div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
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gpmc_clk_ns = gpmc_ticks_to_ns(div);
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if (gpmc_clk_ns < 15) /* >66Mhz */
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hf = 1;
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2011-02-07 09:46:58 +01:00
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if (gpmc_clk_ns < 12) /* >83Mhz */
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vhf = 1;
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if (vhf)
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latency = 8;
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else if (hf)
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2009-05-28 22:23:52 +02:00
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latency = 6;
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else if (gpmc_clk_ns >= 25) /* 40 MHz*/
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latency = 3;
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else
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latency = 4;
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2011-02-07 09:47:00 +01:00
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if (clk_dep) {
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if (gpmc_clk_ns < 12) { /* >83Mhz */
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t_ces = 3;
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t_avds = 4;
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} else if (gpmc_clk_ns < 15) { /* >66Mhz */
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t_ces = 5;
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t_avds = 4;
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} else if (gpmc_clk_ns < 25) { /* >40Mhz */
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t_ces = 6;
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t_avds = 5;
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} else {
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t_ces = 7;
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t_avds = 7;
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}
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}
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2009-05-28 22:23:52 +02:00
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if (first_time)
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set_onenand_cfg(onenand_base, latency,
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2011-02-07 09:46:58 +01:00
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sync_read, sync_write, hf, vhf);
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2009-05-28 22:23:52 +02:00
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if (div == 1) {
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reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
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reg |= (1 << 7);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
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reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
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reg |= (1 << 7);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
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reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
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reg |= (1 << 7);
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reg |= (1 << 23);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
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} else {
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reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
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reg &= ~(1 << 7);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
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reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
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reg &= ~(1 << 7);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
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reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
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reg &= ~(1 << 7);
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reg &= ~(1 << 23);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
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}
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/* Set synchronous read timings */
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memset(&t, 0, sizeof(t));
|
|
|
|
t.sync_clk = min_gpmc_clk_period;
|
|
|
|
t.cs_on = 0;
|
|
|
|
t.adv_on = 0;
|
|
|
|
fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
|
|
|
|
fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
|
|
|
|
t.page_burst_access = gpmc_clk_ns;
|
|
|
|
|
|
|
|
/* Read */
|
|
|
|
t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
|
|
|
|
t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
|
2011-02-07 09:46:58 +01:00
|
|
|
/* Force at least 1 clk between AVD High to OE Low */
|
|
|
|
if (t.oe_on <= t.adv_rd_off)
|
|
|
|
t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
|
2009-05-28 22:23:52 +02:00
|
|
|
t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
|
|
|
|
t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
|
|
|
|
t.cs_rd_off = t.oe_off;
|
|
|
|
ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;
|
|
|
|
t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
|
|
|
|
ticks_cez);
|
|
|
|
|
|
|
|
/* Write */
|
|
|
|
if (sync_write) {
|
|
|
|
t.adv_wr_off = t.adv_rd_off;
|
|
|
|
t.we_on = 0;
|
|
|
|
t.we_off = t.cs_rd_off;
|
|
|
|
t.cs_wr_off = t.cs_rd_off;
|
|
|
|
t.wr_cycle = t.rd_cycle;
|
|
|
|
if (cpu_is_omap34xx()) {
|
|
|
|
t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
|
2010-12-09 09:48:27 +01:00
|
|
|
gpmc_ps_to_ticks(min_gpmc_clk_period +
|
|
|
|
t_rdyo * 1000));
|
2009-05-28 22:23:52 +02:00
|
|
|
t.wr_access = t.access;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int,
|
|
|
|
t_avdp, t_cer));
|
|
|
|
t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);
|
|
|
|
t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
|
|
|
|
t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
|
|
|
|
t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
|
|
|
|
if (cpu_is_omap34xx()) {
|
|
|
|
t.wr_data_mux_bus = t.we_on;
|
|
|
|
t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Configure GPMC for synchronous read */
|
|
|
|
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
|
|
|
|
GPMC_CONFIG1_WRAPBURST_SUPP |
|
|
|
|
GPMC_CONFIG1_READMULTIPLE_SUPP |
|
|
|
|
(sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
|
|
|
|
(sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
|
|
|
|
(sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
|
|
|
|
GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
|
|
|
|
GPMC_CONFIG1_PAGE_LEN(2) |
|
|
|
|
(cpu_is_omap34xx() ? 0 :
|
|
|
|
(GPMC_CONFIG1_WAIT_READ_MON |
|
|
|
|
GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
|
|
|
|
GPMC_CONFIG1_DEVICESIZE_16 |
|
|
|
|
GPMC_CONFIG1_DEVICETYPE_NOR |
|
|
|
|
GPMC_CONFIG1_MUXADDDATA);
|
|
|
|
|
|
|
|
err = gpmc_cs_set_timings(cs, &t);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2011-02-07 09:46:58 +01:00
|
|
|
set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
|
2009-05-28 22:23:52 +02:00
|
|
|
|
2011-02-07 09:46:59 +01:00
|
|
|
*freq_ptr = freq;
|
|
|
|
|
2009-05-28 22:23:52 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-02-07 09:46:59 +01:00
|
|
|
static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
|
2009-05-28 22:23:52 +02:00
|
|
|
{
|
|
|
|
struct device *dev = &gpmc_onenand_device.dev;
|
|
|
|
|
|
|
|
/* Set sync timings in GPMC */
|
|
|
|
if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
|
2011-02-07 09:46:59 +01:00
|
|
|
freq_ptr) < 0) {
|
2009-05-28 22:23:52 +02:00
|
|
|
dev_err(dev, "Unable to set synchronous mode\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
|
|
|
|
{
|
2012-08-30 21:53:23 +02:00
|
|
|
int err;
|
|
|
|
|
2009-05-28 22:23:52 +02:00
|
|
|
gpmc_onenand_data = _onenand_data;
|
|
|
|
gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
|
|
|
|
gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
|
|
|
|
|
|
|
|
if (cpu_is_omap24xx() &&
|
|
|
|
(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
|
|
|
|
printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
|
|
|
|
gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
|
|
|
|
gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
|
|
|
|
}
|
|
|
|
|
2012-08-30 21:53:23 +02:00
|
|
|
err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
|
|
|
|
(unsigned long *)&gpmc_onenand_resource.start);
|
|
|
|
if (err < 0) {
|
|
|
|
pr_err("%s: Cannot request GPMC CS\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
gpmc_onenand_resource.end = gpmc_onenand_resource.start +
|
|
|
|
ONENAND_IO_SIZE - 1;
|
|
|
|
|
2009-05-28 22:23:52 +02:00
|
|
|
if (platform_device_register(&gpmc_onenand_device) < 0) {
|
2012-08-30 21:53:23 +02:00
|
|
|
pr_err("%s: Unable to register OneNAND device\n", __func__);
|
|
|
|
gpmc_cs_free(gpmc_onenand_data->cs);
|
2009-05-28 22:23:52 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|