2010-05-12 17:54:36 +02:00
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/*
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* Hardware modules present on the OMAP44xx chips
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*
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2012-04-19 12:04:31 +02:00
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* Copyright (C) 2009-2012 Texas Instruments, Inc.
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2010-05-12 17:54:36 +02:00
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* Copyright (C) 2009-2010 Nokia Corporation
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*
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* Paul Walmsley
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* Benoit Cousson
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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2012-08-31 00:37:24 +02:00
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#include <linux/platform_data/gpio-omap.h>
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2012-04-25 12:36:20 +02:00
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#include <linux/power/smartreflex.h>
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2012-10-27 15:35:55 +02:00
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#include <linux/platform_data/omap_ocp2scp.h>
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2010-05-12 17:54:36 +02:00
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#include <plat/omap_hwmod.h>
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2011-07-10 13:27:16 +02:00
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#include <plat/i2c.h>
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2010-12-21 03:27:19 +01:00
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#include <plat/dma.h>
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2012-08-24 15:21:06 +02:00
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#include <linux/platform_data/spi-omap2-mcspi.h>
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#include <linux/platform_data/asoc-ti-mcbsp.h>
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2011-03-01 22:12:56 +01:00
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#include <plat/mmc.h>
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2011-09-20 13:30:18 +02:00
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#include <plat/dmtimer.h>
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2011-11-08 11:16:13 +01:00
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#include <plat/common.h>
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2012-09-24 01:28:24 +02:00
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#include <plat/iommu.h>
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2010-05-12 17:54:36 +02:00
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#include "omap_hwmod_common_data.h"
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2010-12-21 23:30:54 +01:00
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#include "cm1_44xx.h"
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#include "cm2_44xx.h"
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#include "prm44xx.h"
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2010-05-12 17:54:36 +02:00
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#include "prm-regbits-44xx.h"
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OMAP2+: wd_timer: disable on boot via hwmod postsetup mechanism
The OMAP watchdog timer IP blocks require a specific set of register
writes to occur before they will be disabled[1], even if the device
clocks appear to be disabled in the CM_*CLKEN registers. In the MPU
watchdog case, failure to execute this reset sequence will eventually
cause the watchdog to reset the OMAP unexpectedly.
Previously, the code to disable this watchdog was manually called from
mach-omap2/devices.c during device initialization. This causes the
watchdog to be unconditionally disabled for a portion of kernel
initialization. This should be controllable by the board-*.c files,
since some system integrators will want full watchdog coverage of
kernel initialization. Also, the watchdog disable code was not
connected to the hwmod shutdown code. This means that calling
omap_hwmod_shutdown() will not, in fact, disable the watchdog, and the
goal of omap_hwmod_shutdown() is to be able to shutdown any on-chip
OMAP device.
To resolve the latter problem, populate the pre_shutdown pointer in
the watchdog timer hwmod classes with a function that executes the
watchdog shutdown sequence. This allows the hwmod code to fully
disable the watchdog.
Then, to allow some board files to support watchdog coverage
throughout kernel initialization, add common code to mach-omap2/io.c
to cause the MPU watchdog to be disabled on boot unless a board file
specifically requests it to remain enabled. Board files can do this
by changing the watchdog timer hwmod's postsetup state between the
omap2_init_common_infrastructure() and omap2_init_common_devices()
function calls.
1. OMAP34xx Multimedia Device Silicon Revision 3.1.x Rev. ZH
[SWPU222H], Section 16.4.3.6, "Start/Stop Sequence for WDTs (Using
WDTi.WSPR Register)"
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Charulatha Varadarajan <charu@ti.com>
2010-12-21 23:39:15 +01:00
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#include "wd_timer.h"
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2010-05-12 17:54:36 +02:00
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/* Base offset for all OMAP4 interrupts external to MPUSS */
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#define OMAP44XX_IRQ_GIC_START 32
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/* Base offset for all OMAP4 dma requests */
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2012-04-19 12:04:33 +02:00
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#define OMAP44XX_DMA_REQ_START 1
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2010-05-12 17:54:36 +02:00
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/*
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2012-04-19 12:04:33 +02:00
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* IP blocks
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2010-05-12 17:54:36 +02:00
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*/
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2012-04-19 21:33:54 +02:00
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/*
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* 'c2c_target_fw' class
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* instance(s): c2c_target_fw
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*/
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static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
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.name = "c2c_target_fw",
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};
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/* c2c_target_fw */
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static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
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.name = "c2c_target_fw",
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.class = &omap44xx_c2c_target_fw_hwmod_class,
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.clkdm_name = "d2d_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
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},
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},
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};
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2010-05-12 17:54:36 +02:00
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/*
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* 'dmm' class
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* instance(s): dmm
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*/
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static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
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2010-12-23 23:30:32 +01:00
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.name = "dmm",
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2010-05-12 17:54:36 +02:00
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};
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2011-07-10 03:14:28 +02:00
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/* dmm */
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static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
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{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
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{ .irq = -1 }
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};
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2010-05-12 17:54:36 +02:00
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static struct omap_hwmod omap44xx_dmm_hwmod = {
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.name = "dmm",
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.class = &omap44xx_dmm_hwmod_class,
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2011-07-10 13:56:29 +02:00
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.clkdm_name = "l3_emif_clkdm",
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2012-04-19 12:04:33 +02:00
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.mpu_irqs = omap44xx_dmm_irqs,
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2011-07-10 13:56:30 +02:00
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
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2011-07-10 13:56:32 +02:00
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.context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
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2011-07-10 13:56:30 +02:00
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},
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},
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2010-05-12 17:54:36 +02:00
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};
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/*
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* 'emif_fw' class
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* instance(s): emif_fw
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*/
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static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
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2010-12-23 23:30:32 +01:00
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.name = "emif_fw",
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2010-05-12 17:54:36 +02:00
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};
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2011-07-10 03:14:28 +02:00
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/* emif_fw */
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2010-05-12 17:54:36 +02:00
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static struct omap_hwmod omap44xx_emif_fw_hwmod = {
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.name = "emif_fw",
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.class = &omap44xx_emif_fw_hwmod_class,
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2011-07-10 13:56:29 +02:00
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.clkdm_name = "l3_emif_clkdm",
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2011-07-10 13:56:30 +02:00
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
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2011-07-10 13:56:32 +02:00
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.context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
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2011-07-10 13:56:30 +02:00
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},
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},
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2010-05-12 17:54:36 +02:00
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};
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/*
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* 'l3' class
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* instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
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*/
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static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
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2010-12-23 23:30:32 +01:00
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.name = "l3",
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2010-05-12 17:54:36 +02:00
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};
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2011-07-10 03:14:28 +02:00
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/* l3_instr */
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2010-05-12 17:54:36 +02:00
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static struct omap_hwmod omap44xx_l3_instr_hwmod = {
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.name = "l3_instr",
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.class = &omap44xx_l3_hwmod_class,
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2011-07-10 13:56:29 +02:00
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.clkdm_name = "l3_instr_clkdm",
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2011-07-10 13:56:30 +02:00
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
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2011-07-10 13:56:32 +02:00
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.context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
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2011-07-10 13:56:32 +02:00
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.modulemode = MODULEMODE_HWCTRL,
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2011-07-10 13:56:30 +02:00
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},
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},
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2010-05-12 17:54:36 +02:00
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};
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2011-07-10 03:14:28 +02:00
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/* l3_main_1 */
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2011-07-10 03:14:27 +02:00
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static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
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{ .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
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{ .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
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{ .irq = -1 }
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};
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2010-05-12 17:54:36 +02:00
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static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
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.name = "l3_main_1",
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.class = &omap44xx_l3_hwmod_class,
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2011-07-10 13:56:29 +02:00
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.clkdm_name = "l3_1_clkdm",
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2011-07-10 03:14:28 +02:00
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.mpu_irqs = omap44xx_l3_main_1_irqs,
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2011-07-10 13:56:30 +02:00
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
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2011-07-10 13:56:32 +02:00
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.context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
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2011-07-10 13:56:30 +02:00
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},
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},
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2010-05-12 17:54:36 +02:00
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};
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2011-07-10 03:14:28 +02:00
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/* l3_main_2 */
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2010-05-12 17:54:36 +02:00
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static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
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.name = "l3_main_2",
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.class = &omap44xx_l3_hwmod_class,
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2011-07-10 13:56:29 +02:00
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.clkdm_name = "l3_2_clkdm",
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2011-07-10 13:56:30 +02:00
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
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2011-07-10 13:56:32 +02:00
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.context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
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2011-07-10 13:56:30 +02:00
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},
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},
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2010-05-12 17:54:36 +02:00
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};
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2011-07-10 03:14:28 +02:00
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/* l3_main_3 */
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2010-05-12 17:54:36 +02:00
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static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
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.name = "l3_main_3",
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.class = &omap44xx_l3_hwmod_class,
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2011-07-10 13:56:29 +02:00
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.clkdm_name = "l3_instr_clkdm",
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2011-07-10 13:56:30 +02:00
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
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2011-07-10 13:56:32 +02:00
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.context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
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2011-07-10 13:56:32 +02:00
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.modulemode = MODULEMODE_HWCTRL,
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2011-07-10 13:56:30 +02:00
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},
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},
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2010-05-12 17:54:36 +02:00
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};
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/*
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* 'l4' class
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* instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
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*/
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static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
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2010-12-23 23:30:32 +01:00
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.name = "l4",
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2010-05-12 17:54:36 +02:00
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};
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2011-07-10 03:14:28 +02:00
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/* l4_abe */
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2010-05-12 17:54:36 +02:00
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static struct omap_hwmod omap44xx_l4_abe_hwmod = {
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.name = "l4_abe",
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.class = &omap44xx_l4_hwmod_class,
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2011-07-10 13:56:29 +02:00
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.clkdm_name = "abe_clkdm",
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2011-07-10 13:56:30 +02:00
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
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2012-09-24 01:28:19 +02:00
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.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
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.lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
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2012-09-24 01:28:20 +02:00
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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2011-07-10 13:56:30 +02:00
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},
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},
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2010-05-12 17:54:36 +02:00
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};
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2011-07-10 03:14:28 +02:00
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/* l4_cfg */
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2010-05-12 17:54:36 +02:00
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static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
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.name = "l4_cfg",
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.class = &omap44xx_l4_hwmod_class,
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2011-07-10 13:56:29 +02:00
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.clkdm_name = "l4_cfg_clkdm",
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2011-07-10 13:56:30 +02:00
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
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2011-07-10 13:56:32 +02:00
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.context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
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2011-07-10 13:56:30 +02:00
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},
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},
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2010-05-12 17:54:36 +02:00
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};
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2011-07-10 03:14:28 +02:00
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/* l4_per */
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2010-05-12 17:54:36 +02:00
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static struct omap_hwmod omap44xx_l4_per_hwmod = {
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.name = "l4_per",
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.class = &omap44xx_l4_hwmod_class,
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2011-07-10 13:56:29 +02:00
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.clkdm_name = "l4_per_clkdm",
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2011-07-10 13:56:30 +02:00
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
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2011-07-10 13:56:32 +02:00
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.context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
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2011-07-10 13:56:30 +02:00
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},
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},
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2010-05-12 17:54:36 +02:00
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};
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2011-07-10 03:14:28 +02:00
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/* l4_wkup */
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2010-05-12 17:54:36 +02:00
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static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
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.name = "l4_wkup",
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.class = &omap44xx_l4_hwmod_class,
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2011-07-10 13:56:29 +02:00
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.clkdm_name = "l4_wkup_clkdm",
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2011-07-10 13:56:30 +02:00
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
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2011-07-10 13:56:32 +02:00
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|
|
.context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
|
2011-07-10 13:56:30 +02:00
|
|
|
},
|
|
|
|
},
|
2010-05-12 17:54:36 +02:00
|
|
|
};
|
|
|
|
|
2010-09-21 16:07:14 +02:00
|
|
|
/*
|
2010-12-22 05:08:33 +01:00
|
|
|
* 'mpu_bus' class
|
|
|
|
* instance(s): mpu_private
|
2010-09-21 16:07:14 +02:00
|
|
|
*/
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
|
2010-12-23 23:30:32 +01:00
|
|
|
.name = "mpu_bus",
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
2010-09-21 16:07:14 +02:00
|
|
|
|
2011-07-10 03:14:28 +02:00
|
|
|
/* mpu_private */
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod omap44xx_mpu_private_hwmod = {
|
|
|
|
.name = "mpu_private",
|
|
|
|
.class = &omap44xx_mpu_bus_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "mpuss_clkdm",
|
2012-09-24 01:28:20 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
|
},
|
|
|
|
},
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:56 +02:00
|
|
|
/*
|
|
|
|
* 'ocp_wp_noc' class
|
|
|
|
* instance(s): ocp_wp_noc
|
|
|
|
*/
|
|
|
|
static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
|
|
|
|
.name = "ocp_wp_noc",
|
|
|
|
};
|
|
|
|
|
|
|
|
/* ocp_wp_noc */
|
|
|
|
static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
|
|
|
|
.name = "ocp_wp_noc",
|
|
|
|
.class = &omap44xx_ocp_wp_noc_hwmod_class,
|
|
|
|
.clkdm_name = "l3_instr_clkdm",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/*
|
|
|
|
* Modules omap_hwmod structures
|
|
|
|
*
|
|
|
|
* The following IPs are excluded for the moment because:
|
|
|
|
* - They do not need an explicit SW control using omap_hwmod API.
|
|
|
|
* - They still need to be validated with the driver
|
|
|
|
* properly adapted to omap_hwmod / omap_device
|
|
|
|
*
|
2012-04-19 21:33:59 +02:00
|
|
|
* usim
|
2010-12-22 05:08:33 +01:00
|
|
|
*/
|
|
|
|
|
2011-02-15 22:39:48 +01:00
|
|
|
/*
|
|
|
|
* 'aess' class
|
|
|
|
* audio engine sub system
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
2011-07-01 22:54:01 +02:00
|
|
|
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
|
|
|
|
MSTANDBY_SMART_WKUP),
|
2011-02-15 22:39:48 +01:00
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
|
|
|
|
.name = "aess",
|
|
|
|
.sysc = &omap44xx_aess_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* aess */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
|
|
|
|
{ .irq = 99 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
|
|
|
|
{ .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_aess_hwmod = {
|
|
|
|
.name = "aess",
|
|
|
|
.class = &omap44xx_aess_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_aess_irqs,
|
|
|
|
.sdma_reqs = omap44xx_aess_sdma_reqs,
|
|
|
|
.main_clk = "aess_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
|
2012-09-24 01:28:19 +02:00
|
|
|
.lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
/*
|
|
|
|
* 'c2c' class
|
|
|
|
* chip 2 chip interface used to plug the ape soc (omap) with an external modem
|
|
|
|
* soc
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
|
|
|
|
.name = "c2c",
|
|
|
|
};
|
|
|
|
|
|
|
|
/* c2c */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
|
|
|
|
{ .irq = 88 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
|
|
|
|
{ .dma_req = 68 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .dma_req = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_c2c_hwmod = {
|
|
|
|
.name = "c2c",
|
|
|
|
.class = &omap44xx_c2c_hwmod_class,
|
|
|
|
.clkdm_name = "d2d_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_c2c_irqs,
|
|
|
|
.sdma_reqs = omap44xx_c2c_sdma_reqs,
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-02-15 22:39:48 +01:00
|
|
|
/*
|
|
|
|
* 'counter' class
|
|
|
|
* 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0004,
|
|
|
|
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
2012-06-17 19:57:51 +02:00
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO),
|
2011-02-15 22:39:48 +01:00
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
|
|
|
|
.name = "counter",
|
|
|
|
.sysc = &omap44xx_counter_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* counter_32k */
|
|
|
|
static struct omap_hwmod omap44xx_counter_32k_hwmod = {
|
|
|
|
.name = "counter_32k",
|
|
|
|
.class = &omap44xx_counter_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_wkup_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.flags = HWMOD_SWSUP_SIDLE,
|
|
|
|
.main_clk = "sys_32k_ck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:57 +02:00
|
|
|
/*
|
|
|
|
* 'ctrl_module' class
|
|
|
|
* attila core control module + core pad control module + wkup pad control
|
|
|
|
* module + attila wkup control module
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
|
|
|
|
.name = "ctrl_module",
|
|
|
|
.sysc = &omap44xx_ctrl_module_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* ctrl_module_core */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
|
|
|
|
{ .irq = 8 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
|
|
|
|
.name = "ctrl_module_core",
|
|
|
|
.class = &omap44xx_ctrl_module_hwmod_class,
|
|
|
|
.clkdm_name = "l4_cfg_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_ctrl_module_core_irqs,
|
2012-09-24 01:28:20 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
|
},
|
|
|
|
},
|
2012-04-19 21:33:57 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* ctrl_module_pad_core */
|
|
|
|
static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
|
|
|
|
.name = "ctrl_module_pad_core",
|
|
|
|
.class = &omap44xx_ctrl_module_hwmod_class,
|
|
|
|
.clkdm_name = "l4_cfg_clkdm",
|
2012-09-24 01:28:20 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
|
},
|
|
|
|
},
|
2012-04-19 21:33:57 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* ctrl_module_wkup */
|
|
|
|
static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
|
|
|
|
.name = "ctrl_module_wkup",
|
|
|
|
.class = &omap44xx_ctrl_module_hwmod_class,
|
|
|
|
.clkdm_name = "l4_wkup_clkdm",
|
2012-09-24 01:28:20 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
|
},
|
|
|
|
},
|
2012-04-19 21:33:57 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* ctrl_module_pad_wkup */
|
|
|
|
static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
|
|
|
|
.name = "ctrl_module_pad_wkup",
|
|
|
|
.class = &omap44xx_ctrl_module_hwmod_class,
|
|
|
|
.clkdm_name = "l4_wkup_clkdm",
|
2012-09-24 01:28:20 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
|
},
|
|
|
|
},
|
2012-04-19 21:33:57 +02:00
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:59 +02:00
|
|
|
/*
|
|
|
|
* 'debugss' class
|
|
|
|
* debug and emulation sub system
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
|
|
|
|
.name = "debugss",
|
|
|
|
};
|
|
|
|
|
|
|
|
/* debugss */
|
|
|
|
static struct omap_hwmod omap44xx_debugss_hwmod = {
|
|
|
|
.name = "debugss",
|
|
|
|
.class = &omap44xx_debugss_hwmod_class,
|
|
|
|
.clkdm_name = "emu_sys_clkdm",
|
|
|
|
.main_clk = "trace_clk_div_ck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-12-23 23:30:31 +01:00
|
|
|
/*
|
|
|
|
* 'dma' class
|
|
|
|
* dma controller for data exchange between memory to memory (i.e. internal or
|
|
|
|
* external memory) and gp peripherals to memory or memory to gp peripherals
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x002c,
|
|
|
|
.syss_offs = 0x0028,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
|
|
SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
|
|
SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
|
|
|
|
.name = "dma",
|
|
|
|
.sysc = &omap44xx_dma_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dma dev_attr */
|
|
|
|
static struct omap_dma_dev_attr dma_dev_attr = {
|
|
|
|
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
|
|
|
|
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
|
|
|
|
.lch_count = 32,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dma_system */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
|
|
|
|
{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-23 23:30:31 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_dma_system_hwmod = {
|
|
|
|
.name = "dma_system",
|
|
|
|
.class = &omap44xx_dma_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_dma_clkdm",
|
2010-12-23 23:30:31 +01:00
|
|
|
.mpu_irqs = omap44xx_dma_system_irqs,
|
|
|
|
.main_clk = "l3_div_ck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
|
2010-12-23 23:30:31 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
.dev_attr = &dma_dev_attr,
|
|
|
|
};
|
|
|
|
|
2011-01-25 23:01:00 +01:00
|
|
|
/*
|
|
|
|
* 'dmic' class
|
|
|
|
* digital microphone controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
|
|
|
|
.name = "dmic",
|
|
|
|
.sysc = &omap44xx_dmic_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dmic */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
|
|
|
|
{ .irq = 114 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-01-25 23:01:00 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
|
|
|
|
{ .dma_req = 66 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-01-25 23:01:00 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_dmic_hwmod = {
|
|
|
|
.name = "dmic",
|
|
|
|
.class = &omap44xx_dmic_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
2011-01-25 23:01:00 +01:00
|
|
|
.mpu_irqs = omap44xx_dmic_irqs,
|
|
|
|
.sdma_reqs = omap44xx_dmic_sdma_reqs,
|
|
|
|
.main_clk = "dmic_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-01-25 23:01:00 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-01-25 23:01:00 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:34 +01:00
|
|
|
/*
|
|
|
|
* 'dsp' class
|
|
|
|
* dsp sub-system
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
|
2010-12-23 23:30:32 +01:00
|
|
|
.name = "dsp",
|
2010-12-22 05:08:34 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* dsp */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
|
|
|
|
{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-22 05:08:34 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
|
|
|
|
{ .name = "dsp", .rst_shift = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_dsp_hwmod = {
|
|
|
|
.name = "dsp",
|
|
|
|
.class = &omap44xx_dsp_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "tesla_clkdm",
|
2010-12-22 05:08:34 +01:00
|
|
|
.mpu_irqs = omap44xx_dsp_irqs,
|
|
|
|
.rst_lines = omap44xx_dsp_resets,
|
|
|
|
.rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
|
|
|
|
.main_clk = "dsp_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
|
2011-07-10 13:56:31 +02:00
|
|
|
.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2010-12-22 05:08:34 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
/*
|
|
|
|
* 'dss' class
|
|
|
|
* display sub-system
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = SYSS_HAS_RESET_STATUS,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
|
|
|
|
.name = "dss",
|
|
|
|
.sysc = &omap44xx_dss_sysc,
|
2011-11-08 11:16:13 +01:00
|
|
|
.reset = omap_dss_reset,
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* dss */
|
|
|
|
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
|
|
|
|
{ .role = "sys_clk", .clk = "dss_sys_clk" },
|
|
|
|
{ .role = "tv_clk", .clk = "dss_tv_clk" },
|
2011-11-08 11:16:12 +01:00
|
|
|
{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_dss_hwmod = {
|
|
|
|
.name = "dss_core",
|
2011-11-08 11:16:11 +01:00
|
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.class = &omap44xx_dss_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_dss_clkdm",
|
2011-07-10 04:39:45 +02:00
|
|
|
.main_clk = "dss_dss_clk",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
.opt_clks = dss_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'dispc' class
|
|
|
|
* display controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
|
|
SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
|
|
|
|
.name = "dispc",
|
|
|
|
.sysc = &omap44xx_dispc_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dss_dispc */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
|
|
|
|
{ .irq = 25 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
|
|
|
|
{ .dma_req = 5 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
2011-10-07 02:04:08 +02:00
|
|
|
static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
|
|
|
|
.manager_count = 3,
|
|
|
|
.has_framedonetv_irq = 1
|
|
|
|
};
|
|
|
|
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
|
|
|
|
.name = "dss_dispc",
|
|
|
|
.class = &omap44xx_dispc_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_dss_clkdm",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.mpu_irqs = omap44xx_dss_dispc_irqs,
|
|
|
|
.sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
|
2011-07-10 04:39:45 +02:00
|
|
|
.main_clk = "dss_dss_clk",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
},
|
|
|
|
},
|
2011-10-07 02:04:08 +02:00
|
|
|
.dev_attr = &omap44xx_dss_dispc_dev_attr
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'dsi' class
|
|
|
|
* display serial interface controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
|
|
|
|
.name = "dsi",
|
|
|
|
.sysc = &omap44xx_dsi_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dss_dsi1 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
|
|
|
|
{ .irq = 53 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
|
|
|
|
{ .dma_req = 74 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
2011-07-10 04:39:44 +02:00
|
|
|
static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
|
|
|
|
{ .role = "sys_clk", .clk = "dss_sys_clk" },
|
|
|
|
};
|
|
|
|
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
|
|
|
|
.name = "dss_dsi1",
|
|
|
|
.class = &omap44xx_dsi_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_dss_clkdm",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.mpu_irqs = omap44xx_dss_dsi1_irqs,
|
|
|
|
.sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
|
2011-07-10 04:39:45 +02:00
|
|
|
.main_clk = "dss_dss_clk",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
},
|
|
|
|
},
|
2011-07-10 04:39:44 +02:00
|
|
|
.opt_clks = dss_dsi1_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* dss_dsi2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
|
|
|
|
{ .irq = 84 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
|
|
|
|
{ .dma_req = 83 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
2011-07-10 04:39:44 +02:00
|
|
|
static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
|
|
|
|
{ .role = "sys_clk", .clk = "dss_sys_clk" },
|
|
|
|
};
|
|
|
|
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
|
|
|
|
.name = "dss_dsi2",
|
|
|
|
.class = &omap44xx_dsi_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_dss_clkdm",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.mpu_irqs = omap44xx_dss_dsi2_irqs,
|
|
|
|
.sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
|
2011-07-10 04:39:45 +02:00
|
|
|
.main_clk = "dss_dss_clk",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
},
|
|
|
|
},
|
2011-07-10 04:39:44 +02:00
|
|
|
.opt_clks = dss_dsi2_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'hdmi' class
|
|
|
|
* hdmi controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
|
|
|
|
.name = "hdmi",
|
|
|
|
.sysc = &omap44xx_hdmi_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dss_hdmi */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
|
|
|
|
{ .irq = 101 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
|
|
|
|
{ .dma_req = 75 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
2011-07-10 04:39:44 +02:00
|
|
|
static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
|
|
|
|
{ .role = "sys_clk", .clk = "dss_sys_clk" },
|
|
|
|
};
|
|
|
|
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
|
|
|
|
.name = "dss_hdmi",
|
|
|
|
.class = &omap44xx_hdmi_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_dss_clkdm",
|
2012-06-21 10:08:53 +02:00
|
|
|
/*
|
|
|
|
* HDMI audio requires to use no-idle mode. Hence,
|
|
|
|
* set idle mode by software.
|
|
|
|
*/
|
|
|
|
.flags = HWMOD_SWSUP_SIDLE,
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.mpu_irqs = omap44xx_dss_hdmi_irqs,
|
|
|
|
.sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
|
2011-11-08 11:16:12 +01:00
|
|
|
.main_clk = "dss_48mhz_clk",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
},
|
|
|
|
},
|
2011-07-10 04:39:44 +02:00
|
|
|
.opt_clks = dss_hdmi_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'rfbi' class
|
|
|
|
* remote frame buffer interface
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
|
|
|
|
.name = "rfbi",
|
|
|
|
.sysc = &omap44xx_rfbi_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dss_rfbi */
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
|
|
|
|
{ .dma_req = 13 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
2011-07-10 04:39:44 +02:00
|
|
|
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
|
|
|
|
{ .role = "ick", .clk = "dss_fck" },
|
|
|
|
};
|
|
|
|
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
|
|
|
|
.name = "dss_rfbi",
|
|
|
|
.class = &omap44xx_rfbi_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_dss_clkdm",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
|
2011-07-10 04:39:45 +02:00
|
|
|
.main_clk = "dss_dss_clk",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
},
|
|
|
|
},
|
2011-07-10 04:39:44 +02:00
|
|
|
.opt_clks = dss_rfbi_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'venc' class
|
|
|
|
* video encoder
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
|
|
|
|
.name = "venc",
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dss_venc */
|
|
|
|
static struct omap_hwmod omap44xx_dss_venc_hwmod = {
|
|
|
|
.name = "dss_venc",
|
|
|
|
.class = &omap44xx_venc_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_dss_clkdm",
|
2011-11-08 11:16:12 +01:00
|
|
|
.main_clk = "dss_tv_clk",
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson@ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
2011-01-27 12:17:03 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
/*
|
|
|
|
* 'elm' class
|
|
|
|
* bch error location module
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
|
|
SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
|
|
|
|
.name = "elm",
|
|
|
|
.sysc = &omap44xx_elm_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* elm */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
|
|
|
|
{ .irq = 4 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_elm_hwmod = {
|
|
|
|
.name = "elm",
|
|
|
|
.class = &omap44xx_elm_hwmod_class,
|
|
|
|
.clkdm_name = "l4_per_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_elm_irqs,
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:52 +02:00
|
|
|
/*
|
|
|
|
* 'emif' class
|
|
|
|
* external memory interface no1
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
|
|
|
|
.name = "emif",
|
|
|
|
.sysc = &omap44xx_emif_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* emif1 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
|
|
|
|
{ .irq = 110 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_emif1_hwmod = {
|
|
|
|
.name = "emif1",
|
|
|
|
.class = &omap44xx_emif_hwmod_class,
|
|
|
|
.clkdm_name = "l3_emif_clkdm",
|
|
|
|
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
|
|
|
|
.mpu_irqs = omap44xx_emif1_irqs,
|
|
|
|
.main_clk = "ddrphy_ck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* emif2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
|
|
|
|
{ .irq = 111 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_emif2_hwmod = {
|
|
|
|
.name = "emif2",
|
|
|
|
.class = &omap44xx_emif_hwmod_class,
|
|
|
|
.clkdm_name = "l3_emif_clkdm",
|
|
|
|
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
|
|
|
|
.mpu_irqs = omap44xx_emif2_irqs,
|
|
|
|
.main_clk = "ddrphy_ck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:50 +02:00
|
|
|
/*
|
|
|
|
* 'fdif' class
|
|
|
|
* face detection hw accelerator module
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
/*
|
|
|
|
* FDIF needs 100 OCP clk cycles delay after a softreset before
|
|
|
|
* accessing sysconfig again.
|
|
|
|
* The lowest frequency at the moment for L3 bus is 100 MHz, so
|
|
|
|
* 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
|
|
|
|
*
|
|
|
|
* TODO: Indicate errata when available.
|
|
|
|
*/
|
|
|
|
.srst_udelay = 2,
|
|
|
|
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
|
|
|
|
.name = "fdif",
|
|
|
|
.sysc = &omap44xx_fdif_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* fdif */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
|
|
|
|
{ .irq = 69 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_fdif_hwmod = {
|
|
|
|
.name = "fdif",
|
|
|
|
.class = &omap44xx_fdif_hwmod_class,
|
|
|
|
.clkdm_name = "iss_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_fdif_irqs,
|
|
|
|
.main_clk = "fdif_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/*
|
|
|
|
* 'gpio' class
|
|
|
|
* general purpose io module
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
2010-09-21 16:07:14 +02:00
|
|
|
.sysc_offs = 0x0010,
|
2010-12-22 05:08:33 +01:00
|
|
|
.syss_offs = 0x0114,
|
2010-12-22 05:08:33 +01:00
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
|
|
SYSS_HAS_RESET_STATUS),
|
2010-12-22 05:31:28 +01:00
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
2010-09-21 16:07:14 +02:00
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
|
2010-12-23 23:30:32 +01:00
|
|
|
.name = "gpio",
|
|
|
|
.sysc = &omap44xx_gpio_sysc,
|
|
|
|
.rev = 2,
|
2010-09-21 16:07:14 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* gpio dev_attr */
|
|
|
|
static struct omap_gpio_dev_attr gpio_dev_attr = {
|
2010-12-23 23:30:32 +01:00
|
|
|
.bank_width = 32,
|
|
|
|
.dbck_flag = true,
|
2010-09-21 16:07:14 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* gpio1 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
|
|
|
|
{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-09-21 16:07:14 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
|
2010-12-22 05:08:34 +01:00
|
|
|
{ .role = "dbclk", .clk = "gpio1_dbclk" },
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_gpio1_hwmod = {
|
|
|
|
.name = "gpio1",
|
|
|
|
.class = &omap44xx_gpio_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_wkup_clkdm",
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_gpio1_irqs,
|
|
|
|
.main_clk = "gpio1_ick",
|
2010-09-21 16:07:14 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2010-09-21 16:07:14 +02:00
|
|
|
},
|
|
|
|
},
|
2010-12-22 05:08:33 +01:00
|
|
|
.opt_clks = gpio1_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
|
|
|
|
.dev_attr = &gpio_dev_attr,
|
2010-09-21 16:07:14 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* gpio2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
|
|
|
|
{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-09-21 16:07:14 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
|
2010-12-22 05:08:34 +01:00
|
|
|
{ .role = "dbclk", .clk = "gpio2_dbclk" },
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_gpio2_hwmod = {
|
|
|
|
.name = "gpio2",
|
|
|
|
.class = &omap44xx_gpio_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2010-12-22 05:08:34 +01:00
|
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_gpio2_irqs,
|
|
|
|
.main_clk = "gpio2_ick",
|
2010-09-21 16:07:14 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2010-09-21 16:07:14 +02:00
|
|
|
},
|
|
|
|
},
|
2010-12-22 05:08:33 +01:00
|
|
|
.opt_clks = gpio2_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
|
|
|
|
.dev_attr = &gpio_dev_attr,
|
2010-09-21 16:07:14 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* gpio3 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
|
|
|
|
{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-09-21 16:07:14 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
|
2010-12-22 05:08:34 +01:00
|
|
|
{ .role = "dbclk", .clk = "gpio3_dbclk" },
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_gpio3_hwmod = {
|
|
|
|
.name = "gpio3",
|
|
|
|
.class = &omap44xx_gpio_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2010-12-22 05:08:34 +01:00
|
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_gpio3_irqs,
|
|
|
|
.main_clk = "gpio3_ick",
|
2010-09-21 16:07:14 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2010-09-21 16:07:14 +02:00
|
|
|
},
|
|
|
|
},
|
2010-12-22 05:08:33 +01:00
|
|
|
.opt_clks = gpio3_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
|
|
|
|
.dev_attr = &gpio_dev_attr,
|
2010-09-21 16:07:14 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* gpio4 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
|
|
|
|
{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-09-21 16:07:14 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
|
2010-12-22 05:08:34 +01:00
|
|
|
{ .role = "dbclk", .clk = "gpio4_dbclk" },
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_gpio4_hwmod = {
|
|
|
|
.name = "gpio4",
|
|
|
|
.class = &omap44xx_gpio_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2010-12-22 05:08:34 +01:00
|
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_gpio4_irqs,
|
|
|
|
.main_clk = "gpio4_ick",
|
2010-09-21 16:07:14 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2010-09-21 16:07:14 +02:00
|
|
|
},
|
|
|
|
},
|
2010-12-22 05:08:33 +01:00
|
|
|
.opt_clks = gpio4_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
|
|
|
|
.dev_attr = &gpio_dev_attr,
|
2010-09-21 16:07:14 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* gpio5 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
|
|
|
|
{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-05-12 17:54:36 +02:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
|
|
|
|
{ .role = "dbclk", .clk = "gpio5_dbclk" },
|
2010-05-12 17:54:36 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod omap44xx_gpio5_hwmod = {
|
|
|
|
.name = "gpio5",
|
|
|
|
.class = &omap44xx_gpio_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2010-12-22 05:08:34 +01:00
|
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_gpio5_irqs,
|
|
|
|
.main_clk = "gpio5_ick",
|
2010-05-12 17:54:36 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2010-05-12 17:54:36 +02:00
|
|
|
},
|
|
|
|
},
|
2010-12-22 05:08:33 +01:00
|
|
|
.opt_clks = gpio5_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
|
|
|
|
.dev_attr = &gpio_dev_attr,
|
2010-05-12 17:54:36 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* gpio6 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
|
|
|
|
{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-09-23 16:32:41 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
|
2010-12-22 05:08:34 +01:00
|
|
|
{ .role = "dbclk", .clk = "gpio6_dbclk" },
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod omap44xx_gpio6_hwmod = {
|
|
|
|
.name = "gpio6",
|
|
|
|
.class = &omap44xx_gpio_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2010-12-22 05:08:34 +01:00
|
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_gpio6_irqs,
|
|
|
|
.main_clk = "gpio6_ick",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2010-12-22 05:08:33 +01:00
|
|
|
},
|
2010-09-27 16:49:19 +02:00
|
|
|
},
|
2010-12-22 05:08:33 +01:00
|
|
|
.opt_clks = gpio6_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
|
|
|
|
.dev_attr = &gpio_dev_attr,
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:51 +02:00
|
|
|
/*
|
|
|
|
* 'gpmc' class
|
|
|
|
* general purpose memory controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
|
|
|
|
.name = "gpmc",
|
|
|
|
.sysc = &omap44xx_gpmc_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* gpmc */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
|
|
|
|
{ .irq = 20 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
|
|
|
|
{ .dma_req = 3 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .dma_req = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_gpmc_hwmod = {
|
|
|
|
.name = "gpmc",
|
|
|
|
.class = &omap44xx_gpmc_hwmod_class,
|
|
|
|
.clkdm_name = "l3_2_clkdm",
|
2012-09-24 01:28:24 +02:00
|
|
|
/*
|
|
|
|
* XXX HWMOD_INIT_NO_RESET should not be needed for this IP
|
|
|
|
* block. It is not being added due to any known bugs with
|
|
|
|
* resetting the GPMC IP block, but rather because any timings
|
|
|
|
* set by the bootloader are not being correctly programmed by
|
|
|
|
* the kernel from the board file or DT data.
|
|
|
|
* HWMOD_INIT_NO_RESET should be removed ASAP.
|
|
|
|
*/
|
2012-04-19 21:33:51 +02:00
|
|
|
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
|
|
|
|
.mpu_irqs = omap44xx_gpmc_irqs,
|
|
|
|
.sdma_reqs = omap44xx_gpmc_sdma_reqs,
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:53 +02:00
|
|
|
/*
|
|
|
|
* 'gpu' class
|
|
|
|
* 2d/3d graphics accelerator
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
|
|
|
|
.rev_offs = 0x1fc00,
|
|
|
|
.sysc_offs = 0x1fc10,
|
|
|
|
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
|
|
|
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
|
|
|
|
.name = "gpu",
|
|
|
|
.sysc = &omap44xx_gpu_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* gpu */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
|
|
|
|
{ .irq = 21 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_gpu_hwmod = {
|
|
|
|
.name = "gpu",
|
|
|
|
.class = &omap44xx_gpu_hwmod_class,
|
|
|
|
.clkdm_name = "l3_gfx_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_gpu_irqs,
|
|
|
|
.main_clk = "gpu_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:50 +02:00
|
|
|
/*
|
|
|
|
* 'hdq1w' class
|
|
|
|
* hdq / 1-wire serial interface controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0014,
|
|
|
|
.syss_offs = 0x0018,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
|
|
|
|
SYSS_HAS_RESET_STATUS),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
|
|
|
|
.name = "hdq1w",
|
|
|
|
.sysc = &omap44xx_hdq1w_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* hdq1w */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
|
|
|
|
{ .irq = 58 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_hdq1w_hwmod = {
|
|
|
|
.name = "hdq1w",
|
|
|
|
.class = &omap44xx_hdq1w_hwmod_class,
|
|
|
|
.clkdm_name = "l4_per_clkdm",
|
|
|
|
.flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
|
|
|
|
.mpu_irqs = omap44xx_hdq1w_irqs,
|
|
|
|
.main_clk = "hdq1w_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-02-15 22:39:48 +01:00
|
|
|
/*
|
|
|
|
* 'hsi' class
|
|
|
|
* mipi high-speed synchronous serial interface (multichannel and full-duplex
|
|
|
|
* serial if)
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
|
|
|
|
SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
2011-07-01 22:54:01 +02:00
|
|
|
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
2011-02-15 22:39:48 +01:00
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
|
|
|
|
.name = "hsi",
|
|
|
|
.sysc = &omap44xx_hsi_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* hsi */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
|
|
|
|
{ .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_hsi_hwmod = {
|
|
|
|
.name = "hsi",
|
|
|
|
.class = &omap44xx_hsi_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_init_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_hsi_irqs,
|
|
|
|
.main_clk = "hsi_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/*
|
|
|
|
* 'i2c' class
|
|
|
|
* multimaster high-speed i2c controller
|
|
|
|
*/
|
2010-09-27 16:49:19 +02:00
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0090,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
2010-12-22 05:08:33 +01:00
|
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
2010-12-22 05:31:28 +01:00
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
2011-12-13 11:55:54 +01:00
|
|
|
.clockact = CLOCKACT_TEST_ICLK,
|
2010-12-22 05:08:33 +01:00
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
|
2010-12-23 23:30:32 +01:00
|
|
|
.name = "i2c",
|
|
|
|
.sysc = &omap44xx_i2c_sysc,
|
2011-07-10 13:27:15 +02:00
|
|
|
.rev = OMAP_I2C_IP_VERSION_2,
|
2011-07-10 13:27:16 +02:00
|
|
|
.reset = &omap_i2c_reset,
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2011-07-10 13:27:16 +02:00
|
|
|
static struct omap_i2c_dev_attr i2c_dev_attr = {
|
2012-05-08 19:34:29 +02:00
|
|
|
.flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
|
|
|
|
OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
|
2011-07-10 13:27:16 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* i2c1 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
|
|
|
|
{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod omap44xx_i2c1_hwmod = {
|
|
|
|
.name = "i2c1",
|
|
|
|
.class = &omap44xx_i2c_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-12-13 11:55:54 +01:00
|
|
|
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_i2c1_irqs,
|
|
|
|
.sdma_reqs = omap44xx_i2c1_sdma_reqs,
|
|
|
|
.main_clk = "i2c1_fck",
|
2010-09-23 16:32:41 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-09-23 16:32:41 +02:00
|
|
|
},
|
|
|
|
},
|
2011-07-10 13:27:16 +02:00
|
|
|
.dev_attr = &i2c_dev_attr,
|
2010-09-23 16:32:41 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* i2c2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
|
|
|
|
{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-09-23 16:32:41 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_i2c2_hwmod = {
|
|
|
|
.name = "i2c2",
|
|
|
|
.class = &omap44xx_i2c_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-12-13 11:55:54 +01:00
|
|
|
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_i2c2_irqs,
|
|
|
|
.sdma_reqs = omap44xx_i2c2_sdma_reqs,
|
|
|
|
.main_clk = "i2c2_fck",
|
2010-09-27 16:49:19 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-09-27 16:49:19 +02:00
|
|
|
},
|
|
|
|
},
|
2011-07-10 13:27:16 +02:00
|
|
|
.dev_attr = &i2c_dev_attr,
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* i2c3 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
|
|
|
|
{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2010-09-23 16:32:41 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod omap44xx_i2c3_hwmod = {
|
|
|
|
.name = "i2c3",
|
|
|
|
.class = &omap44xx_i2c_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-12-13 11:55:54 +01:00
|
|
|
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_i2c3_irqs,
|
|
|
|
.sdma_reqs = omap44xx_i2c3_sdma_reqs,
|
|
|
|
.main_clk = "i2c3_fck",
|
2010-09-27 16:49:19 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-09-27 16:49:19 +02:00
|
|
|
},
|
|
|
|
},
|
2011-07-10 13:27:16 +02:00
|
|
|
.dev_attr = &i2c_dev_attr,
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* i2c4 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
|
|
|
|
{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod omap44xx_i2c4_hwmod = {
|
|
|
|
.name = "i2c4",
|
|
|
|
.class = &omap44xx_i2c_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-12-13 11:55:54 +01:00
|
|
|
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_i2c4_irqs,
|
|
|
|
.sdma_reqs = omap44xx_i2c4_sdma_reqs,
|
|
|
|
.main_clk = "i2c4_fck",
|
2010-09-23 16:32:41 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-09-23 16:32:41 +02:00
|
|
|
},
|
|
|
|
},
|
2011-07-10 13:27:16 +02:00
|
|
|
.dev_attr = &i2c_dev_attr,
|
2010-09-23 16:32:41 +02:00
|
|
|
};
|
|
|
|
|
2011-02-15 22:39:48 +01:00
|
|
|
/*
|
|
|
|
* 'ipu' class
|
|
|
|
* imaging processor unit
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
|
|
|
|
.name = "ipu",
|
|
|
|
};
|
|
|
|
|
|
|
|
/* ipu */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
|
|
|
|
{ .irq = 100 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
ARM: OMAP4: hwmod data: remove pseudo-hwmods associated with hardreset lines
Remove the pseudo-hwmods associated with hardreset lines from the
OMAP4 data file. Future patches will convert this data to register
hwmods by interfaces, rather than registering hwmods directly. The
pseudo-hwmods aren't associated with any interfaces, so this will
create a problem.
After this change, the hwmod code will reset processor IPs at the
hwmod level, rather than by individual hardreset lines. So, for
example, if the IVA device driver code wishes to place one of the
sequencer cores into reset, while leaving the other active, it must do
so itself by calling the appropriate PRM functions.
This patch will cause a change in the initialization behavior of the
DSP, IVA, and IPU.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
2012-04-19 03:10:02 +02:00
|
|
|
static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
|
2011-02-15 22:39:48 +01:00
|
|
|
{ .name = "cpu0", .rst_shift = 0 },
|
|
|
|
{ .name = "cpu1", .rst_shift = 1 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_ipu_hwmod = {
|
|
|
|
.name = "ipu",
|
|
|
|
.class = &omap44xx_ipu_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "ducati_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_ipu_irqs,
|
|
|
|
.rst_lines = omap44xx_ipu_resets,
|
|
|
|
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
|
|
|
|
.main_clk = "ipu_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
|
2011-07-10 13:56:31 +02:00
|
|
|
.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'iss' class
|
|
|
|
* external images sensor pixel data processor
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
2012-04-13 13:08:03 +02:00
|
|
|
/*
|
|
|
|
* ISS needs 100 OCP clk cycles delay after a softreset before
|
|
|
|
* accessing sysconfig again.
|
|
|
|
* The lowest frequency at the moment for L3 bus is 100 MHz, so
|
|
|
|
* 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
|
|
|
|
*
|
|
|
|
* TODO: Indicate errata when available.
|
|
|
|
*/
|
|
|
|
.srst_udelay = 2,
|
2011-02-15 22:39:48 +01:00
|
|
|
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
2011-07-01 22:54:01 +02:00
|
|
|
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
2011-02-15 22:39:48 +01:00
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
|
|
|
|
.name = "iss",
|
|
|
|
.sysc = &omap44xx_iss_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* iss */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
|
|
|
|
{ .irq = 24 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
|
|
|
|
{ .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_opt_clk iss_opt_clks[] = {
|
|
|
|
{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_iss_hwmod = {
|
|
|
|
.name = "iss",
|
|
|
|
.class = &omap44xx_iss_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "iss_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_iss_irqs,
|
|
|
|
.sdma_reqs = omap44xx_iss_sdma_reqs,
|
|
|
|
.main_clk = "iss_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
.opt_clks = iss_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:34 +01:00
|
|
|
/*
|
|
|
|
* 'iva' class
|
|
|
|
* multi-standard video encoder/decoder hardware accelerator
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
|
2010-12-23 23:30:32 +01:00
|
|
|
.name = "iva",
|
2010-12-22 05:08:34 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* iva */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
|
|
|
|
{ .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-22 05:08:34 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
|
|
|
|
{ .name = "seq0", .rst_shift = 0 },
|
|
|
|
{ .name = "seq1", .rst_shift = 1 },
|
ARM: OMAP4: hwmod data: remove pseudo-hwmods associated with hardreset lines
Remove the pseudo-hwmods associated with hardreset lines from the
OMAP4 data file. Future patches will convert this data to register
hwmods by interfaces, rather than registering hwmods directly. The
pseudo-hwmods aren't associated with any interfaces, so this will
create a problem.
After this change, the hwmod code will reset processor IPs at the
hwmod level, rather than by individual hardreset lines. So, for
example, if the IVA device driver code wishes to place one of the
sequencer cores into reset, while leaving the other active, it must do
so itself by calling the appropriate PRM functions.
This patch will cause a change in the initialization behavior of the
DSP, IVA, and IPU.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
2012-04-19 03:10:02 +02:00
|
|
|
{ .name = "logic", .rst_shift = 2 },
|
2010-12-22 05:08:34 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_iva_hwmod = {
|
|
|
|
.name = "iva",
|
|
|
|
.class = &omap44xx_iva_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "ivahd_clkdm",
|
2010-12-22 05:08:34 +01:00
|
|
|
.mpu_irqs = omap44xx_iva_irqs,
|
|
|
|
.rst_lines = omap44xx_iva_resets,
|
|
|
|
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
|
|
|
|
.main_clk = "iva_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
|
2011-07-10 13:56:31 +02:00
|
|
|
.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2010-12-22 05:08:34 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-02-15 22:39:48 +01:00
|
|
|
/*
|
|
|
|
* 'kbd' class
|
|
|
|
* keyboard controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
|
|
SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
|
|
SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
|
|
|
|
.name = "kbd",
|
|
|
|
.sysc = &omap44xx_kbd_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* kbd */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
|
|
|
|
{ .irq = 120 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_kbd_hwmod = {
|
|
|
|
.name = "kbd",
|
|
|
|
.class = &omap44xx_kbd_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_wkup_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_kbd_irqs,
|
|
|
|
.main_clk = "kbd_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-02-02 20:27:21 +01:00
|
|
|
/*
|
|
|
|
* 'mailbox' class
|
|
|
|
* mailbox module allowing communication between the on-chip processors using a
|
|
|
|
* queued mailbox-interrupt mechanism.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
|
|
|
|
.name = "mailbox",
|
|
|
|
.sysc = &omap44xx_mailbox_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mailbox */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
|
|
|
|
{ .irq = 26 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-02 20:27:21 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mailbox_hwmod = {
|
|
|
|
.name = "mailbox",
|
|
|
|
.class = &omap44xx_mailbox_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_cfg_clkdm",
|
2011-02-02 20:27:21 +01:00
|
|
|
.mpu_irqs = omap44xx_mailbox_irqs,
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-02 20:27:21 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
|
2011-02-02 20:27:21 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
/*
|
|
|
|
* 'mcasp' class
|
|
|
|
* multi-channel audio serial port controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* The IP is not compliant to type1 / type2 scheme */
|
|
|
|
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
|
|
|
|
.sidle_shift = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
|
|
|
|
.sysc_offs = 0x0004,
|
|
|
|
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type_mcasp,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
|
|
|
|
.name = "mcasp",
|
|
|
|
.sysc = &omap44xx_mcasp_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mcasp */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
|
|
|
|
{ .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
|
|
|
|
{ .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .dma_req = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mcasp_hwmod = {
|
|
|
|
.name = "mcasp",
|
|
|
|
.class = &omap44xx_mcasp_hwmod_class,
|
|
|
|
.clkdm_name = "abe_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_mcasp_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mcasp_sdma_reqs,
|
|
|
|
.main_clk = "mcasp_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-01-31 15:50:30 +01:00
|
|
|
/*
|
|
|
|
* 'mcbsp' class
|
|
|
|
* multi channel buffered serial port controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
|
|
|
|
.sysc_offs = 0x008c,
|
|
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
|
|
|
|
.name = "mcbsp",
|
|
|
|
.sysc = &omap44xx_mcbsp_sysc,
|
2011-02-24 10:46:50 +01:00
|
|
|
.rev = MCBSP_CONFIG_TYPE4,
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* mcbsp1 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
|
2012-05-08 19:34:29 +02:00
|
|
|
{ .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
2012-04-04 17:11:48 +02:00
|
|
|
static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
|
|
|
|
{ .role = "pad_fck", .clk = "pad_clks_ck" },
|
2012-07-04 14:55:29 +02:00
|
|
|
{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
|
2012-04-04 17:11:48 +02:00
|
|
|
};
|
|
|
|
|
2011-01-31 15:50:30 +01:00
|
|
|
static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
|
|
|
|
.name = "mcbsp1",
|
|
|
|
.class = &omap44xx_mcbsp_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
2011-01-31 15:50:30 +01:00
|
|
|
.mpu_irqs = omap44xx_mcbsp1_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
|
|
|
|
.main_clk = "mcbsp1_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-01-31 15:50:30 +01:00
|
|
|
},
|
|
|
|
},
|
2012-04-04 17:11:48 +02:00
|
|
|
.opt_clks = mcbsp1_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* mcbsp2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
|
2012-05-08 19:34:29 +02:00
|
|
|
{ .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
|
|
|
|
{ .role = "pad_fck", .clk = "pad_clks_ck" },
|
2012-07-04 14:55:29 +02:00
|
|
|
{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
|
2012-04-04 17:11:48 +02:00
|
|
|
};
|
|
|
|
|
2011-01-31 15:50:30 +01:00
|
|
|
static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
|
|
|
|
.name = "mcbsp2",
|
|
|
|
.class = &omap44xx_mcbsp_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
2011-01-31 15:50:30 +01:00
|
|
|
.mpu_irqs = omap44xx_mcbsp2_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
|
|
|
|
.main_clk = "mcbsp2_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-01-31 15:50:30 +01:00
|
|
|
},
|
|
|
|
},
|
2012-04-04 17:11:48 +02:00
|
|
|
.opt_clks = mcbsp2_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* mcbsp3 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
|
2012-05-08 19:34:29 +02:00
|
|
|
{ .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
2012-04-04 17:11:48 +02:00
|
|
|
static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
|
|
|
|
{ .role = "pad_fck", .clk = "pad_clks_ck" },
|
2012-07-04 14:55:29 +02:00
|
|
|
{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
|
2012-04-04 17:11:48 +02:00
|
|
|
};
|
|
|
|
|
2011-01-31 15:50:30 +01:00
|
|
|
static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
|
|
|
|
.name = "mcbsp3",
|
|
|
|
.class = &omap44xx_mcbsp_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
2011-01-31 15:50:30 +01:00
|
|
|
.mpu_irqs = omap44xx_mcbsp3_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
|
|
|
|
.main_clk = "mcbsp3_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-01-31 15:50:30 +01:00
|
|
|
},
|
|
|
|
},
|
2012-04-04 17:11:48 +02:00
|
|
|
.opt_clks = mcbsp3_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* mcbsp4 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
|
2012-05-08 19:34:29 +02:00
|
|
|
{ .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
2012-04-04 17:11:48 +02:00
|
|
|
static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
|
|
|
|
{ .role = "pad_fck", .clk = "pad_clks_ck" },
|
2012-07-04 14:55:29 +02:00
|
|
|
{ .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
|
2012-04-04 17:11:48 +02:00
|
|
|
};
|
|
|
|
|
2011-01-31 15:50:30 +01:00
|
|
|
static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
|
|
|
|
.name = "mcbsp4",
|
|
|
|
.class = &omap44xx_mcbsp_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-01-31 15:50:30 +01:00
|
|
|
.mpu_irqs = omap44xx_mcbsp4_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
|
|
|
|
.main_clk = "mcbsp4_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-01-31 15:50:30 +01:00
|
|
|
},
|
|
|
|
},
|
2012-04-04 17:11:48 +02:00
|
|
|
.opt_clks = mcbsp4_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
|
2011-01-31 15:50:30 +01:00
|
|
|
};
|
|
|
|
|
2011-02-15 22:39:48 +01:00
|
|
|
/*
|
|
|
|
* 'mcpdm' class
|
|
|
|
* multi channel pdm controller (proprietary interface with phoenix power
|
|
|
|
* ic)
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
|
|
|
|
.name = "mcpdm",
|
|
|
|
.sysc = &omap44xx_mcpdm_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mcpdm */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
|
|
|
|
{ .irq = 112 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
|
|
|
|
{ .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mcpdm_hwmod = {
|
|
|
|
.name = "mcpdm",
|
|
|
|
.class = &omap44xx_mcpdm_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
2012-10-30 05:02:14 +01:00
|
|
|
/*
|
|
|
|
* It's suspected that the McPDM requires an off-chip main
|
|
|
|
* functional clock, controlled via I2C. This IP block is
|
|
|
|
* currently reset very early during boot, before I2C is
|
|
|
|
* available, so it doesn't seem that we have any choice in
|
|
|
|
* the kernel other than to avoid resetting it.
|
|
|
|
*/
|
|
|
|
.flags = HWMOD_EXT_OPT_MAIN_CLK,
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_mcpdm_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mcpdm_sdma_reqs,
|
|
|
|
.main_clk = "mcpdm_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-02-02 13:22:13 +01:00
|
|
|
/*
|
|
|
|
* 'mcspi' class
|
|
|
|
* multichannel serial port interface (mcspi) / master/slave synchronous serial
|
|
|
|
* bus
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
|
|
|
|
.name = "mcspi",
|
|
|
|
.sysc = &omap44xx_mcspi_sysc,
|
2011-02-18 14:01:06 +01:00
|
|
|
.rev = OMAP4_MCSPI_REV,
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* mcspi1 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
|
|
|
|
{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
|
|
|
|
{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
2011-02-18 14:01:06 +01:00
|
|
|
/* mcspi1 dev_attr */
|
|
|
|
static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
|
|
|
|
.num_chipselect = 4,
|
|
|
|
};
|
|
|
|
|
2011-02-02 13:22:13 +01:00
|
|
|
static struct omap_hwmod omap44xx_mcspi1_hwmod = {
|
|
|
|
.name = "mcspi1",
|
|
|
|
.class = &omap44xx_mcspi_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-02-02 13:22:13 +01:00
|
|
|
.mpu_irqs = omap44xx_mcspi1_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mcspi1_sdma_reqs,
|
|
|
|
.main_clk = "mcspi1_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-02 13:22:13 +01:00
|
|
|
},
|
|
|
|
},
|
2011-02-18 14:01:06 +01:00
|
|
|
.dev_attr = &mcspi1_dev_attr,
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* mcspi2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
|
|
|
|
{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
|
|
|
|
{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
2011-02-18 14:01:06 +01:00
|
|
|
/* mcspi2 dev_attr */
|
|
|
|
static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
|
|
|
|
.num_chipselect = 2,
|
|
|
|
};
|
|
|
|
|
2011-02-02 13:22:13 +01:00
|
|
|
static struct omap_hwmod omap44xx_mcspi2_hwmod = {
|
|
|
|
.name = "mcspi2",
|
|
|
|
.class = &omap44xx_mcspi_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-02-02 13:22:13 +01:00
|
|
|
.mpu_irqs = omap44xx_mcspi2_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mcspi2_sdma_reqs,
|
|
|
|
.main_clk = "mcspi2_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-02 13:22:13 +01:00
|
|
|
},
|
|
|
|
},
|
2011-02-18 14:01:06 +01:00
|
|
|
.dev_attr = &mcspi2_dev_attr,
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* mcspi3 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
|
|
|
|
{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
|
|
|
|
{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
2011-02-18 14:01:06 +01:00
|
|
|
/* mcspi3 dev_attr */
|
|
|
|
static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
|
|
|
|
.num_chipselect = 2,
|
|
|
|
};
|
|
|
|
|
2011-02-02 13:22:13 +01:00
|
|
|
static struct omap_hwmod omap44xx_mcspi3_hwmod = {
|
|
|
|
.name = "mcspi3",
|
|
|
|
.class = &omap44xx_mcspi_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-02-02 13:22:13 +01:00
|
|
|
.mpu_irqs = omap44xx_mcspi3_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mcspi3_sdma_reqs,
|
|
|
|
.main_clk = "mcspi3_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-02 13:22:13 +01:00
|
|
|
},
|
|
|
|
},
|
2011-02-18 14:01:06 +01:00
|
|
|
.dev_attr = &mcspi3_dev_attr,
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* mcspi4 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
|
|
|
|
{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
|
|
|
|
{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
2011-02-18 14:01:06 +01:00
|
|
|
/* mcspi4 dev_attr */
|
|
|
|
static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
|
|
|
|
.num_chipselect = 1,
|
|
|
|
};
|
|
|
|
|
2011-02-02 13:22:13 +01:00
|
|
|
static struct omap_hwmod omap44xx_mcspi4_hwmod = {
|
|
|
|
.name = "mcspi4",
|
|
|
|
.class = &omap44xx_mcspi_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-02-02 13:22:13 +01:00
|
|
|
.mpu_irqs = omap44xx_mcspi4_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mcspi4_sdma_reqs,
|
|
|
|
.main_clk = "mcspi4_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-02 13:22:13 +01:00
|
|
|
},
|
|
|
|
},
|
2011-02-18 14:01:06 +01:00
|
|
|
.dev_attr = &mcspi4_dev_attr,
|
2011-02-02 13:22:13 +01:00
|
|
|
};
|
|
|
|
|
2011-02-15 22:39:48 +01:00
|
|
|
/*
|
|
|
|
* 'mmc' class
|
|
|
|
* multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
|
|
|
|
SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
2011-07-01 22:54:01 +02:00
|
|
|
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
2011-02-15 22:39:48 +01:00
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
|
|
|
|
.name = "mmc",
|
|
|
|
.sysc = &omap44xx_mmc_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mmc1 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
|
|
|
|
{ .irq = 83 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
2011-03-01 22:12:56 +01:00
|
|
|
/* mmc1 dev_attr */
|
|
|
|
static struct omap_mmc_dev_attr mmc1_dev_attr = {
|
|
|
|
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
|
|
|
|
};
|
|
|
|
|
2011-02-15 22:39:48 +01:00
|
|
|
static struct omap_hwmod omap44xx_mmc1_hwmod = {
|
|
|
|
.name = "mmc1",
|
|
|
|
.class = &omap44xx_mmc_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_init_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_mmc1_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mmc1_sdma_reqs,
|
|
|
|
.main_clk = "mmc1_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
2011-03-01 22:12:56 +01:00
|
|
|
.dev_attr = &mmc1_dev_attr,
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* mmc2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
|
|
|
|
{ .irq = 86 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mmc2_hwmod = {
|
|
|
|
.name = "mmc2",
|
|
|
|
.class = &omap44xx_mmc_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_init_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_mmc2_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mmc2_sdma_reqs,
|
|
|
|
.main_clk = "mmc2_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mmc3 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
|
|
|
|
{ .irq = 94 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mmc3_hwmod = {
|
|
|
|
.name = "mmc3",
|
|
|
|
.class = &omap44xx_mmc_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_mmc3_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mmc3_sdma_reqs,
|
|
|
|
.main_clk = "mmc3_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mmc4 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
|
|
|
|
{ .irq = 96 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mmc4_hwmod = {
|
|
|
|
.name = "mmc4",
|
|
|
|
.class = &omap44xx_mmc_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_mmc4_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mmc4_sdma_reqs,
|
|
|
|
.main_clk = "mmc4_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mmc5 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
|
|
|
|
{ .irq = 59 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2011-02-15 22:39:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mmc5_hwmod = {
|
|
|
|
.name = "mmc5",
|
|
|
|
.class = &omap44xx_mmc_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-02-15 22:39:48 +01:00
|
|
|
.mpu_irqs = omap44xx_mmc5_irqs,
|
|
|
|
.sdma_reqs = omap44xx_mmc5_sdma_reqs,
|
|
|
|
.main_clk = "mmc5_fck",
|
2011-07-10 03:14:28 +02:00
|
|
|
.prcm = {
|
2011-02-15 22:39:48 +01:00
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2011-02-15 22:39:48 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-09-24 01:28:24 +02:00
|
|
|
/*
|
|
|
|
* 'mmu' class
|
|
|
|
* The memory management unit performs virtual to physical address translation
|
|
|
|
* for its requestors.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig mmu_sysc = {
|
|
|
|
.rev_offs = 0x000,
|
|
|
|
.sysc_offs = 0x010,
|
|
|
|
.syss_offs = 0x014,
|
|
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
|
|
|
|
.name = "mmu",
|
|
|
|
.sysc = &mmu_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mmu ipu */
|
|
|
|
|
|
|
|
static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
|
|
|
|
.da_start = 0x0,
|
|
|
|
.da_end = 0xfffff000,
|
|
|
|
.nr_tlb_entries = 32,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
|
|
|
|
{ .irq = 100 + OMAP44XX_IRQ_GIC_START, },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
|
|
|
|
{ .name = "mmu_cache", .rst_shift = 2 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x55082000,
|
|
|
|
.pa_end = 0x550820ff,
|
|
|
|
.flags = ADDR_TYPE_RT,
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> mmu_ipu */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_mmu_ipu_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_mmu_ipu_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
|
|
|
|
.name = "mmu_ipu",
|
|
|
|
.class = &omap44xx_mmu_hwmod_class,
|
|
|
|
.clkdm_name = "ducati_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_mmu_ipu_irqs,
|
|
|
|
.rst_lines = omap44xx_mmu_ipu_resets,
|
|
|
|
.rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
|
|
|
|
.main_clk = "ducati_clk_mux_ck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
|
|
|
|
.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.dev_attr = &mmu_ipu_dev_attr,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mmu dsp */
|
|
|
|
|
|
|
|
static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
|
|
|
|
.da_start = 0x0,
|
|
|
|
.da_end = 0xfffff000,
|
|
|
|
.nr_tlb_entries = 32,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
|
|
|
|
{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
|
|
|
|
{ .name = "mmu_cache", .rst_shift = 1 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a066000,
|
|
|
|
.pa_end = 0x4a0660ff,
|
|
|
|
.flags = ADDR_TYPE_RT,
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> dsp */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_mmu_dsp_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mmu_dsp_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
|
|
|
|
.name = "mmu_dsp",
|
|
|
|
.class = &omap44xx_mmu_hwmod_class,
|
|
|
|
.clkdm_name = "tesla_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_mmu_dsp_irqs,
|
|
|
|
.rst_lines = omap44xx_mmu_dsp_resets,
|
|
|
|
.rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
|
|
|
|
.main_clk = "dpll_iva_m4x2_ck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
|
|
|
|
.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.dev_attr = &mmu_dsp_dev_attr,
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/*
|
|
|
|
* 'mpu' class
|
|
|
|
* mpu sub-system
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
|
2010-12-23 23:30:32 +01:00
|
|
|
.name = "mpu",
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* mpu */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
|
2012-09-24 01:28:30 +02:00
|
|
|
{ .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
|
2010-12-22 05:08:33 +01:00
|
|
|
{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-09-27 16:49:19 +02:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod omap44xx_mpu_hwmod = {
|
|
|
|
.name = "mpu",
|
|
|
|
.class = &omap44xx_mpu_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "mpuss_clkdm",
|
2011-07-10 03:14:28 +02:00
|
|
|
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_mpu_irqs,
|
|
|
|
.main_clk = "dpll_mpu_m2_ck",
|
2010-09-27 16:49:19 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
|
2010-09-27 16:49:19 +02:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:56 +02:00
|
|
|
/*
|
|
|
|
* 'ocmc_ram' class
|
|
|
|
* top-level core on-chip ram
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
|
|
|
|
.name = "ocmc_ram",
|
|
|
|
};
|
|
|
|
|
|
|
|
/* ocmc_ram */
|
|
|
|
static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
|
|
|
|
.name = "ocmc_ram",
|
|
|
|
.class = &omap44xx_ocmc_ram_hwmod_class,
|
|
|
|
.clkdm_name = "l3_2_clkdm",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:55 +02:00
|
|
|
/*
|
|
|
|
* 'ocp2scp' class
|
|
|
|
* bridge to transform ocp interface protocol to scp (serial control port)
|
|
|
|
* protocol
|
|
|
|
*/
|
|
|
|
|
2012-09-24 01:28:21 +02:00
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:55 +02:00
|
|
|
static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
|
|
|
|
.name = "ocp2scp",
|
2012-09-24 01:28:21 +02:00
|
|
|
.sysc = &omap44xx_ocp2scp_sysc,
|
2012-04-19 21:33:55 +02:00
|
|
|
};
|
|
|
|
|
2012-10-27 15:35:55 +02:00
|
|
|
/* ocp2scp dev_attr */
|
|
|
|
static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "usb_phy",
|
|
|
|
.start = 0x4a0ad080,
|
|
|
|
.end = 0x4a0ae000,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* XXX: Remove this once control module driver is in place */
|
|
|
|
.name = "ctrl_dev",
|
|
|
|
.start = 0x4a002300,
|
|
|
|
.end = 0x4a002303,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
|
|
|
|
{
|
|
|
|
.drv_name = "omap-usb2",
|
|
|
|
.res = omap44xx_usb_phy_and_pll_addrs,
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:55 +02:00
|
|
|
/* ocp2scp_usb_phy */
|
|
|
|
static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
|
|
|
|
.name = "ocp2scp_usb_phy",
|
|
|
|
.class = &omap44xx_ocp2scp_hwmod_class,
|
|
|
|
.clkdm_name = "l3_init_clkdm",
|
2012-09-24 01:28:22 +02:00
|
|
|
.main_clk = "ocp2scp_usb_phy_phy_48m",
|
2012-04-19 21:33:55 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
|
|
},
|
|
|
|
},
|
2012-10-27 15:35:55 +02:00
|
|
|
.dev_attr = ocp2scp_dev_attr,
|
2012-04-19 21:33:55 +02:00
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:58 +02:00
|
|
|
/*
|
|
|
|
* 'prcm' class
|
|
|
|
* power and reset manager (part of the prcm infrastructure) + clock manager 2
|
|
|
|
* + clock manager 1 (in always on power domain) + local prm in mpu
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
|
|
|
|
.name = "prcm",
|
|
|
|
};
|
|
|
|
|
|
|
|
/* prcm_mpu */
|
|
|
|
static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
|
|
|
|
.name = "prcm_mpu",
|
|
|
|
.class = &omap44xx_prcm_hwmod_class,
|
|
|
|
.clkdm_name = "l4_wkup_clkdm",
|
2012-09-24 01:28:22 +02:00
|
|
|
.flags = HWMOD_NO_IDLEST,
|
2012-09-24 01:28:20 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
|
},
|
|
|
|
},
|
2012-04-19 21:33:58 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* cm_core_aon */
|
|
|
|
static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
|
|
|
|
.name = "cm_core_aon",
|
|
|
|
.class = &omap44xx_prcm_hwmod_class,
|
2012-09-24 01:28:22 +02:00
|
|
|
.flags = HWMOD_NO_IDLEST,
|
2012-09-24 01:28:20 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
|
},
|
|
|
|
},
|
2012-04-19 21:33:58 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* cm_core */
|
|
|
|
static struct omap_hwmod omap44xx_cm_core_hwmod = {
|
|
|
|
.name = "cm_core",
|
|
|
|
.class = &omap44xx_prcm_hwmod_class,
|
2012-09-24 01:28:22 +02:00
|
|
|
.flags = HWMOD_NO_IDLEST,
|
2012-09-24 01:28:20 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
|
},
|
|
|
|
},
|
2012-04-19 21:33:58 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* prm */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
|
|
|
|
{ .irq = 11 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
|
|
|
|
{ .name = "rst_global_warm_sw", .rst_shift = 0 },
|
|
|
|
{ .name = "rst_global_cold_sw", .rst_shift = 1 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_prm_hwmod = {
|
|
|
|
.name = "prm",
|
|
|
|
.class = &omap44xx_prcm_hwmod_class,
|
|
|
|
.mpu_irqs = omap44xx_prm_irqs,
|
|
|
|
.rst_lines = omap44xx_prm_resets,
|
|
|
|
.rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'scrm' class
|
|
|
|
* system clock and reset manager
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
|
|
|
|
.name = "scrm",
|
|
|
|
};
|
|
|
|
|
|
|
|
/* scrm */
|
|
|
|
static struct omap_hwmod omap44xx_scrm_hwmod = {
|
|
|
|
.name = "scrm",
|
|
|
|
.class = &omap44xx_scrm_hwmod_class,
|
|
|
|
.clkdm_name = "l4_wkup_clkdm",
|
2012-09-24 01:28:20 +02:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
|
},
|
|
|
|
},
|
2012-04-19 21:33:58 +02:00
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
/*
|
|
|
|
* 'sl2if' class
|
|
|
|
* shared level 2 memory interface
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
|
|
|
|
.name = "sl2if",
|
|
|
|
};
|
|
|
|
|
|
|
|
/* sl2if */
|
|
|
|
static struct omap_hwmod omap44xx_sl2if_hwmod = {
|
|
|
|
.name = "sl2if",
|
|
|
|
.class = &omap44xx_sl2if_hwmod_class,
|
|
|
|
.clkdm_name = "ivahd_clkdm",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:53 +02:00
|
|
|
/*
|
|
|
|
* 'slimbus' class
|
|
|
|
* bidirectional, multi-drop, multi-channel two-line serial interface between
|
|
|
|
* the device and external components
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
|
|
|
|
.name = "slimbus",
|
|
|
|
.sysc = &omap44xx_slimbus_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* slimbus1 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
|
|
|
|
{ .irq = 97 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
|
|
|
|
{ .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .dma_req = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
|
|
|
|
{ .role = "fclk_1", .clk = "slimbus1_fclk_1" },
|
|
|
|
{ .role = "fclk_0", .clk = "slimbus1_fclk_0" },
|
|
|
|
{ .role = "fclk_2", .clk = "slimbus1_fclk_2" },
|
|
|
|
{ .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_slimbus1_hwmod = {
|
|
|
|
.name = "slimbus1",
|
|
|
|
.class = &omap44xx_slimbus_hwmod_class,
|
|
|
|
.clkdm_name = "abe_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_slimbus1_irqs,
|
|
|
|
.sdma_reqs = omap44xx_slimbus1_sdma_reqs,
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.opt_clks = slimbus1_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
|
|
|
|
};
|
|
|
|
|
|
|
|
/* slimbus2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
|
|
|
|
{ .irq = 98 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
|
|
|
|
{ .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .dma_req = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
|
|
|
|
{ .role = "fclk_1", .clk = "slimbus2_fclk_1" },
|
|
|
|
{ .role = "fclk_0", .clk = "slimbus2_fclk_0" },
|
|
|
|
{ .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_slimbus2_hwmod = {
|
|
|
|
.name = "slimbus2",
|
|
|
|
.class = &omap44xx_slimbus_hwmod_class,
|
|
|
|
.clkdm_name = "l4_per_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_slimbus2_irqs,
|
|
|
|
.sdma_reqs = omap44xx_slimbus2_sdma_reqs,
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.opt_clks = slimbus2_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
|
|
|
|
};
|
|
|
|
|
2010-12-23 23:30:30 +01:00
|
|
|
/*
|
|
|
|
* 'smartreflex' class
|
|
|
|
* smartreflex module (monitor silicon performance and outputs a measure of
|
|
|
|
* performance error)
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* The IP is not compliant to type1 / type2 scheme */
|
|
|
|
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
|
|
|
|
.sidle_shift = 24,
|
|
|
|
.enwkup_shift = 26,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
|
|
|
|
.sysc_offs = 0x0038,
|
|
|
|
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type_smartreflex,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
|
2010-12-23 23:30:32 +01:00
|
|
|
.name = "smartreflex",
|
|
|
|
.sysc = &omap44xx_smartreflex_sysc,
|
|
|
|
.rev = 2,
|
2010-12-23 23:30:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* smartreflex_core */
|
2012-02-29 23:33:37 +01:00
|
|
|
static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
|
|
|
|
.sensor_voltdm_name = "core",
|
|
|
|
};
|
|
|
|
|
2010-12-23 23:30:30 +01:00
|
|
|
static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
|
|
|
|
{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-23 23:30:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
|
|
|
|
.name = "smartreflex_core",
|
|
|
|
.class = &omap44xx_smartreflex_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_ao_clkdm",
|
2010-12-23 23:30:30 +01:00
|
|
|
.mpu_irqs = omap44xx_smartreflex_core_irqs,
|
2011-07-10 03:14:06 +02:00
|
|
|
|
2010-12-23 23:30:30 +01:00
|
|
|
.main_clk = "smartreflex_core_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-12-23 23:30:30 +01:00
|
|
|
},
|
|
|
|
},
|
2012-02-29 23:33:37 +01:00
|
|
|
.dev_attr = &smartreflex_core_dev_attr,
|
2010-12-23 23:30:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* smartreflex_iva */
|
2012-02-29 23:33:37 +01:00
|
|
|
static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
|
|
|
|
.sensor_voltdm_name = "iva",
|
|
|
|
};
|
|
|
|
|
2010-12-23 23:30:30 +01:00
|
|
|
static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
|
|
|
|
{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-23 23:30:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
|
|
|
|
.name = "smartreflex_iva",
|
|
|
|
.class = &omap44xx_smartreflex_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_ao_clkdm",
|
2010-12-23 23:30:30 +01:00
|
|
|
.mpu_irqs = omap44xx_smartreflex_iva_irqs,
|
|
|
|
.main_clk = "smartreflex_iva_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-12-23 23:30:30 +01:00
|
|
|
},
|
|
|
|
},
|
2012-02-29 23:33:37 +01:00
|
|
|
.dev_attr = &smartreflex_iva_dev_attr,
|
2010-12-23 23:30:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* smartreflex_mpu */
|
2012-02-29 23:33:37 +01:00
|
|
|
static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
|
|
|
|
.sensor_voltdm_name = "mpu",
|
|
|
|
};
|
|
|
|
|
2010-12-23 23:30:30 +01:00
|
|
|
static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
|
|
|
|
{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-23 23:30:30 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
|
|
|
|
.name = "smartreflex_mpu",
|
|
|
|
.class = &omap44xx_smartreflex_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_ao_clkdm",
|
2010-12-23 23:30:30 +01:00
|
|
|
.mpu_irqs = omap44xx_smartreflex_mpu_irqs,
|
|
|
|
.main_clk = "smartreflex_mpu_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-12-23 23:30:30 +01:00
|
|
|
},
|
|
|
|
},
|
2012-02-29 23:33:37 +01:00
|
|
|
.dev_attr = &smartreflex_mpu_dev_attr,
|
2010-12-23 23:30:30 +01:00
|
|
|
};
|
|
|
|
|
2011-02-02 13:04:36 +01:00
|
|
|
/*
|
|
|
|
* 'spinlock' class
|
|
|
|
* spinlock provides hardware assistance for synchronizing the processes
|
|
|
|
* running on multiple processors
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
|
|
|
|
.name = "spinlock",
|
|
|
|
.sysc = &omap44xx_spinlock_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* spinlock */
|
|
|
|
static struct omap_hwmod omap44xx_spinlock_hwmod = {
|
|
|
|
.name = "spinlock",
|
|
|
|
.class = &omap44xx_spinlock_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_cfg_clkdm",
|
2011-02-02 13:04:36 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
|
2011-02-02 13:04:36 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
/*
|
|
|
|
* 'timer' class
|
|
|
|
* general purpose timer module with accurate 1ms tick
|
|
|
|
* This class contains several variants: ['timer_1ms', 'timer']
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
|
|
SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
|
|
SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
|
|
|
|
.name = "timer",
|
|
|
|
.sysc = &omap44xx_timer_1ms_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
|
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
|
|
|
|
.name = "timer",
|
|
|
|
.sysc = &omap44xx_timer_sysc,
|
|
|
|
};
|
|
|
|
|
2011-09-20 13:30:18 +02:00
|
|
|
/* always-on timers dev attribute */
|
|
|
|
static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
|
|
|
|
.timer_capability = OMAP_TIMER_ALWON,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* pwm timers dev attribute */
|
|
|
|
static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
|
|
|
|
.timer_capability = OMAP_TIMER_HAS_PWM,
|
|
|
|
};
|
|
|
|
|
2012-09-24 01:28:27 +02:00
|
|
|
/* timers with DSP interrupt dev attribute */
|
|
|
|
static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
|
|
|
|
.timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* pwm timers with DSP interrupt dev attribute */
|
|
|
|
static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
|
|
|
|
.timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
|
|
|
|
};
|
|
|
|
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
/* timer1 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
|
|
|
|
{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer1_hwmod = {
|
|
|
|
.name = "timer1",
|
|
|
|
.class = &omap44xx_timer_1ms_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_wkup_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer1_irqs,
|
|
|
|
.main_clk = "timer1_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
2011-09-20 13:30:18 +02:00
|
|
|
.dev_attr = &capability_alwon_dev_attr,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* timer2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
|
|
|
|
{ .irq = 38 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer2_hwmod = {
|
|
|
|
.name = "timer2",
|
|
|
|
.class = &omap44xx_timer_1ms_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer2_irqs,
|
|
|
|
.main_clk = "timer2_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* timer3 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
|
|
|
|
{ .irq = 39 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer3_hwmod = {
|
|
|
|
.name = "timer3",
|
|
|
|
.class = &omap44xx_timer_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer3_irqs,
|
|
|
|
.main_clk = "timer3_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* timer4 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
|
|
|
|
{ .irq = 40 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer4_hwmod = {
|
|
|
|
.name = "timer4",
|
|
|
|
.class = &omap44xx_timer_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer4_irqs,
|
|
|
|
.main_clk = "timer4_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* timer5 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
|
|
|
|
{ .irq = 41 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer5_hwmod = {
|
|
|
|
.name = "timer5",
|
|
|
|
.class = &omap44xx_timer_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer5_irqs,
|
|
|
|
.main_clk = "timer5_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
2012-09-24 01:28:27 +02:00
|
|
|
.dev_attr = &capability_dsp_dev_attr,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* timer6 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
|
|
|
|
{ .irq = 42 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer6_hwmod = {
|
|
|
|
.name = "timer6",
|
|
|
|
.class = &omap44xx_timer_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer6_irqs,
|
2011-07-10 03:14:06 +02:00
|
|
|
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.main_clk = "timer6_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
2012-09-24 01:28:27 +02:00
|
|
|
.dev_attr = &capability_dsp_dev_attr,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* timer7 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
|
|
|
|
{ .irq = 43 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer7_hwmod = {
|
|
|
|
.name = "timer7",
|
|
|
|
.class = &omap44xx_timer_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer7_irqs,
|
|
|
|
.main_clk = "timer7_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
2012-09-24 01:28:27 +02:00
|
|
|
.dev_attr = &capability_dsp_dev_attr,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* timer8 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
|
|
|
|
{ .irq = 44 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer8_hwmod = {
|
|
|
|
.name = "timer8",
|
|
|
|
.class = &omap44xx_timer_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer8_irqs,
|
|
|
|
.main_clk = "timer8_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
2012-09-24 01:28:27 +02:00
|
|
|
.dev_attr = &capability_dsp_pwm_dev_attr,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* timer9 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
|
|
|
|
{ .irq = 45 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer9_hwmod = {
|
|
|
|
.name = "timer9",
|
|
|
|
.class = &omap44xx_timer_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer9_irqs,
|
|
|
|
.main_clk = "timer9_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
2011-09-20 13:30:18 +02:00
|
|
|
.dev_attr = &capability_pwm_dev_attr,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* timer10 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
|
|
|
|
{ .irq = 46 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer10_hwmod = {
|
|
|
|
.name = "timer10",
|
|
|
|
.class = &omap44xx_timer_1ms_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer10_irqs,
|
|
|
|
.main_clk = "timer10_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
2011-09-20 13:30:18 +02:00
|
|
|
.dev_attr = &capability_pwm_dev_attr,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* timer11 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
|
|
|
|
{ .irq = 47 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_timer11_hwmod = {
|
|
|
|
.name = "timer11",
|
|
|
|
.class = &omap44xx_timer_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
.mpu_irqs = omap44xx_timer11_irqs,
|
|
|
|
.main_clk = "timer11_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
},
|
|
|
|
},
|
2011-09-20 13:30:18 +02:00
|
|
|
.dev_attr = &capability_pwm_dev_attr,
|
OMAP4: hwmod data: Add timer
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson@ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
2011-02-11 12:17:14 +01:00
|
|
|
};
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
/*
|
2010-12-22 05:08:33 +01:00
|
|
|
* 'uart' class
|
|
|
|
* universal asynchronous receiver/transmitter (uart)
|
2010-12-08 01:26:57 +01:00
|
|
|
*/
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
|
|
|
|
.rev_offs = 0x0050,
|
|
|
|
.sysc_offs = 0x0054,
|
|
|
|
.syss_offs = 0x0058,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
|
2010-12-22 05:08:33 +01:00
|
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
|
|
SYSS_HAS_RESET_STATUS),
|
2010-12-22 05:31:28 +01:00
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
2010-12-08 01:26:57 +01:00
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
|
2010-12-23 23:30:32 +01:00
|
|
|
.name = "uart",
|
|
|
|
.sysc = &omap44xx_uart_sysc,
|
2010-12-08 01:26:57 +01:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* uart1 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
|
|
|
|
{ .irq = 72 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-08 01:26:57 +01:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2010-12-08 01:26:57 +01:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod omap44xx_uart1_hwmod = {
|
|
|
|
.name = "uart1",
|
|
|
|
.class = &omap44xx_uart_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_uart1_irqs,
|
|
|
|
.sdma_reqs = omap44xx_uart1_sdma_reqs,
|
|
|
|
.main_clk = "uart1_fck",
|
2010-12-08 01:26:57 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-12-08 01:26:57 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* uart2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
|
|
|
|
{ .irq = 73 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-08 01:26:57 +01:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_uart2_hwmod = {
|
|
|
|
.name = "uart2",
|
|
|
|
.class = &omap44xx_uart_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_uart2_irqs,
|
|
|
|
.sdma_reqs = omap44xx_uart2_sdma_reqs,
|
|
|
|
.main_clk = "uart2_fck",
|
2010-12-08 01:26:57 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-12-08 01:26:57 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* uart3 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
|
|
|
|
{ .irq = 74 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-08 01:26:57 +01:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_uart3_hwmod = {
|
|
|
|
.name = "uart3",
|
|
|
|
.class = &omap44xx_uart_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2011-07-10 03:14:28 +02:00
|
|
|
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_uart3_irqs,
|
|
|
|
.sdma_reqs = omap44xx_uart3_sdma_reqs,
|
|
|
|
.main_clk = "uart3_fck",
|
2010-12-08 01:26:57 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-12-08 01:26:57 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* uart4 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
|
|
|
|
{ .irq = 70 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-08 01:26:57 +01:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
|
|
|
|
{ .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
|
2011-07-10 03:14:07 +02:00
|
|
|
{ .dma_req = -1 }
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_uart4_hwmod = {
|
|
|
|
.name = "uart4",
|
|
|
|
.class = &omap44xx_uart_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_per_clkdm",
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_uart4_irqs,
|
|
|
|
.sdma_reqs = omap44xx_uart4_sdma_reqs,
|
|
|
|
.main_clk = "uart4_fck",
|
2010-12-08 01:26:57 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-12-08 01:26:57 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:55 +02:00
|
|
|
/*
|
|
|
|
* 'usb_host_fs' class
|
|
|
|
* full-speed usb host controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* The IP is not compliant to type1 / type2 scheme */
|
|
|
|
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
|
|
|
|
.midle_shift = 4,
|
|
|
|
.sidle_shift = 2,
|
|
|
|
.srst_shift = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0210,
|
|
|
|
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
|
|
|
|
.name = "usb_host_fs",
|
|
|
|
.sysc = &omap44xx_usb_host_fs_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* usb_host_fs */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
|
|
|
|
{ .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
|
|
|
|
.name = "usb_host_fs",
|
|
|
|
.class = &omap44xx_usb_host_fs_hwmod_class,
|
|
|
|
.clkdm_name = "l3_init_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_usb_host_fs_irqs,
|
|
|
|
.main_clk = "usb_host_fs_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-02-17 13:41:05 +01:00
|
|
|
/*
|
2012-04-19 12:04:33 +02:00
|
|
|
* 'usb_host_hs' class
|
|
|
|
* high-speed multi-port usb host controller
|
2011-02-17 13:41:05 +01:00
|
|
|
*/
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET),
|
2011-02-17 13:41:05 +01:00
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
2012-04-19 12:04:33 +02:00
|
|
|
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
2011-02-17 13:41:05 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
|
|
|
|
.name = "usb_host_hs",
|
|
|
|
.sysc = &omap44xx_usb_host_hs_sysc,
|
2011-02-17 13:41:05 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* usb_host_hs */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
|
|
|
|
{ .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2011-02-17 13:41:05 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
|
|
|
|
.name = "usb_host_hs",
|
|
|
|
.class = &omap44xx_usb_host_hs_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l3_init_clkdm",
|
2012-04-19 12:04:33 +02:00
|
|
|
.main_clk = "usb_host_hs_fck",
|
2011-02-17 13:41:05 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2012-04-19 12:04:33 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.mpu_irqs = omap44xx_usb_host_hs_irqs,
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
|
|
|
|
* id: i660
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* In the following configuration :
|
|
|
|
* - USBHOST module is set to smart-idle mode
|
|
|
|
* - PRCM asserts idle_req to the USBHOST module ( This typically
|
|
|
|
* happens when the system is going to a low power mode : all ports
|
|
|
|
* have been suspended, the master part of the USBHOST module has
|
|
|
|
* entered the standby state, and SW has cut the functional clocks)
|
|
|
|
* - an USBHOST interrupt occurs before the module is able to answer
|
|
|
|
* idle_ack, typically a remote wakeup IRQ.
|
|
|
|
* Then the USB HOST module will enter a deadlock situation where it
|
|
|
|
* is no more accessible nor functional.
|
|
|
|
*
|
|
|
|
* Workaround:
|
|
|
|
* Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Errata: USB host EHCI may stall when entering smart-standby mode
|
|
|
|
* Id: i571
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* When the USBHOST module is set to smart-standby mode, and when it is
|
|
|
|
* ready to enter the standby state (i.e. all ports are suspended and
|
|
|
|
* all attached devices are in suspend mode), then it can wrongly assert
|
|
|
|
* the Mstandby signal too early while there are still some residual OCP
|
|
|
|
* transactions ongoing. If this condition occurs, the internal state
|
|
|
|
* machine may go to an undefined state and the USB link may be stuck
|
|
|
|
* upon the next resume.
|
|
|
|
*
|
|
|
|
* Workaround:
|
|
|
|
* Don't use smart standby; use only force standby,
|
|
|
|
* hence HWMOD_SWSUP_MSTANDBY
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* During system boot; If the hwmod framework resets the module
|
|
|
|
* the module will have smart idle settings; which can lead to deadlock
|
|
|
|
* (above Errata Id:i660); so, dont reset the module during boot;
|
|
|
|
* Use HWMOD_INIT_NO_RESET.
|
|
|
|
*/
|
|
|
|
|
|
|
|
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
|
|
|
|
HWMOD_INIT_NO_RESET,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'usb_otg_hs' class
|
|
|
|
* high-speed on-the-go universal serial bus (usb_otg_hs) controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
|
|
|
|
.rev_offs = 0x0400,
|
|
|
|
.sysc_offs = 0x0404,
|
|
|
|
.syss_offs = 0x0408,
|
|
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
|
|
|
|
SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
|
|
|
MSTANDBY_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
|
|
|
|
.name = "usb_otg_hs",
|
|
|
|
.sysc = &omap44xx_usb_otg_hs_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* usb_otg_hs */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
|
|
|
|
{ .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
|
|
|
|
{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
|
|
|
|
.name = "usb_otg_hs",
|
|
|
|
.class = &omap44xx_usb_otg_hs_hwmod_class,
|
|
|
|
.clkdm_name = "l3_init_clkdm",
|
|
|
|
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
|
|
|
.mpu_irqs = omap44xx_usb_otg_hs_irqs,
|
|
|
|
.main_clk = "usb_otg_hs_ick",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.opt_clks = usb_otg_hs_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'usb_tll_hs' class
|
|
|
|
* usb_tll_hs module is the adapter on the usb_host_hs ports
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
|
|
|
SYSC_HAS_AUTOIDLE),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
|
|
|
|
.name = "usb_tll_hs",
|
|
|
|
.sysc = &omap44xx_usb_tll_hs_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
|
|
|
|
{ .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
{ .irq = -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
|
|
|
|
.name = "usb_tll_hs",
|
|
|
|
.class = &omap44xx_usb_tll_hs_hwmod_class,
|
|
|
|
.clkdm_name = "l3_init_clkdm",
|
|
|
|
.mpu_irqs = omap44xx_usb_tll_hs_irqs,
|
|
|
|
.main_clk = "usb_tll_hs_ick",
|
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
|
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
|
|
|
|
.context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
|
|
|
|
.modulemode = MODULEMODE_HWCTRL,
|
2011-02-17 13:41:05 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/*
|
|
|
|
* 'wd_timer' class
|
|
|
|
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
|
|
|
|
* overflow condition
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
|
|
|
|
.rev_offs = 0x0000,
|
|
|
|
.sysc_offs = 0x0010,
|
|
|
|
.syss_offs = 0x0014,
|
|
|
|
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
|
2010-12-22 05:08:33 +01:00
|
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
2010-12-22 05:31:28 +01:00
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
SIDLE_SMART_WKUP),
|
2010-12-22 05:08:33 +01:00
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
2010-12-08 01:26:57 +01:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
|
|
|
|
.name = "wd_timer",
|
|
|
|
.sysc = &omap44xx_wd_timer_sysc,
|
2010-12-23 23:30:32 +01:00
|
|
|
.pre_shutdown = &omap2_wd_timer_disable,
|
ARM: OMAP2+: WDTIMER integration: fix !PM boot crash, disarm timer after hwmod reset
Without runtime PM enabled, hwmod needs to leave all IP blocks in an
enabled state by default so any driver access to the HW will succeed.
This is accomplished by seting the postsetup_state to enabled for all
hwmods during init when runtime PM is disabled.
Currently, we have a special case for WDT in that its postsetup_state
is always set to disabled. This is done so that the WDT is disabled
and the timer is disarmed at boot in case there is no WDT driver.
This also means that when runtime PM is disabled, if a WDT driver *is*
built in the kernel, the kernel will crash on the first access to the
WDT hardware.
We can't simply leave the WDT module enabled, because the timer is
armed by default after reset. That means that if there is no WDT
driver initialzed or loaded before the timer expires, the kernel will
reboot.
To fix this, a custom reset method is added to the watchdog class of
omap_hwmod. This method will *always* disarm the timer after hwmod
reset. The WDT timer then will only be rearmed when/if the driver is
loaded for the WDT. With the timer disarmed by default, we no longer
need a special-case for the postsetup_state of WDT during init, so it
is removed.
Any platforms wishing to ensure the watchdog remains armed across the
entire boot boot can simply disable the reset-on-init feature of the
watchdog hwmod using omap_hwmod_no_setup_reset().
Tested on 3530/Overo, 4430/Panda.
NOTE: on 4430, the hwmod OCP reset does not seem to rearm the timer as
documented in the TRM (and what happens on OMAP3.) I noticed this
because testing the HWMOD_INIT_NO_RESET feature with no driver loaded,
I expected a reboot part way through the boot, but did not see a
reboot. Adding some debug to read the counter, I verified that right
after OCP softreset, the counter is not firing. After writing the
magic start sequence, the timer starts counting. This means that the
timer disarm sequence added here does not seem to be needed for 4430,
but is technically the correct way to ensure the timer is disarmed, so
it is left in for OMAP4.
Special thanks to Paul Walmsley for helping brainstorm ideas to fix
this problem.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[paul@pwsan.com: updated the omap2_wd_timer_reset() function in the
wake of commit 3c55c1baffa5f719eb2ae9729088bc867f972f53 ("ARM:
OMAP2+: hwmod: Revert "ARM: OMAP2+: hwmod: Make omap_hwmod_softreset
wait for reset status""); added kerneldoc; rolled in warning fix from Kevin]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-05-08 19:34:30 +02:00
|
|
|
.reset = &omap2_wd_timer_reset,
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/* wd_timer2 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
|
|
|
|
{ .irq = 80 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-22 05:08:33 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
|
|
|
|
.name = "wd_timer2",
|
|
|
|
.class = &omap44xx_wd_timer_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "l4_wkup_clkdm",
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_wd_timer2_irqs,
|
|
|
|
.main_clk = "wd_timer2_fck",
|
2010-12-08 01:26:57 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-12-08 01:26:57 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
/* wd_timer3 */
|
|
|
|
static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
|
|
|
|
{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
|
2011-07-10 03:14:06 +02:00
|
|
|
{ .irq = -1 }
|
2010-12-08 01:26:57 +01:00
|
|
|
};
|
|
|
|
|
2010-12-22 05:08:33 +01:00
|
|
|
static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
|
|
|
|
.name = "wd_timer3",
|
|
|
|
.class = &omap44xx_wd_timer_hwmod_class,
|
2011-07-10 13:56:29 +02:00
|
|
|
.clkdm_name = "abe_clkdm",
|
2010-12-22 05:08:33 +01:00
|
|
|
.mpu_irqs = omap44xx_wd_timer3_irqs,
|
|
|
|
.main_clk = "wd_timer3_fck",
|
2010-12-08 01:26:57 +01:00
|
|
|
.prcm = {
|
|
|
|
.omap4 = {
|
2011-07-10 13:56:30 +02:00
|
|
|
.clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
|
2011-07-10 13:56:32 +02:00
|
|
|
.modulemode = MODULEMODE_SWCTRL,
|
2010-12-08 01:26:57 +01:00
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
2010-12-21 03:27:19 +01:00
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
|
2011-12-16 07:15:18 +01:00
|
|
|
/*
|
2012-04-19 12:04:33 +02:00
|
|
|
* interfaces
|
2011-12-16 07:15:18 +01:00
|
|
|
*/
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a204000,
|
|
|
|
.pa_end = 0x4a2040ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* c2c -> c2c_target_fw */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
|
|
|
|
.master = &omap44xx_c2c_hwmod,
|
|
|
|
.slave = &omap44xx_c2c_target_fw_hwmod,
|
|
|
|
.clk = "div_core_ck",
|
|
|
|
.addr = omap44xx_c2c_target_fw_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> c2c_target_fw */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_c2c_target_fw_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* l3_main_1 -> dmm */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
|
|
|
|
.master = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.slave = &omap44xx_dmm_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_SDMA,
|
2011-12-16 07:15:18 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
|
2011-12-16 07:15:18 +01:00
|
|
|
{
|
2012-04-19 12:04:33 +02:00
|
|
|
.pa_start = 0x4e000000,
|
|
|
|
.pa_end = 0x4e0007ff,
|
2011-12-16 07:15:18 +01:00
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
2012-04-19 12:04:33 +02:00
|
|
|
{ }
|
2011-12-16 07:15:18 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* mpu -> dmm */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
|
|
|
|
.master = &omap44xx_mpu_hwmod,
|
|
|
|
.slave = &omap44xx_dmm_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_dmm_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
2011-12-16 07:15:18 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
/* c2c -> emif_fw */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
|
|
|
|
.master = &omap44xx_c2c_hwmod,
|
|
|
|
.slave = &omap44xx_emif_fw_hwmod,
|
|
|
|
.clk = "div_core_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* dmm -> emif_fw */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
|
|
|
|
.master = &omap44xx_dmm_hwmod,
|
|
|
|
.slave = &omap44xx_emif_fw_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a20c000,
|
|
|
|
.pa_end = 0x4a20c0ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> emif_fw */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_emif_fw_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_emif_fw_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* iva -> l3_instr */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
|
|
|
|
.master = &omap44xx_iva_hwmod,
|
|
|
|
.slave = &omap44xx_l3_instr_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_3 -> l3_instr */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
|
|
|
|
.master = &omap44xx_l3_main_3_hwmod,
|
|
|
|
.slave = &omap44xx_l3_instr_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:56 +02:00
|
|
|
/* ocp_wp_noc -> l3_instr */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
|
|
|
|
.master = &omap44xx_ocp_wp_noc_hwmod,
|
|
|
|
.slave = &omap44xx_l3_instr_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* dsp -> l3_main_1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
|
|
|
|
.master = &omap44xx_dsp_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dss -> l3_main_1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
|
|
|
|
.master = &omap44xx_dss_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> l3_main_1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> l3_main_1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mmc1 -> l3_main_1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
|
|
|
|
.master = &omap44xx_mmc1_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mmc2 -> l3_main_1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
|
|
|
|
.master = &omap44xx_mmc2_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x44000000,
|
|
|
|
.pa_end = 0x44000fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mpu -> l3_main_1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
|
|
|
|
.master = &omap44xx_mpu_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_l3_main_1_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
/* c2c_target_fw -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
|
|
|
|
.master = &omap44xx_c2c_target_fw_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:59 +02:00
|
|
|
/* debugss -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
|
|
|
|
.master = &omap44xx_debugss_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "dbgclk_mux_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* dma_system -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
|
|
|
|
.master = &omap44xx_dma_system_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:50 +02:00
|
|
|
/* fdif -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
|
|
|
|
.master = &omap44xx_fdif_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:53 +02:00
|
|
|
/* gpu -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
|
|
|
|
.master = &omap44xx_gpu_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* hsi -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
|
|
|
|
.master = &omap44xx_hsi_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* ipu -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
|
|
|
|
.master = &omap44xx_ipu_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* iss -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
|
|
|
|
.master = &omap44xx_iss_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* iva -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
|
|
|
|
.master = &omap44xx_iva_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x44800000,
|
|
|
|
.pa_end = 0x44801fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_1 -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
|
|
|
|
.master = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_l3_main_2_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:55 +02:00
|
|
|
/* usb_host_fs -> l3_main_2 */
|
2012-07-04 14:55:29 +02:00
|
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
|
2012-04-19 21:33:55 +02:00
|
|
|
.master = &omap44xx_usb_host_fs_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* usb_host_hs -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
|
|
|
|
.master = &omap44xx_usb_host_hs_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* usb_otg_hs -> l3_main_2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
|
|
|
|
.master = &omap44xx_usb_otg_hs_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x45000000,
|
|
|
|
.pa_end = 0x45000fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_1 -> l3_main_3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
|
|
|
|
.master = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_3_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_l3_main_3_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> l3_main_3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_3_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> l3_main_3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_l3_main_3_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* aess -> l4_abe */
|
2012-07-04 14:55:29 +02:00
|
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
|
2012-04-19 12:04:33 +02:00
|
|
|
.master = &omap44xx_aess_hwmod,
|
|
|
|
.slave = &omap44xx_l4_abe_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dsp -> l4_abe */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
|
|
|
|
.master = &omap44xx_dsp_hwmod,
|
|
|
|
.slave = &omap44xx_l4_abe_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_1 -> l4_abe */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
|
|
|
|
.master = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.slave = &omap44xx_l4_abe_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mpu -> l4_abe */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
|
|
|
|
.master = &omap44xx_mpu_hwmod,
|
|
|
|
.slave = &omap44xx_l4_abe_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_1 -> l4_cfg */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
|
|
|
|
.master = &omap44xx_l3_main_1_hwmod,
|
|
|
|
.slave = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> l4_per */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_l4_per_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> l4_wkup */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mpu -> mpu_private */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
|
|
|
|
.master = &omap44xx_mpu_hwmod,
|
|
|
|
.slave = &omap44xx_mpu_private_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:56 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a102000,
|
|
|
|
.pa_end = 0x4a10207f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> ocp_wp_noc */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_ocp_wp_noc_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_ocp_wp_noc_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x401f1000,
|
|
|
|
.pa_end = 0x401f13ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> aess */
|
2012-07-04 14:55:29 +02:00
|
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
|
2012-04-19 12:04:33 +02:00
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_aess_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_aess_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x490f1000,
|
|
|
|
.pa_end = 0x490f13ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> aess (dma) */
|
2012-07-04 14:55:29 +02:00
|
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
|
2012-04-19 12:04:33 +02:00
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_aess_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_aess_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
/* l3_main_2 -> c2c */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_c2c_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a304000,
|
|
|
|
.pa_end = 0x4a30401f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> counter_32k */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
|
|
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap44xx_counter_32k_hwmod,
|
|
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
|
|
.addr = omap44xx_counter_32k_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:57 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a002000,
|
|
|
|
.pa_end = 0x4a0027ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> ctrl_module_core */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_ctrl_module_core_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_ctrl_module_core_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a100000,
|
|
|
|
.pa_end = 0x4a1007ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> ctrl_module_pad_core */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_ctrl_module_pad_core_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_ctrl_module_pad_core_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a30c000,
|
|
|
|
.pa_end = 0x4a30c7ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> ctrl_module_wkup */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
|
|
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap44xx_ctrl_module_wkup_hwmod,
|
|
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
|
|
.addr = omap44xx_ctrl_module_wkup_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a31e000,
|
|
|
|
.pa_end = 0x4a31e7ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> ctrl_module_pad_wkup */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
|
|
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
|
|
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
|
|
.addr = omap44xx_ctrl_module_pad_wkup_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:59 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x54160000,
|
|
|
|
.pa_end = 0x54167fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_instr -> debugss */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
|
|
|
|
.master = &omap44xx_l3_instr_hwmod,
|
|
|
|
.slave = &omap44xx_debugss_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_debugss_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a056000,
|
|
|
|
.pa_end = 0x4a056fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> dma_system */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_dma_system_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_dma_system_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "mpu",
|
|
|
|
.pa_start = 0x4012e000,
|
|
|
|
.pa_end = 0x4012e07f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> dmic */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_dmic_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_dmic_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "dma",
|
|
|
|
.pa_start = 0x4902e000,
|
|
|
|
.pa_end = 0x4902e07f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> dmic (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_dmic_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_dmic_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dsp -> iva */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
|
|
|
|
.master = &omap44xx_dsp_hwmod,
|
|
|
|
.slave = &omap44xx_iva_hwmod,
|
|
|
|
.clk = "dpll_iva_m5x2_ck",
|
|
|
|
.user = OCP_USER_DSP,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
/* dsp -> sl2if */
|
2012-09-03 19:50:53 +02:00
|
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
|
2012-04-19 21:33:54 +02:00
|
|
|
.master = &omap44xx_dsp_hwmod,
|
|
|
|
.slave = &omap44xx_sl2if_hwmod,
|
|
|
|
.clk = "dpll_iva_m5x2_ck",
|
|
|
|
.user = OCP_USER_DSP,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* l4_cfg -> dsp */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_dsp_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x58000000,
|
|
|
|
.pa_end = 0x5800007f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> dss */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_dss_hwmod,
|
|
|
|
.clk = "dss_fck",
|
|
|
|
.addr = omap44xx_dss_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48040000,
|
|
|
|
.pa_end = 0x4804007f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> dss */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_dss_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_dss_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x58001000,
|
|
|
|
.pa_end = 0x58001fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> dss_dispc */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_dss_dispc_hwmod,
|
|
|
|
.clk = "dss_fck",
|
|
|
|
.addr = omap44xx_dss_dispc_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48041000,
|
|
|
|
.pa_end = 0x48041fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> dss_dispc */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_dss_dispc_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_dss_dispc_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x58004000,
|
|
|
|
.pa_end = 0x580041ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> dss_dsi1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_dss_dsi1_hwmod,
|
|
|
|
.clk = "dss_fck",
|
|
|
|
.addr = omap44xx_dss_dsi1_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48044000,
|
|
|
|
.pa_end = 0x480441ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> dss_dsi1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_dss_dsi1_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_dss_dsi1_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x58005000,
|
|
|
|
.pa_end = 0x580051ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> dss_dsi2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_dss_dsi2_hwmod,
|
|
|
|
.clk = "dss_fck",
|
|
|
|
.addr = omap44xx_dss_dsi2_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48045000,
|
|
|
|
.pa_end = 0x480451ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> dss_dsi2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_dss_dsi2_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_dss_dsi2_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x58006000,
|
|
|
|
.pa_end = 0x58006fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> dss_hdmi */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_dss_hdmi_hwmod,
|
|
|
|
.clk = "dss_fck",
|
|
|
|
.addr = omap44xx_dss_hdmi_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48046000,
|
|
|
|
.pa_end = 0x48046fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> dss_hdmi */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_dss_hdmi_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_dss_hdmi_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x58002000,
|
|
|
|
.pa_end = 0x580020ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> dss_rfbi */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_dss_rfbi_hwmod,
|
|
|
|
.clk = "dss_fck",
|
|
|
|
.addr = omap44xx_dss_rfbi_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48042000,
|
|
|
|
.pa_end = 0x480420ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> dss_rfbi */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_dss_rfbi_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_dss_rfbi_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x58003000,
|
|
|
|
.pa_end = 0x580030ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> dss_venc */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_dss_venc_hwmod,
|
|
|
|
.clk = "dss_fck",
|
|
|
|
.addr = omap44xx_dss_venc_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48043000,
|
|
|
|
.pa_end = 0x480430ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> dss_venc */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_dss_venc_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_dss_venc_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48078000,
|
|
|
|
.pa_end = 0x48078fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> elm */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_elm_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_elm_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:52 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4c000000,
|
|
|
|
.pa_end = 0x4c0000ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* emif_fw -> emif1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
|
|
|
|
.master = &omap44xx_emif_fw_hwmod,
|
|
|
|
.slave = &omap44xx_emif1_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_emif1_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4d000000,
|
|
|
|
.pa_end = 0x4d0000ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* emif_fw -> emif2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
|
|
|
|
.master = &omap44xx_emif_fw_hwmod,
|
|
|
|
.slave = &omap44xx_emif2_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_emif2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:50 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a10a000,
|
|
|
|
.pa_end = 0x4a10a1ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> fdif */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_fdif_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_fdif_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a310000,
|
|
|
|
.pa_end = 0x4a3101ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> gpio1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
|
|
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap44xx_gpio1_hwmod,
|
|
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
|
|
.addr = omap44xx_gpio1_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48055000,
|
|
|
|
.pa_end = 0x480551ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> gpio2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_gpio2_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_gpio2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48057000,
|
|
|
|
.pa_end = 0x480571ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> gpio3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_gpio3_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_gpio3_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48059000,
|
|
|
|
.pa_end = 0x480591ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> gpio4 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_gpio4_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_gpio4_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4805b000,
|
|
|
|
.pa_end = 0x4805b1ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> gpio5 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_gpio5_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_gpio5_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4805d000,
|
|
|
|
.pa_end = 0x4805d1ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> gpio6 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_gpio6_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_gpio6_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:51 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x50000000,
|
|
|
|
.pa_end = 0x500003ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> gpmc */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_gpmc_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_gpmc_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:53 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x56000000,
|
|
|
|
.pa_end = 0x5600ffff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> gpu */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_gpu_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_gpu_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:50 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x480b2000,
|
|
|
|
.pa_end = 0x480b201f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> hdq1w */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_hdq1w_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_hdq1w_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a058000,
|
|
|
|
.pa_end = 0x4a05bfff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> hsi */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_hsi_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_hsi_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48070000,
|
|
|
|
.pa_end = 0x480700ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> i2c1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_i2c1_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_i2c1_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48072000,
|
|
|
|
.pa_end = 0x480720ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> i2c2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_i2c2_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_i2c2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48060000,
|
|
|
|
.pa_end = 0x480600ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> i2c3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_i2c3_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_i2c3_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48350000,
|
|
|
|
.pa_end = 0x483500ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> i2c4 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_i2c4_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_i2c4_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> ipu */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_ipu_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x52000000,
|
|
|
|
.pa_end = 0x520000ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> iss */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_iss_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_iss_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
/* iva -> sl2if */
|
2012-09-03 19:50:53 +02:00
|
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
|
2012-04-19 21:33:54 +02:00
|
|
|
.master = &omap44xx_iva_hwmod,
|
|
|
|
.slave = &omap44xx_sl2if_hwmod,
|
|
|
|
.clk = "dpll_iva_m5x2_ck",
|
|
|
|
.user = OCP_USER_IVA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x5a000000,
|
|
|
|
.pa_end = 0x5a07ffff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l3_main_2 -> iva */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_iva_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_iva_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a31c000,
|
|
|
|
.pa_end = 0x4a31c07f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> kbd */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
|
|
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap44xx_kbd_hwmod,
|
|
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
|
|
.addr = omap44xx_kbd_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a0f4000,
|
|
|
|
.pa_end = 0x4a0f41ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> mailbox */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_mailbox_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mailbox_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x40128000,
|
|
|
|
.pa_end = 0x401283ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> mcasp */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_mcasp_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_mcasp_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x49028000,
|
|
|
|
.pa_end = 0x490283ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> mcasp (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_mcasp_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_mcasp_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "mpu",
|
|
|
|
.pa_start = 0x40122000,
|
|
|
|
.pa_end = 0x401220ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> mcbsp1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_mcbsp1_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_mcbsp1_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "dma",
|
|
|
|
.pa_start = 0x49022000,
|
|
|
|
.pa_end = 0x490220ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> mcbsp1 (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_mcbsp1_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_mcbsp1_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "mpu",
|
|
|
|
.pa_start = 0x40124000,
|
|
|
|
.pa_end = 0x401240ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> mcbsp2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_mcbsp2_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_mcbsp2_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "dma",
|
|
|
|
.pa_start = 0x49024000,
|
|
|
|
.pa_end = 0x490240ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> mcbsp2 (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_mcbsp2_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_mcbsp2_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "mpu",
|
|
|
|
.pa_start = 0x40126000,
|
|
|
|
.pa_end = 0x401260ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> mcbsp3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_mcbsp3_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_mcbsp3_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "dma",
|
|
|
|
.pa_start = 0x49026000,
|
|
|
|
.pa_end = 0x490260ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> mcbsp3 (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_mcbsp3_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_mcbsp3_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48096000,
|
|
|
|
.pa_end = 0x480960ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> mcbsp4 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_mcbsp4_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mcbsp4_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
|
|
|
|
{
|
2012-09-14 14:05:53 +02:00
|
|
|
.name = "mpu",
|
2012-04-19 12:04:33 +02:00
|
|
|
.pa_start = 0x40132000,
|
|
|
|
.pa_end = 0x4013207f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> mcpdm */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_mcpdm_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_mcpdm_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
|
|
|
|
{
|
2012-09-14 14:05:53 +02:00
|
|
|
.name = "dma",
|
2012-04-19 12:04:33 +02:00
|
|
|
.pa_start = 0x49032000,
|
|
|
|
.pa_end = 0x4903207f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> mcpdm (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_mcpdm_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_mcpdm_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48098000,
|
|
|
|
.pa_end = 0x480981ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> mcspi1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_mcspi1_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mcspi1_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4809a000,
|
|
|
|
.pa_end = 0x4809a1ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> mcspi2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_mcspi2_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mcspi2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x480b8000,
|
|
|
|
.pa_end = 0x480b81ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> mcspi3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_mcspi3_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mcspi3_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x480ba000,
|
|
|
|
.pa_end = 0x480ba1ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> mcspi4 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_mcspi4_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mcspi4_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4809c000,
|
|
|
|
.pa_end = 0x4809c3ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> mmc1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_mmc1_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mmc1_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x480b4000,
|
|
|
|
.pa_end = 0x480b43ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> mmc2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_mmc2_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mmc2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x480ad000,
|
|
|
|
.pa_end = 0x480ad3ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> mmc3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_mmc3_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mmc3_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x480d1000,
|
|
|
|
.pa_end = 0x480d13ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> mmc4 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_mmc4_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mmc4_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x480d5000,
|
|
|
|
.pa_end = 0x480d53ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> mmc5 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_mmc5_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_mmc5_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:56 +02:00
|
|
|
/* l3_main_2 -> ocmc_ram */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
|
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_ocmc_ram_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-09-24 01:28:21 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a0ad000,
|
|
|
|
.pa_end = 0x4a0ad01f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:55 +02:00
|
|
|
/* l4_cfg -> ocp2scp_usb_phy */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_ocp2scp_usb_phy_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
2012-09-24 01:28:21 +02:00
|
|
|
.addr = omap44xx_ocp2scp_usb_phy_addrs,
|
2012-04-19 21:33:55 +02:00
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:58 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48243000,
|
|
|
|
.pa_end = 0x48243fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mpu_private -> prcm_mpu */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
|
|
|
|
.master = &omap44xx_mpu_private_hwmod,
|
|
|
|
.slave = &omap44xx_prcm_mpu_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.addr = omap44xx_prcm_mpu_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a004000,
|
|
|
|
.pa_end = 0x4a004fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> cm_core_aon */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
|
|
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap44xx_cm_core_aon_hwmod,
|
|
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
|
|
.addr = omap44xx_cm_core_aon_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a008000,
|
|
|
|
.pa_end = 0x4a009fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> cm_core */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_cm_core_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_cm_core_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a306000,
|
|
|
|
.pa_end = 0x4a307fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> prm */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
|
|
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap44xx_prm_hwmod,
|
|
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
|
|
.addr = omap44xx_prm_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a30a000,
|
|
|
|
.pa_end = 0x4a30a7ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> scrm */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
|
|
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap44xx_scrm_hwmod,
|
|
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
|
|
.addr = omap44xx_scrm_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:54 +02:00
|
|
|
/* l3_main_2 -> sl2if */
|
2012-09-03 19:50:53 +02:00
|
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
|
2012-04-19 21:33:54 +02:00
|
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
|
|
.slave = &omap44xx_sl2if_hwmod,
|
|
|
|
.clk = "l3_div_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:53 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4012c000,
|
|
|
|
.pa_end = 0x4012c3ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> slimbus1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_slimbus1_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_slimbus1_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4902c000,
|
|
|
|
.pa_end = 0x4902c3ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> slimbus1 (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_slimbus1_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_slimbus1_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48076000,
|
|
|
|
.pa_end = 0x480763ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> slimbus2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_slimbus2_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_slimbus2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a0dd000,
|
|
|
|
.pa_end = 0x4a0dd03f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> smartreflex_core */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_smartreflex_core_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_smartreflex_core_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a0db000,
|
|
|
|
.pa_end = 0x4a0db03f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> smartreflex_iva */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_smartreflex_iva_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_smartreflex_iva_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a0d9000,
|
|
|
|
.pa_end = 0x4a0d903f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> smartreflex_mpu */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_smartreflex_mpu_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_smartreflex_mpu_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a0f6000,
|
|
|
|
.pa_end = 0x4a0f6fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> spinlock */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_spinlock_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_spinlock_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a318000,
|
|
|
|
.pa_end = 0x4a31807f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> timer1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
|
|
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap44xx_timer1_hwmod,
|
|
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
|
|
.addr = omap44xx_timer1_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48032000,
|
|
|
|
.pa_end = 0x4803207f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> timer2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_timer2_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_timer2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48034000,
|
|
|
|
.pa_end = 0x4803407f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> timer3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_timer3_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_timer3_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48036000,
|
|
|
|
.pa_end = 0x4803607f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> timer4 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_timer4_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_timer4_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x40138000,
|
|
|
|
.pa_end = 0x4013807f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> timer5 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_timer5_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_timer5_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x49038000,
|
|
|
|
.pa_end = 0x4903807f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> timer5 (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_timer5_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_timer5_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4013a000,
|
|
|
|
.pa_end = 0x4013a07f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> timer6 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_timer6_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_timer6_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4903a000,
|
|
|
|
.pa_end = 0x4903a07f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> timer6 (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_timer6_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_timer6_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4013c000,
|
|
|
|
.pa_end = 0x4013c07f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> timer7 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_timer7_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_timer7_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4903c000,
|
|
|
|
.pa_end = 0x4903c07f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> timer7 (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_timer7_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_timer7_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4013e000,
|
|
|
|
.pa_end = 0x4013e07f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> timer8 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_timer8_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_timer8_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4903e000,
|
|
|
|
.pa_end = 0x4903e07f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> timer8 (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_timer8_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_timer8_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4803e000,
|
|
|
|
.pa_end = 0x4803e07f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> timer9 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_timer9_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_timer9_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48086000,
|
|
|
|
.pa_end = 0x4808607f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> timer10 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_timer10_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_timer10_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48088000,
|
|
|
|
.pa_end = 0x4808807f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_per -> timer11 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_timer11_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_timer11_addrs,
|
2011-12-16 07:15:18 +01:00
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4806a000,
|
|
|
|
.pa_end = 0x4806a0ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
2011-12-16 07:15:18 +01:00
|
|
|
},
|
2012-04-19 12:04:33 +02:00
|
|
|
{ }
|
|
|
|
};
|
2011-12-16 07:15:18 +01:00
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* l4_per -> uart1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_uart1_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_uart1_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
2011-12-16 07:15:18 +01:00
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4806c000,
|
|
|
|
.pa_end = 0x4806c0ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
2011-12-16 07:15:18 +01:00
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* l4_per -> uart2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_uart2_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_uart2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
2011-12-16 07:15:18 +01:00
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x48020000,
|
|
|
|
.pa_end = 0x480200ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
2011-12-16 07:15:18 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* l4_per -> uart3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_uart3_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_uart3_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
2011-12-16 07:15:18 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4806e000,
|
|
|
|
.pa_end = 0x4806e0ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
2011-12-16 07:15:18 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* l4_per -> uart4 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
|
|
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
|
|
.slave = &omap44xx_uart4_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_uart4_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 21:33:55 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a0a9000,
|
|
|
|
.pa_end = 0x4a0a93ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> usb_host_fs */
|
2012-07-04 14:55:29 +02:00
|
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
|
2012-04-19 21:33:55 +02:00
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_usb_host_fs_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_usb_host_fs_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "uhh",
|
|
|
|
.pa_start = 0x4a064000,
|
|
|
|
.pa_end = 0x4a0647ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "ohci",
|
|
|
|
.pa_start = 0x4a064800,
|
|
|
|
.pa_end = 0x4a064bff,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "ehci",
|
|
|
|
.pa_start = 0x4a064c00,
|
|
|
|
.pa_end = 0x4a064fff,
|
|
|
|
},
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> usb_host_hs */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_usb_host_hs_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_usb_host_hs_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a0ab000,
|
2012-09-24 01:28:21 +02:00
|
|
|
.pa_end = 0x4a0ab7ff,
|
2012-04-19 12:04:33 +02:00
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
2012-09-11 11:09:38 +02:00
|
|
|
{
|
|
|
|
/* XXX: Remove this once control module driver is in place */
|
|
|
|
.pa_start = 0x4a00233c,
|
|
|
|
.pa_end = 0x4a00233f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
2012-04-19 12:04:33 +02:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_cfg -> usb_otg_hs */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_usb_otg_hs_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_usb_otg_hs_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
2011-12-16 07:15:18 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "tll",
|
|
|
|
.pa_start = 0x4a062000,
|
|
|
|
.pa_end = 0x4a063fff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
/* l4_cfg -> usb_tll_hs */
|
2011-12-16 07:15:18 +01:00
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
|
|
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
|
|
.slave = &omap44xx_usb_tll_hs_hwmod,
|
|
|
|
.clk = "l4_div_ck",
|
|
|
|
.addr = omap44xx_usb_tll_hs_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:33 +02:00
|
|
|
static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4a314000,
|
|
|
|
.pa_end = 0x4a31407f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
2011-12-16 07:15:18 +01:00
|
|
|
},
|
2012-04-19 12:04:33 +02:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> wd_timer2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
|
|
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap44xx_wd_timer2_hwmod,
|
|
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
|
|
.addr = omap44xx_wd_timer2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x40130000,
|
|
|
|
.pa_end = 0x4013007f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> wd_timer3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_wd_timer3_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_wd_timer3_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x49030000,
|
|
|
|
.pa_end = 0x4903007f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_abe -> wd_timer3 (dma) */
|
|
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
|
|
|
|
.master = &omap44xx_l4_abe_hwmod,
|
|
|
|
.slave = &omap44xx_wd_timer3_hwmod,
|
|
|
|
.clk = "ocp_abe_iclk",
|
|
|
|
.addr = omap44xx_wd_timer3_dma_addrs,
|
|
|
|
.user = OCP_USER_SDMA,
|
2011-12-16 07:15:18 +01:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:04:31 +02:00
|
|
|
static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
|
2012-04-19 21:33:54 +02:00
|
|
|
&omap44xx_c2c__c2c_target_fw,
|
|
|
|
&omap44xx_l4_cfg__c2c_target_fw,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_l3_main_1__dmm,
|
|
|
|
&omap44xx_mpu__dmm,
|
2012-04-19 21:33:54 +02:00
|
|
|
&omap44xx_c2c__emif_fw,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_dmm__emif_fw,
|
|
|
|
&omap44xx_l4_cfg__emif_fw,
|
|
|
|
&omap44xx_iva__l3_instr,
|
|
|
|
&omap44xx_l3_main_3__l3_instr,
|
2012-04-19 21:33:56 +02:00
|
|
|
&omap44xx_ocp_wp_noc__l3_instr,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_dsp__l3_main_1,
|
|
|
|
&omap44xx_dss__l3_main_1,
|
|
|
|
&omap44xx_l3_main_2__l3_main_1,
|
|
|
|
&omap44xx_l4_cfg__l3_main_1,
|
|
|
|
&omap44xx_mmc1__l3_main_1,
|
|
|
|
&omap44xx_mmc2__l3_main_1,
|
|
|
|
&omap44xx_mpu__l3_main_1,
|
2012-04-19 21:33:54 +02:00
|
|
|
&omap44xx_c2c_target_fw__l3_main_2,
|
2012-04-19 21:33:59 +02:00
|
|
|
&omap44xx_debugss__l3_main_2,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_dma_system__l3_main_2,
|
2012-04-19 21:33:50 +02:00
|
|
|
&omap44xx_fdif__l3_main_2,
|
2012-04-19 21:33:53 +02:00
|
|
|
&omap44xx_gpu__l3_main_2,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_hsi__l3_main_2,
|
|
|
|
&omap44xx_ipu__l3_main_2,
|
|
|
|
&omap44xx_iss__l3_main_2,
|
|
|
|
&omap44xx_iva__l3_main_2,
|
|
|
|
&omap44xx_l3_main_1__l3_main_2,
|
|
|
|
&omap44xx_l4_cfg__l3_main_2,
|
2012-07-04 14:55:29 +02:00
|
|
|
/* &omap44xx_usb_host_fs__l3_main_2, */
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_usb_host_hs__l3_main_2,
|
|
|
|
&omap44xx_usb_otg_hs__l3_main_2,
|
|
|
|
&omap44xx_l3_main_1__l3_main_3,
|
|
|
|
&omap44xx_l3_main_2__l3_main_3,
|
|
|
|
&omap44xx_l4_cfg__l3_main_3,
|
2012-07-04 14:55:29 +02:00
|
|
|
/* &omap44xx_aess__l4_abe, */
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_dsp__l4_abe,
|
|
|
|
&omap44xx_l3_main_1__l4_abe,
|
|
|
|
&omap44xx_mpu__l4_abe,
|
|
|
|
&omap44xx_l3_main_1__l4_cfg,
|
|
|
|
&omap44xx_l3_main_2__l4_per,
|
|
|
|
&omap44xx_l4_cfg__l4_wkup,
|
|
|
|
&omap44xx_mpu__mpu_private,
|
2012-04-19 21:33:56 +02:00
|
|
|
&omap44xx_l4_cfg__ocp_wp_noc,
|
2012-07-04 14:55:29 +02:00
|
|
|
/* &omap44xx_l4_abe__aess, */
|
|
|
|
/* &omap44xx_l4_abe__aess_dma, */
|
2012-04-19 21:33:54 +02:00
|
|
|
&omap44xx_l3_main_2__c2c,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_l4_wkup__counter_32k,
|
2012-04-19 21:33:57 +02:00
|
|
|
&omap44xx_l4_cfg__ctrl_module_core,
|
|
|
|
&omap44xx_l4_cfg__ctrl_module_pad_core,
|
|
|
|
&omap44xx_l4_wkup__ctrl_module_wkup,
|
|
|
|
&omap44xx_l4_wkup__ctrl_module_pad_wkup,
|
2012-04-19 21:33:59 +02:00
|
|
|
&omap44xx_l3_instr__debugss,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_l4_cfg__dma_system,
|
|
|
|
&omap44xx_l4_abe__dmic,
|
|
|
|
&omap44xx_l4_abe__dmic_dma,
|
|
|
|
&omap44xx_dsp__iva,
|
2012-09-03 19:50:53 +02:00
|
|
|
/* &omap44xx_dsp__sl2if, */
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_l4_cfg__dsp,
|
|
|
|
&omap44xx_l3_main_2__dss,
|
|
|
|
&omap44xx_l4_per__dss,
|
|
|
|
&omap44xx_l3_main_2__dss_dispc,
|
|
|
|
&omap44xx_l4_per__dss_dispc,
|
|
|
|
&omap44xx_l3_main_2__dss_dsi1,
|
|
|
|
&omap44xx_l4_per__dss_dsi1,
|
|
|
|
&omap44xx_l3_main_2__dss_dsi2,
|
|
|
|
&omap44xx_l4_per__dss_dsi2,
|
|
|
|
&omap44xx_l3_main_2__dss_hdmi,
|
|
|
|
&omap44xx_l4_per__dss_hdmi,
|
|
|
|
&omap44xx_l3_main_2__dss_rfbi,
|
|
|
|
&omap44xx_l4_per__dss_rfbi,
|
|
|
|
&omap44xx_l3_main_2__dss_venc,
|
|
|
|
&omap44xx_l4_per__dss_venc,
|
2012-04-19 21:33:54 +02:00
|
|
|
&omap44xx_l4_per__elm,
|
2012-04-19 21:33:52 +02:00
|
|
|
&omap44xx_emif_fw__emif1,
|
|
|
|
&omap44xx_emif_fw__emif2,
|
2012-04-19 21:33:50 +02:00
|
|
|
&omap44xx_l4_cfg__fdif,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_l4_wkup__gpio1,
|
|
|
|
&omap44xx_l4_per__gpio2,
|
|
|
|
&omap44xx_l4_per__gpio3,
|
|
|
|
&omap44xx_l4_per__gpio4,
|
|
|
|
&omap44xx_l4_per__gpio5,
|
|
|
|
&omap44xx_l4_per__gpio6,
|
2012-04-19 21:33:51 +02:00
|
|
|
&omap44xx_l3_main_2__gpmc,
|
2012-04-19 21:33:53 +02:00
|
|
|
&omap44xx_l3_main_2__gpu,
|
2012-04-19 21:33:50 +02:00
|
|
|
&omap44xx_l4_per__hdq1w,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_l4_cfg__hsi,
|
|
|
|
&omap44xx_l4_per__i2c1,
|
|
|
|
&omap44xx_l4_per__i2c2,
|
|
|
|
&omap44xx_l4_per__i2c3,
|
|
|
|
&omap44xx_l4_per__i2c4,
|
|
|
|
&omap44xx_l3_main_2__ipu,
|
|
|
|
&omap44xx_l3_main_2__iss,
|
2012-09-03 19:50:53 +02:00
|
|
|
/* &omap44xx_iva__sl2if, */
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_l3_main_2__iva,
|
|
|
|
&omap44xx_l4_wkup__kbd,
|
|
|
|
&omap44xx_l4_cfg__mailbox,
|
2012-04-19 21:33:54 +02:00
|
|
|
&omap44xx_l4_abe__mcasp,
|
|
|
|
&omap44xx_l4_abe__mcasp_dma,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_l4_abe__mcbsp1,
|
|
|
|
&omap44xx_l4_abe__mcbsp1_dma,
|
|
|
|
&omap44xx_l4_abe__mcbsp2,
|
|
|
|
&omap44xx_l4_abe__mcbsp2_dma,
|
|
|
|
&omap44xx_l4_abe__mcbsp3,
|
|
|
|
&omap44xx_l4_abe__mcbsp3_dma,
|
|
|
|
&omap44xx_l4_per__mcbsp4,
|
|
|
|
&omap44xx_l4_abe__mcpdm,
|
|
|
|
&omap44xx_l4_abe__mcpdm_dma,
|
|
|
|
&omap44xx_l4_per__mcspi1,
|
|
|
|
&omap44xx_l4_per__mcspi2,
|
|
|
|
&omap44xx_l4_per__mcspi3,
|
|
|
|
&omap44xx_l4_per__mcspi4,
|
|
|
|
&omap44xx_l4_per__mmc1,
|
|
|
|
&omap44xx_l4_per__mmc2,
|
|
|
|
&omap44xx_l4_per__mmc3,
|
|
|
|
&omap44xx_l4_per__mmc4,
|
|
|
|
&omap44xx_l4_per__mmc5,
|
2012-09-24 01:28:24 +02:00
|
|
|
&omap44xx_l3_main_2__mmu_ipu,
|
|
|
|
&omap44xx_l4_cfg__mmu_dsp,
|
2012-04-19 21:33:56 +02:00
|
|
|
&omap44xx_l3_main_2__ocmc_ram,
|
2012-04-19 21:33:55 +02:00
|
|
|
&omap44xx_l4_cfg__ocp2scp_usb_phy,
|
2012-04-19 21:33:58 +02:00
|
|
|
&omap44xx_mpu_private__prcm_mpu,
|
|
|
|
&omap44xx_l4_wkup__cm_core_aon,
|
|
|
|
&omap44xx_l4_cfg__cm_core,
|
|
|
|
&omap44xx_l4_wkup__prm,
|
|
|
|
&omap44xx_l4_wkup__scrm,
|
2012-09-03 19:50:53 +02:00
|
|
|
/* &omap44xx_l3_main_2__sl2if, */
|
2012-04-19 21:33:53 +02:00
|
|
|
&omap44xx_l4_abe__slimbus1,
|
|
|
|
&omap44xx_l4_abe__slimbus1_dma,
|
|
|
|
&omap44xx_l4_per__slimbus2,
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_l4_cfg__smartreflex_core,
|
|
|
|
&omap44xx_l4_cfg__smartreflex_iva,
|
|
|
|
&omap44xx_l4_cfg__smartreflex_mpu,
|
|
|
|
&omap44xx_l4_cfg__spinlock,
|
|
|
|
&omap44xx_l4_wkup__timer1,
|
|
|
|
&omap44xx_l4_per__timer2,
|
|
|
|
&omap44xx_l4_per__timer3,
|
|
|
|
&omap44xx_l4_per__timer4,
|
|
|
|
&omap44xx_l4_abe__timer5,
|
|
|
|
&omap44xx_l4_abe__timer5_dma,
|
|
|
|
&omap44xx_l4_abe__timer6,
|
|
|
|
&omap44xx_l4_abe__timer6_dma,
|
|
|
|
&omap44xx_l4_abe__timer7,
|
|
|
|
&omap44xx_l4_abe__timer7_dma,
|
|
|
|
&omap44xx_l4_abe__timer8,
|
|
|
|
&omap44xx_l4_abe__timer8_dma,
|
|
|
|
&omap44xx_l4_per__timer9,
|
|
|
|
&omap44xx_l4_per__timer10,
|
|
|
|
&omap44xx_l4_per__timer11,
|
|
|
|
&omap44xx_l4_per__uart1,
|
|
|
|
&omap44xx_l4_per__uart2,
|
|
|
|
&omap44xx_l4_per__uart3,
|
|
|
|
&omap44xx_l4_per__uart4,
|
2012-07-04 14:55:29 +02:00
|
|
|
/* &omap44xx_l4_cfg__usb_host_fs, */
|
2012-04-19 12:04:31 +02:00
|
|
|
&omap44xx_l4_cfg__usb_host_hs,
|
|
|
|
&omap44xx_l4_cfg__usb_otg_hs,
|
|
|
|
&omap44xx_l4_cfg__usb_tll_hs,
|
|
|
|
&omap44xx_l4_wkup__wd_timer2,
|
|
|
|
&omap44xx_l4_abe__wd_timer3,
|
|
|
|
&omap44xx_l4_abe__wd_timer3_dma,
|
2010-05-12 17:54:36 +02:00
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
int __init omap44xx_hwmod_init(void)
|
|
|
|
{
|
2012-06-18 20:12:23 +02:00
|
|
|
omap_hwmod_init();
|
2012-04-19 12:04:31 +02:00
|
|
|
return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
|
2010-05-12 17:54:36 +02:00
|
|
|
}
|
|
|
|
|