2009-05-28 19:56:16 +02:00
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/*
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* OMAP3 Power Management Routines
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*
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* Copyright (C) 2006-2008 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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* Jouni Hogander
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*
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2008-09-26 14:20:07 +02:00
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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2009-05-28 19:56:16 +02:00
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap1
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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2009-10-06 23:25:09 +02:00
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#include <linux/clk.h>
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2009-11-17 17:34:53 +01:00
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#include <linux/delay.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 09:04:11 +01:00
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#include <linux/slab.h>
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2012-08-31 00:37:24 +02:00
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#include <linux/platform_data/gpio-omap.h>
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2011-03-03 11:25:43 +01:00
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#include <trace/events/power.h>
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2009-05-28 19:56:16 +02:00
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2011-06-22 18:41:48 +02:00
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#include <asm/suspend.h>
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2012-03-28 19:30:01 +02:00
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#include <asm/system_misc.h>
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2011-06-22 18:41:48 +02:00
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2009-10-20 18:40:47 +02:00
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#include <plat/sram.h>
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2010-12-22 05:05:15 +01:00
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#include "clockdomain.h"
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2010-12-22 05:05:16 +01:00
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#include "powerdomain.h"
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2008-09-26 14:19:56 +02:00
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#include <plat/sdrc.h>
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2008-09-26 14:20:07 +02:00
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#include <plat/prcm.h>
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#include <plat/gpmc.h>
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2008-08-28 15:13:31 +02:00
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#include <plat/dma.h>
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2009-05-28 19:56:16 +02:00
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2011-11-10 22:45:17 +01:00
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#include "common.h"
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2010-12-21 23:30:55 +01:00
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#include "cm2xxx_3xxx.h"
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2009-05-28 19:56:16 +02:00
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#include "cm-regbits-34xx.h"
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#include "prm-regbits-34xx.h"
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2010-12-21 23:30:55 +01:00
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#include "prm2xxx_3xxx.h"
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2009-05-28 19:56:16 +02:00
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#include "pm.h"
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2008-10-13 12:17:06 +02:00
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#include "sdrc.h"
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2010-10-08 19:40:20 +02:00
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#include "control.h"
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2008-10-13 12:17:06 +02:00
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2010-12-20 21:05:05 +01:00
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/* pm34xx errata defined in pm.h */
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u16 pm34xx_errata;
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2009-05-28 19:56:16 +02:00
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struct power_state {
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struct powerdomain *pwrdm;
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u32 next_state;
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2009-06-24 20:39:18 +02:00
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#ifdef CONFIG_SUSPEND
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2009-05-28 19:56:16 +02:00
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u32 saved_state;
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2009-06-24 20:39:18 +02:00
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#endif
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2009-05-28 19:56:16 +02:00
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struct list_head node;
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};
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static LIST_HEAD(pwrst_list);
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2008-10-13 12:15:00 +02:00
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static int (*_omap_save_secure_sram)(u32 *addr);
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2011-06-29 18:40:23 +02:00
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void (*omap3_do_wfi_sram)(void);
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2008-10-13 12:15:00 +02:00
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2008-09-26 14:19:22 +02:00
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static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
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static struct powerdomain *core_pwrdm, *per_pwrdm;
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2009-03-26 14:59:01 +01:00
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2008-09-26 14:20:07 +02:00
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static void omap3_core_save_context(void)
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{
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2010-12-22 05:05:16 +01:00
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omap3_ctrl_save_padconf();
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2009-11-17 17:34:53 +01:00
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/*
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* Force write last pad into memory, as this can fail in some
|
2010-12-18 16:44:46 +01:00
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* cases according to errata 1.157, 1.185
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2009-11-17 17:34:53 +01:00
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*/
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omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
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OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
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2008-09-26 14:20:07 +02:00
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/* Save the Interrupt controller context */
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omap_intc_save_context();
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/* Save the GPMC context */
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omap3_gpmc_save_context();
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/* Save the system control module context, padconf already save above*/
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omap3_control_save_context();
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2008-08-28 15:13:31 +02:00
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omap_dma_global_context_save();
|
2008-09-26 14:20:07 +02:00
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}
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static void omap3_core_restore_context(void)
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{
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/* Restore the control module context, padconf restored by h/w */
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omap3_control_restore_context();
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/* Restore the GPMC context */
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omap3_gpmc_restore_context();
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/* Restore the interrupt controller context */
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omap_intc_restore_context();
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2008-08-28 15:13:31 +02:00
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omap_dma_global_context_restore();
|
2008-09-26 14:20:07 +02:00
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}
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|
2008-12-12 10:20:05 +01:00
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/*
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* FIXME: This function should be called before entering off-mode after
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* OMAP3 secure services have been accessed. Currently it is only called
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* once during boot sequence, but this works as we are not using secure
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* services.
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*/
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2011-01-26 01:40:01 +01:00
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static void omap3_save_secure_ram_context(void)
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2008-10-13 12:15:00 +02:00
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{
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u32 ret;
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2011-01-26 01:40:01 +01:00
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int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
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2008-10-13 12:15:00 +02:00
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if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
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/*
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* MPU next state must be set to POWER_ON temporarily,
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* otherwise the WFI executed inside the ROM code
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* will hang the system.
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*/
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
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ret = _omap_save_secure_sram((u32 *)
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__pa(omap3_secure_ram_storage));
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2011-01-26 01:40:01 +01:00
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pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
|
2008-10-13 12:15:00 +02:00
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/* Following is for error tracking, it should not happen */
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if (ret) {
|
2012-03-18 02:22:48 +01:00
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pr_err("save_secure_sram() returns %08x\n", ret);
|
2008-10-13 12:15:00 +02:00
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while (1)
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;
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}
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}
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}
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|
2009-06-27 07:07:25 +02:00
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/*
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* PRCM Interrupt Handler Helper Function
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*
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* The purpose of this function is to clear any wake-up events latched
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* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
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* may occur whilst attempting to clear a PM_WKST_x register and thus
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* set another bit in this register. A while loop is used to ensure
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* that any peripheral wake-up events occurring while attempting to
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* clear the PM_WKST_x are detected and cleared.
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*/
|
2011-12-16 22:36:59 +01:00
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static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
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2009-05-28 19:56:16 +02:00
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{
|
2009-07-18 02:33:09 +02:00
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u32 wkst, fclk, iclk, clken;
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2009-06-27 07:07:25 +02:00
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u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
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u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
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u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
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2009-07-22 19:18:07 +02:00
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u16 grpsel_off = (regs == 3) ?
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OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
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2009-07-22 19:29:02 +02:00
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int c = 0;
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2009-05-28 19:56:16 +02:00
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2010-12-22 05:05:14 +01:00
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wkst = omap2_prm_read_mod_reg(module, wkst_off);
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wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
|
2011-12-16 22:36:59 +01:00
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wkst &= ~ignore_bits;
|
2009-05-28 19:56:16 +02:00
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if (wkst) {
|
2010-12-22 05:05:14 +01:00
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iclk = omap2_cm_read_mod_reg(module, iclk_off);
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fclk = omap2_cm_read_mod_reg(module, fclk_off);
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2009-06-27 07:07:25 +02:00
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while (wkst) {
|
2009-07-18 02:33:09 +02:00
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clken = wkst;
|
2010-12-22 05:05:14 +01:00
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omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
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2009-07-18 02:33:09 +02:00
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/*
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* For USBHOST, we don't know whether HOST1 or
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* HOST2 woke us up, so enable both f-clocks
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*/
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if (module == OMAP3430ES2_USBHOST_MOD)
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clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
|
2010-12-22 05:05:14 +01:00
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omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
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omap2_prm_write_mod_reg(wkst, module, wkst_off);
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wkst = omap2_prm_read_mod_reg(module, wkst_off);
|
2011-12-16 22:36:59 +01:00
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wkst &= ~ignore_bits;
|
2009-07-22 19:29:02 +02:00
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c++;
|
2009-06-27 07:07:25 +02:00
|
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}
|
2010-12-22 05:05:14 +01:00
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omap2_cm_write_mod_reg(iclk, module, iclk_off);
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omap2_cm_write_mod_reg(fclk, module, fclk_off);
|
2009-05-28 19:56:16 +02:00
|
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}
|
2009-07-22 19:29:02 +02:00
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return c;
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}
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|
2011-12-16 22:36:59 +01:00
|
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|
static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
|
2009-07-22 19:29:02 +02:00
|
|
|
{
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|
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int c;
|
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|
2011-12-16 22:36:59 +01:00
|
|
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c = prcm_clear_mod_irqs(WKUP_MOD, 1,
|
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|
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~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
|
2009-07-22 19:29:02 +02:00
|
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|
|
2011-12-16 22:36:59 +01:00
|
|
|
return c ? IRQ_HANDLED : IRQ_NONE;
|
2009-06-27 07:07:25 +02:00
|
|
|
}
|
2009-05-28 19:56:16 +02:00
|
|
|
|
2011-12-16 22:36:59 +01:00
|
|
|
static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
|
2009-06-27 07:07:25 +02:00
|
|
|
{
|
2011-12-16 22:36:59 +01:00
|
|
|
int c;
|
2010-04-26 23:59:09 +02:00
|
|
|
|
2011-12-16 22:36:59 +01:00
|
|
|
/*
|
|
|
|
* Clear all except ST_IO and ST_IO_CHAIN for wkup module,
|
|
|
|
* these are handled in a separate handler to avoid acking
|
|
|
|
* IO events before parsing in mux code
|
|
|
|
*/
|
|
|
|
c = prcm_clear_mod_irqs(WKUP_MOD, 1,
|
|
|
|
OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
|
|
|
|
c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
|
|
|
|
c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
|
|
c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
|
|
|
|
c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
|
|
|
|
}
|
2009-05-28 19:56:16 +02:00
|
|
|
|
2011-12-16 22:36:59 +01:00
|
|
|
return c ? IRQ_HANDLED : IRQ_NONE;
|
2009-05-28 19:56:16 +02:00
|
|
|
}
|
|
|
|
|
2011-06-30 09:45:49 +02:00
|
|
|
static void omap34xx_save_context(u32 *save)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
/* Read Auxiliary Control Register */
|
|
|
|
asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
|
|
|
|
*save++ = 1;
|
|
|
|
*save++ = val;
|
|
|
|
|
|
|
|
/* Read L2 AUX ctrl register */
|
|
|
|
asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
|
|
|
|
*save++ = 1;
|
|
|
|
*save++ = val;
|
|
|
|
}
|
|
|
|
|
2011-07-02 10:54:01 +02:00
|
|
|
static int omap34xx_do_sram_idle(unsigned long save_state)
|
2008-09-26 14:19:34 +02:00
|
|
|
{
|
2011-06-30 09:45:49 +02:00
|
|
|
omap34xx_cpu_suspend(save_state);
|
2011-07-02 10:54:01 +02:00
|
|
|
return 0;
|
2008-09-26 14:19:34 +02:00
|
|
|
}
|
|
|
|
|
2008-10-08 14:00:58 +02:00
|
|
|
void omap_sram_idle(void)
|
2009-05-28 19:56:16 +02:00
|
|
|
{
|
|
|
|
/* Variable to tell what needs to be saved and restored
|
|
|
|
* in omap_sram_idle*/
|
|
|
|
/* save_state = 0 => Nothing to save and restored */
|
|
|
|
/* save_state = 1 => Only L1 and logic lost */
|
|
|
|
/* save_state = 2 => Only L2 lost */
|
|
|
|
/* save_state = 3 => L1, L2 and logic lost */
|
2008-09-26 14:19:22 +02:00
|
|
|
int save_state = 0;
|
|
|
|
int mpu_next_state = PWRDM_POWER_ON;
|
|
|
|
int per_next_state = PWRDM_POWER_ON;
|
|
|
|
int core_next_state = PWRDM_POWER_ON;
|
2010-12-22 05:05:16 +01:00
|
|
|
int per_going_off;
|
2012-04-13 14:34:32 +02:00
|
|
|
int core_prev_state;
|
2008-10-13 12:17:06 +02:00
|
|
|
u32 sdrc_pwr = 0;
|
2009-05-28 19:56:16 +02:00
|
|
|
|
|
|
|
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
|
|
|
|
switch (mpu_next_state) {
|
2008-09-26 14:19:22 +02:00
|
|
|
case PWRDM_POWER_ON:
|
2009-05-28 19:56:16 +02:00
|
|
|
case PWRDM_POWER_RET:
|
|
|
|
/* No need to save context */
|
|
|
|
save_state = 0;
|
|
|
|
break;
|
2008-09-26 14:19:56 +02:00
|
|
|
case PWRDM_POWER_OFF:
|
|
|
|
save_state = 3;
|
|
|
|
break;
|
2009-05-28 19:56:16 +02:00
|
|
|
default:
|
|
|
|
/* Invalid state */
|
2012-03-18 02:22:48 +01:00
|
|
|
pr_err("Invalid mpu state in sram_idle\n");
|
2009-05-28 19:56:16 +02:00
|
|
|
return;
|
|
|
|
}
|
2008-10-15 16:48:44 +02:00
|
|
|
|
2008-09-26 14:19:22 +02:00
|
|
|
/* NEON control */
|
|
|
|
if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
|
2008-10-28 09:59:05 +01:00
|
|
|
pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
|
2008-09-26 14:19:22 +02:00
|
|
|
|
2010-05-04 01:04:06 +02:00
|
|
|
/* Enable IO-PAD and IO-CHAIN wakeups */
|
2008-11-05 05:50:52 +01:00
|
|
|
per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
|
2008-12-01 12:17:29 +01:00
|
|
|
core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
|
2010-05-04 01:04:06 +02:00
|
|
|
|
2012-08-07 20:28:06 +02:00
|
|
|
pwrdm_pre_transition(NULL);
|
2011-09-13 15:02:37 +02:00
|
|
|
|
2010-05-04 01:04:06 +02:00
|
|
|
/* PER */
|
2008-11-05 05:50:52 +01:00
|
|
|
if (per_next_state < PWRDM_POWER_ON) {
|
2010-12-22 05:05:16 +01:00
|
|
|
per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
|
|
|
|
omap2_gpio_prepare_for_idle(per_going_off);
|
2008-11-05 05:50:52 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* CORE */
|
2008-09-26 14:19:22 +02:00
|
|
|
if (core_next_state < PWRDM_POWER_ON) {
|
2008-09-26 14:20:07 +02:00
|
|
|
if (core_next_state == PWRDM_POWER_OFF) {
|
|
|
|
omap3_core_save_context();
|
2010-12-21 23:30:56 +01:00
|
|
|
omap3_cm_save_context();
|
2008-09-26 14:20:07 +02:00
|
|
|
}
|
2008-09-26 14:19:22 +02:00
|
|
|
}
|
2010-05-04 01:04:06 +02:00
|
|
|
|
2009-10-23 18:03:50 +02:00
|
|
|
omap3_intc_prepare_idle();
|
2009-05-28 19:56:16 +02:00
|
|
|
|
2008-10-13 12:17:06 +02:00
|
|
|
/*
|
2011-10-06 21:43:23 +02:00
|
|
|
* On EMU/HS devices ROM code restores a SRDC value
|
|
|
|
* from scratchpad which has automatic self refresh on timeout
|
|
|
|
* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
|
|
|
|
* Hence store/restore the SDRC_POWER register here.
|
|
|
|
*/
|
|
|
|
if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
|
|
|
|
(omap_type() == OMAP2_DEVICE_TYPE_EMU ||
|
|
|
|
omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
|
2009-06-09 19:00:41 +02:00
|
|
|
core_next_state == PWRDM_POWER_OFF)
|
2008-10-13 12:17:06 +02:00
|
|
|
sdrc_pwr = sdrc_read_reg(SDRC_POWER);
|
|
|
|
|
2008-09-26 14:19:56 +02:00
|
|
|
/*
|
2011-06-22 16:42:54 +02:00
|
|
|
* omap3_arm_context is the location where some ARM context
|
|
|
|
* get saved. The rest is placed on the stack, and restored
|
|
|
|
* from there before resuming.
|
2008-09-26 14:19:56 +02:00
|
|
|
*/
|
2011-06-30 09:45:49 +02:00
|
|
|
if (save_state)
|
|
|
|
omap34xx_save_context(omap3_arm_context);
|
2011-06-22 16:42:54 +02:00
|
|
|
if (save_state == 1 || save_state == 3)
|
2011-06-22 18:41:48 +02:00
|
|
|
cpu_suspend(save_state, omap34xx_do_sram_idle);
|
2011-06-22 16:42:54 +02:00
|
|
|
else
|
|
|
|
omap34xx_do_sram_idle(save_state);
|
2009-05-28 19:56:16 +02:00
|
|
|
|
2009-06-09 19:00:41 +02:00
|
|
|
/* Restore normal SDRC POWER settings */
|
2011-10-06 21:43:23 +02:00
|
|
|
if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
|
|
|
|
(omap_type() == OMAP2_DEVICE_TYPE_EMU ||
|
|
|
|
omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
|
2008-10-13 12:17:06 +02:00
|
|
|
core_next_state == PWRDM_POWER_OFF)
|
|
|
|
sdrc_write_reg(sdrc_pwr, SDRC_POWER);
|
|
|
|
|
2008-11-05 05:50:52 +01:00
|
|
|
/* CORE */
|
2008-09-26 14:19:22 +02:00
|
|
|
if (core_next_state < PWRDM_POWER_ON) {
|
2008-09-26 14:20:07 +02:00
|
|
|
core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
|
|
|
|
if (core_prev_state == PWRDM_POWER_OFF) {
|
|
|
|
omap3_core_restore_context();
|
2010-12-21 23:30:56 +01:00
|
|
|
omap3_cm_restore_context();
|
2008-09-26 14:20:07 +02:00
|
|
|
omap3_sram_restore_context();
|
2009-05-13 12:32:11 +02:00
|
|
|
omap2_sms_restore_context();
|
2008-09-26 14:20:07 +02:00
|
|
|
}
|
2008-11-05 05:50:52 +01:00
|
|
|
if (core_next_state == PWRDM_POWER_OFF)
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
|
2008-11-05 05:50:52 +01:00
|
|
|
OMAP3430_GR_MOD,
|
|
|
|
OMAP3_PRM_VOLTCTRL_OFFSET);
|
|
|
|
}
|
2009-10-23 18:03:50 +02:00
|
|
|
omap3_intc_resume_idle();
|
2008-11-05 05:50:52 +01:00
|
|
|
|
2012-08-07 20:28:06 +02:00
|
|
|
pwrdm_post_transition(NULL);
|
|
|
|
|
2008-11-05 05:50:52 +01:00
|
|
|
/* PER */
|
2012-08-07 20:28:06 +02:00
|
|
|
if (per_next_state < PWRDM_POWER_ON)
|
2009-01-27 20:09:24 +01:00
|
|
|
omap2_gpio_resume_after_idle();
|
2009-05-28 19:56:16 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void omap3_pm_idle(void)
|
|
|
|
{
|
|
|
|
local_fiq_disable();
|
|
|
|
|
2012-01-04 22:27:48 +01:00
|
|
|
if (omap_irq_pending())
|
2009-05-28 19:56:16 +02:00
|
|
|
goto out;
|
|
|
|
|
2011-03-03 11:25:43 +01:00
|
|
|
trace_power_start(POWER_CSTATE, 1, smp_processor_id());
|
|
|
|
trace_cpu_idle(1, smp_processor_id());
|
|
|
|
|
2009-05-28 19:56:16 +02:00
|
|
|
omap_sram_idle();
|
|
|
|
|
2011-03-03 11:25:43 +01:00
|
|
|
trace_power_end(smp_processor_id());
|
|
|
|
trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
|
|
|
|
|
2009-05-28 19:56:16 +02:00
|
|
|
out:
|
|
|
|
local_fiq_enable();
|
|
|
|
}
|
|
|
|
|
2009-06-24 20:39:18 +02:00
|
|
|
#ifdef CONFIG_SUSPEND
|
2009-05-28 19:56:16 +02:00
|
|
|
static int omap3_pm_suspend(void)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
int state, ret = 0;
|
|
|
|
|
|
|
|
/* Read current next_pwrsts */
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node)
|
|
|
|
pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
|
|
|
|
/* Set ones wanted by suspend */
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
2010-09-14 21:34:01 +02:00
|
|
|
if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
|
2009-05-28 19:56:16 +02:00
|
|
|
goto restore;
|
|
|
|
if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
|
|
|
|
goto restore;
|
|
|
|
}
|
|
|
|
|
2009-10-23 18:03:48 +02:00
|
|
|
omap3_intc_suspend();
|
|
|
|
|
2009-05-28 19:56:16 +02:00
|
|
|
omap_sram_idle();
|
|
|
|
|
|
|
|
restore:
|
|
|
|
/* Restore next_pwrsts */
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
|
|
|
|
if (state > pwrst->next_state) {
|
2012-07-26 08:54:26 +02:00
|
|
|
pr_info("Powerdomain (%s) didn't enter target state %d\n",
|
|
|
|
pwrst->pwrdm->name, pwrst->next_state);
|
2009-05-28 19:56:16 +02:00
|
|
|
ret = -1;
|
|
|
|
}
|
2010-09-14 21:34:01 +02:00
|
|
|
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
|
2009-05-28 19:56:16 +02:00
|
|
|
}
|
|
|
|
if (ret)
|
2012-03-18 02:22:48 +01:00
|
|
|
pr_err("Could not enter target state in pm_suspend\n");
|
2009-05-28 19:56:16 +02:00
|
|
|
else
|
2012-03-18 02:22:48 +01:00
|
|
|
pr_info("Successfully put all powerdomains to target state\n");
|
2009-05-28 19:56:16 +02:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-06-24 20:39:18 +02:00
|
|
|
#endif /* CONFIG_SUSPEND */
|
2009-05-28 19:56:16 +02:00
|
|
|
|
2008-11-25 20:48:24 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* omap3_iva_idle(): ensure IVA is in idle so it can be put into
|
|
|
|
* retention
|
|
|
|
*
|
|
|
|
* In cases where IVA2 is activated by bootcode, it may prevent
|
|
|
|
* full-chip retention or off-mode because it is not idle. This
|
|
|
|
* function forces the IVA2 into idle state so it can go
|
|
|
|
* into retention/off and thus allow full-chip retention/off.
|
|
|
|
*
|
|
|
|
**/
|
|
|
|
static void __init omap3_iva_idle(void)
|
|
|
|
{
|
|
|
|
/* ensure IVA2 clock is disabled */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
2008-11-25 20:48:24 +01:00
|
|
|
|
|
|
|
/* if no clock activity, nothing else to do */
|
2010-12-22 05:05:14 +01:00
|
|
|
if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
|
2008-11-25 20:48:24 +01:00
|
|
|
OMAP3430_CLKACTIVITY_IVA2_MASK))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Reset IVA2 */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
2010-05-19 02:47:24 +02:00
|
|
|
OMAP3430_RST2_IVA2_MASK |
|
|
|
|
OMAP3430_RST3_IVA2_MASK,
|
2010-01-27 04:12:51 +01:00
|
|
|
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
2008-11-25 20:48:24 +01:00
|
|
|
|
|
|
|
/* Enable IVA2 clock */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
|
2008-11-25 20:48:24 +01:00
|
|
|
OMAP3430_IVA2_MOD, CM_FCLKEN);
|
|
|
|
|
|
|
|
/* Set IVA2 boot mode to 'idle' */
|
|
|
|
omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
|
|
|
|
OMAP343X_CONTROL_IVA2_BOOTMOD);
|
|
|
|
|
|
|
|
/* Un-reset IVA2 */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
2008-11-25 20:48:24 +01:00
|
|
|
|
|
|
|
/* Disable IVA2 clock */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
2008-11-25 20:48:24 +01:00
|
|
|
|
|
|
|
/* Reset IVA2 */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
2010-05-19 02:47:24 +02:00
|
|
|
OMAP3430_RST2_IVA2_MASK |
|
|
|
|
OMAP3430_RST3_IVA2_MASK,
|
2010-01-27 04:12:51 +01:00
|
|
|
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
2008-11-25 20:48:24 +01:00
|
|
|
}
|
|
|
|
|
2009-04-29 00:27:44 +02:00
|
|
|
static void __init omap3_d2d_idle(void)
|
2009-05-28 19:56:16 +02:00
|
|
|
{
|
2009-04-29 00:27:44 +02:00
|
|
|
u16 mask, padconf;
|
|
|
|
|
|
|
|
/* In a stand alone OMAP3430 where there is not a stacked
|
|
|
|
* modem for the D2D Idle Ack and D2D MStandby must be pulled
|
|
|
|
* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
|
|
|
|
* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
|
|
|
|
mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
|
|
|
|
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
|
|
|
|
padconf |= mask;
|
|
|
|
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
|
|
|
|
|
|
|
|
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
|
|
|
|
padconf |= mask;
|
|
|
|
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
|
|
|
|
|
2009-05-28 19:56:16 +02:00
|
|
|
/* reset modem */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
|
2010-05-19 02:47:24 +02:00
|
|
|
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
|
2010-01-27 04:12:51 +01:00
|
|
|
CORE_MOD, OMAP2_RM_RSTCTRL);
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
|
2009-04-29 00:27:44 +02:00
|
|
|
}
|
2009-05-28 19:56:16 +02:00
|
|
|
|
2009-04-29 00:27:44 +02:00
|
|
|
static void __init prcm_setup_regs(void)
|
|
|
|
{
|
2010-09-27 16:50:25 +02:00
|
|
|
u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
|
|
|
|
OMAP3630_EN_UART4_MASK : 0;
|
|
|
|
u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
|
|
|
|
OMAP3630_GRPSEL_UART4_MASK : 0;
|
|
|
|
|
2011-02-25 23:39:30 +01:00
|
|
|
/* XXX This should be handled by hwmod code or SCM init code */
|
2010-05-19 02:40:23 +02:00
|
|
|
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
|
2009-10-23 18:03:49 +02:00
|
|
|
|
2009-05-28 19:56:16 +02:00
|
|
|
/*
|
|
|
|
* Enable control of expternal oscillator through
|
|
|
|
* sys_clkreq. In the long run clock framework should
|
|
|
|
* take care of this.
|
|
|
|
*/
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
|
2009-05-28 19:56:16 +02:00
|
|
|
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
|
|
|
|
OMAP3430_GR_MOD,
|
|
|
|
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
|
|
|
|
|
|
|
/* setup wakup source */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
|
2010-05-19 02:40:23 +02:00
|
|
|
OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
|
2009-05-28 19:56:16 +02:00
|
|
|
WKUP_MOD, PM_WKEN);
|
|
|
|
/* No need to write EN_IO, that is always enabled */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
|
2010-05-19 02:40:23 +02:00
|
|
|
OMAP3430_GRPSEL_GPT1_MASK |
|
|
|
|
OMAP3430_GRPSEL_GPT12_MASK,
|
2009-05-28 19:56:16 +02:00
|
|
|
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
2008-11-25 20:48:24 +01:00
|
|
|
|
2009-12-22 10:37:50 +01:00
|
|
|
/* Enable PM_WKEN to support DSS LPR */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
|
2009-12-22 10:37:50 +01:00
|
|
|
OMAP3430_DSS_MOD, PM_WKEN);
|
|
|
|
|
2009-10-22 23:48:13 +02:00
|
|
|
/* Enable wakeups in PER */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
|
2010-09-27 16:50:25 +02:00
|
|
|
OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
|
2010-05-19 02:40:23 +02:00
|
|
|
OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
|
|
|
|
OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
|
|
|
|
OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
|
|
|
|
OMAP3430_EN_MCBSP4_MASK,
|
2009-10-22 23:48:13 +02:00
|
|
|
OMAP3430_PER_MOD, PM_WKEN);
|
OMAP3: PM: Enable GPIO module-level wakeups
Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are
enabled as wakups. This patch also enables GPIOs in the PER
powerdomain (banks 2-6) to be used as possible wakeup sources.
In addition, this patch ensures that all GPIO wakeups can wakeup
the MPU using the PM_MPUGRPSEL_<pwrdm> registers.
NOTE: this doesn't enable the individual GPIOs as wakeups, this simply
enables the per-bank wakeups at the powerdomain level.
This problem was discovered by Mike Chan when preventing the CORE
powerdomain from going into retention/off. When CORE was allowed to
hit retention, GPIO wakeups via IO pad were working fine, but when
CORE remained on, GPIO module-level wakeups were not working properly.
To test, prevent CORE from going inactive/retention/off, thus
preventing the IO chain from being armed:
# echo 3 > /debug/pm_debug/core_pwrdm/suspend
This ensures that GPIO wakeups happen via module-level wakeups and
not via IO pad.
Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP)
Tested on Zoom2 using the QUART interrup GPIO (gpio 102, in PER)
Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues:
http://elinux.org/OMAP_Power_Management
Reported-by: Mike Chan <mikechan@google.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-09-10 17:53:08 +02:00
|
|
|
/* and allow them to wake up MPU */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
|
2010-09-27 16:50:25 +02:00
|
|
|
OMAP3430_GRPSEL_GPIO2_MASK |
|
2010-05-19 02:40:23 +02:00
|
|
|
OMAP3430_GRPSEL_GPIO3_MASK |
|
|
|
|
OMAP3430_GRPSEL_GPIO4_MASK |
|
|
|
|
OMAP3430_GRPSEL_GPIO5_MASK |
|
|
|
|
OMAP3430_GRPSEL_GPIO6_MASK |
|
|
|
|
OMAP3430_GRPSEL_UART3_MASK |
|
|
|
|
OMAP3430_GRPSEL_MCBSP2_MASK |
|
|
|
|
OMAP3430_GRPSEL_MCBSP3_MASK |
|
|
|
|
OMAP3430_GRPSEL_MCBSP4_MASK,
|
OMAP3: PM: Enable GPIO module-level wakeups
Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are
enabled as wakups. This patch also enables GPIOs in the PER
powerdomain (banks 2-6) to be used as possible wakeup sources.
In addition, this patch ensures that all GPIO wakeups can wakeup
the MPU using the PM_MPUGRPSEL_<pwrdm> registers.
NOTE: this doesn't enable the individual GPIOs as wakeups, this simply
enables the per-bank wakeups at the powerdomain level.
This problem was discovered by Mike Chan when preventing the CORE
powerdomain from going into retention/off. When CORE was allowed to
hit retention, GPIO wakeups via IO pad were working fine, but when
CORE remained on, GPIO module-level wakeups were not working properly.
To test, prevent CORE from going inactive/retention/off, thus
preventing the IO chain from being armed:
# echo 3 > /debug/pm_debug/core_pwrdm/suspend
This ensures that GPIO wakeups happen via module-level wakeups and
not via IO pad.
Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP)
Tested on Zoom2 using the QUART interrup GPIO (gpio 102, in PER)
Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues:
http://elinux.org/OMAP_Power_Management
Reported-by: Mike Chan <mikechan@google.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-09-10 17:53:08 +02:00
|
|
|
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
|
|
|
2009-05-06 01:34:25 +02:00
|
|
|
/* Don't attach IVA interrupts */
|
2012-04-19 20:17:45 +02:00
|
|
|
if (omap3_has_iva()) {
|
|
|
|
omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
|
|
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
|
|
|
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
|
|
|
omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
|
|
|
|
OMAP3430_PM_IVAGRPSEL);
|
|
|
|
}
|
2009-05-06 01:34:25 +02:00
|
|
|
|
2009-04-28 01:14:54 +02:00
|
|
|
/* Clear any pending 'reset' flags */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
|
|
|
|
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
|
|
|
|
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
|
|
|
|
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
|
|
|
|
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
|
|
|
|
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
|
|
|
|
omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
|
2009-04-28 01:14:54 +02:00
|
|
|
|
2009-04-27 16:50:23 +02:00
|
|
|
/* Clear any pending PRCM interrupts */
|
2010-12-22 05:05:14 +01:00
|
|
|
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
2009-04-27 16:50:23 +02:00
|
|
|
|
2012-04-19 20:17:45 +02:00
|
|
|
if (omap3_has_iva())
|
|
|
|
omap3_iva_idle();
|
|
|
|
|
2009-04-29 00:27:44 +02:00
|
|
|
omap3_d2d_idle();
|
2009-05-28 19:56:16 +02:00
|
|
|
}
|
|
|
|
|
2009-10-06 23:25:09 +02:00
|
|
|
void omap3_pm_off_mode_enable(int enable)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
u32 state;
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
state = PWRDM_POWER_OFF;
|
|
|
|
else
|
|
|
|
state = PWRDM_POWER_RET;
|
|
|
|
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
2010-12-20 21:05:09 +01:00
|
|
|
if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
|
|
|
|
pwrst->pwrdm == core_pwrdm &&
|
|
|
|
state == PWRDM_POWER_OFF) {
|
|
|
|
pwrst->next_state = PWRDM_POWER_RET;
|
2011-01-31 14:35:25 +01:00
|
|
|
pr_warn("%s: Core OFF disabled due to errata i583\n",
|
2010-12-20 21:05:09 +01:00
|
|
|
__func__);
|
|
|
|
} else {
|
|
|
|
pwrst->next_state = state;
|
|
|
|
}
|
|
|
|
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
2009-10-06 23:25:09 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-11-26 11:26:24 +01:00
|
|
|
int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
if (pwrst->pwrdm == pwrdm)
|
|
|
|
return pwrst->next_state;
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
if (pwrst->pwrdm == pwrdm) {
|
|
|
|
pwrst->next_state = state;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2008-10-15 17:13:47 +02:00
|
|
|
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
|
2009-05-28 19:56:16 +02:00
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
|
|
|
|
if (!pwrdm->pwrsts)
|
|
|
|
return 0;
|
|
|
|
|
2009-08-22 15:20:26 +02:00
|
|
|
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
|
2009-05-28 19:56:16 +02:00
|
|
|
if (!pwrst)
|
|
|
|
return -ENOMEM;
|
|
|
|
pwrst->pwrdm = pwrdm;
|
|
|
|
pwrst->next_state = PWRDM_POWER_RET;
|
|
|
|
list_add(&pwrst->node, &pwrst_list);
|
|
|
|
|
|
|
|
if (pwrdm_has_hdwr_sar(pwrdm))
|
|
|
|
pwrdm_enable_hdwr_sar(pwrdm);
|
|
|
|
|
2010-09-14 21:34:01 +02:00
|
|
|
return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
2009-05-28 19:56:16 +02:00
|
|
|
}
|
|
|
|
|
2011-06-29 18:40:23 +02:00
|
|
|
/*
|
|
|
|
* Push functions to SRAM
|
|
|
|
*
|
|
|
|
* The minimum set of functions is pushed to SRAM for execution:
|
|
|
|
* - omap3_do_wfi for erratum i581 WA,
|
|
|
|
* - save_secure_ram_context for security extensions.
|
|
|
|
*/
|
2008-09-26 14:19:14 +02:00
|
|
|
void omap_push_sram_idle(void)
|
|
|
|
{
|
2011-06-29 18:40:23 +02:00
|
|
|
omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
|
|
|
|
|
2008-10-13 12:15:00 +02:00
|
|
|
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
|
|
|
|
_omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
|
|
|
|
save_secure_ram_context_sz);
|
2008-09-26 14:19:14 +02:00
|
|
|
}
|
|
|
|
|
2010-12-20 21:05:05 +01:00
|
|
|
static void __init pm_errata_configure(void)
|
|
|
|
{
|
2010-12-20 21:05:07 +01:00
|
|
|
if (cpu_is_omap3630()) {
|
2010-12-20 21:05:06 +01:00
|
|
|
pm34xx_errata |= PM_RTA_ERRATUM_i608;
|
2010-12-20 21:05:07 +01:00
|
|
|
/* Enable the l2 cache toggling in sleep logic */
|
|
|
|
enable_omap3630_toggle_l2_on_restore();
|
2010-12-20 21:05:09 +01:00
|
|
|
if (omap_rev() < OMAP3630_REV_ES1_2)
|
2012-10-16 08:08:53 +02:00
|
|
|
pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
|
|
|
|
PM_PER_MEMORIES_ERRATUM_i582);
|
|
|
|
} else if (cpu_is_omap34xx()) {
|
|
|
|
pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
|
2010-12-20 21:05:07 +01:00
|
|
|
}
|
2010-12-20 21:05:05 +01:00
|
|
|
}
|
|
|
|
|
2012-04-26 10:06:50 +02:00
|
|
|
int __init omap3_pm_init(void)
|
2009-05-28 19:56:16 +02:00
|
|
|
{
|
|
|
|
struct power_state *pwrst, *tmp;
|
2012-10-16 08:08:53 +02:00
|
|
|
struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
|
2009-05-28 19:56:16 +02:00
|
|
|
int ret;
|
|
|
|
|
ARM: OMAP3: PM: fix I/O wakeup and I/O chain clock control detection
The way that we detect which OMAP3 chips support I/O wakeup and
software I/O chain clock control is broken.
Currently, I/O wakeup is marked as present for all OMAP3 SoCs other
than the AM3505/3517. The TI81xx family of SoCs are at present
considered to be OMAP3 SoCs, but don't support I/O wakeup. To resolve
this, convert the existing blacklist approach to an explicit,
whitelist support, in which only SoCs which are known to support I/O
wakeup are listed. (At present, this only includes OMAP34xx,
OMAP3503, OMAP3515, OMAP3525, OMAP3530, and OMAP36xx.)
Also, the current code incorrectly detects the presence of a
software-controllable I/O chain clock on several chips that don't
support it. This results in writes to reserved bitfields, unnecessary
delays, and console messages on kernels running on those chips:
http://www.spinics.net/lists/linux-omap/msg58735.html
Convert this test to a feature test with a chip-by-chip whitelist.
Thanks to Dave Hylands <dhylands@gmail.com> for reporting this problem
and doing some testing to help isolate the cause. Thanks to Steve
Sakoman <sakoman@gmail.com> for catching a bug in the first version of
this patch. Thanks to Russell King <linux@arm.linux.org.uk> for
comments.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Dave Hylands <dhylands@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Tested-by: Steve Sakoman <sakoman@gmail.com>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-10-07 01:18:45 +02:00
|
|
|
if (!omap3_has_io_chain_ctrl())
|
|
|
|
pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
|
|
|
|
|
2010-12-20 21:05:05 +01:00
|
|
|
pm_errata_configure();
|
|
|
|
|
2009-05-28 19:56:16 +02:00
|
|
|
/* XXX prcm_setup_regs needs to be before enabling hw
|
|
|
|
* supervised mode for powerdomains */
|
|
|
|
prcm_setup_regs();
|
|
|
|
|
2011-12-16 22:36:59 +01:00
|
|
|
ret = request_irq(omap_prcm_event_to_irq("wkup"),
|
|
|
|
_prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
pr_err("pm: Failed to request pm_wkup irq\n");
|
|
|
|
goto err1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* IO interrupt is shared with mux code */
|
|
|
|
ret = request_irq(omap_prcm_event_to_irq("io"),
|
|
|
|
_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
|
|
|
|
omap3_pm_init);
|
2012-04-28 01:05:51 +02:00
|
|
|
enable_irq(omap_prcm_event_to_irq("io"));
|
2011-12-16 22:36:59 +01:00
|
|
|
|
2009-05-28 19:56:16 +02:00
|
|
|
if (ret) {
|
2011-12-16 22:36:59 +01:00
|
|
|
pr_err("pm: Failed to request pm_io irq\n");
|
2012-03-18 02:22:47 +01:00
|
|
|
goto err2;
|
2009-05-28 19:56:16 +02:00
|
|
|
}
|
|
|
|
|
2008-10-15 17:13:47 +02:00
|
|
|
ret = pwrdm_for_each(pwrdms_setup, NULL);
|
2009-05-28 19:56:16 +02:00
|
|
|
if (ret) {
|
2012-03-18 02:22:48 +01:00
|
|
|
pr_err("Failed to setup powerdomains\n");
|
2012-03-18 02:22:47 +01:00
|
|
|
goto err3;
|
2009-05-28 19:56:16 +02:00
|
|
|
}
|
|
|
|
|
2012-02-02 10:38:50 +01:00
|
|
|
(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
|
2009-05-28 19:56:16 +02:00
|
|
|
|
|
|
|
mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
|
|
|
|
if (mpu_pwrdm == NULL) {
|
2012-03-18 02:22:48 +01:00
|
|
|
pr_err("Failed to get mpu_pwrdm\n");
|
2012-03-18 02:22:47 +01:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto err3;
|
2009-05-28 19:56:16 +02:00
|
|
|
}
|
|
|
|
|
2008-09-26 14:19:22 +02:00
|
|
|
neon_pwrdm = pwrdm_lookup("neon_pwrdm");
|
|
|
|
per_pwrdm = pwrdm_lookup("per_pwrdm");
|
|
|
|
core_pwrdm = pwrdm_lookup("core_pwrdm");
|
|
|
|
|
2010-01-27 04:12:59 +01:00
|
|
|
neon_clkdm = clkdm_lookup("neon_clkdm");
|
|
|
|
mpu_clkdm = clkdm_lookup("mpu_clkdm");
|
2012-10-16 08:08:53 +02:00
|
|
|
per_clkdm = clkdm_lookup("per_clkdm");
|
|
|
|
wkup_clkdm = clkdm_lookup("wkup_clkdm");
|
2010-01-27 04:12:59 +01:00
|
|
|
|
2009-06-24 20:39:18 +02:00
|
|
|
#ifdef CONFIG_SUSPEND
|
2012-02-02 10:30:50 +01:00
|
|
|
omap_pm_suspend = omap3_pm_suspend;
|
|
|
|
#endif
|
2009-05-28 19:56:16 +02:00
|
|
|
|
2012-01-04 22:27:48 +01:00
|
|
|
arm_pm_idle = omap3_pm_idle;
|
2008-09-26 10:04:20 +02:00
|
|
|
omap3_idle_init();
|
2009-05-28 19:56:16 +02:00
|
|
|
|
2010-12-20 21:05:06 +01:00
|
|
|
/*
|
|
|
|
* RTA is disabled during initialization as per erratum i608
|
|
|
|
* it is safer to disable RTA by the bootloader, but we would like
|
|
|
|
* to be doubly sure here and prevent any mishaps.
|
|
|
|
*/
|
|
|
|
if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
|
|
|
|
omap3630_ctrl_disable_rta();
|
|
|
|
|
2012-10-16 08:08:53 +02:00
|
|
|
/*
|
|
|
|
* The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
|
|
|
|
* not correctly reset when the PER powerdomain comes back
|
|
|
|
* from OFF or OSWR when the CORE powerdomain is kept active.
|
|
|
|
* See OMAP36xx Erratum i582 "PER Domain reset issue after
|
|
|
|
* Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
|
|
|
|
* complete workaround. The kernel must also prevent the PER
|
|
|
|
* powerdomain from going to OSWR/OFF while the CORE
|
|
|
|
* powerdomain is not going to OSWR/OFF. And if PER last
|
|
|
|
* power state was off while CORE last power state was ON, the
|
|
|
|
* UART3/4 and McBSP2/3 SIDETONE devices need to run a
|
|
|
|
* self-test using their loopback tests; if that fails, those
|
|
|
|
* devices are unusable until the PER/CORE can complete a transition
|
|
|
|
* from ON to OSWR/OFF and then back to ON.
|
|
|
|
*
|
|
|
|
* XXX Technically this workaround is only needed if off-mode
|
|
|
|
* or OSWR is enabled.
|
|
|
|
*/
|
|
|
|
if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
|
|
|
|
clkdm_add_wkdep(per_clkdm, wkup_clkdm);
|
|
|
|
|
2010-01-27 04:12:59 +01:00
|
|
|
clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
|
2008-10-13 12:15:00 +02:00
|
|
|
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
|
|
|
|
omap3_secure_ram_storage =
|
|
|
|
kmalloc(0x803F, GFP_KERNEL);
|
|
|
|
if (!omap3_secure_ram_storage)
|
2012-07-26 08:54:26 +02:00
|
|
|
pr_err("Memory allocation failed when allocating for secure sram context\n");
|
2008-12-12 10:20:05 +01:00
|
|
|
|
|
|
|
local_irq_disable();
|
|
|
|
local_fiq_disable();
|
|
|
|
|
|
|
|
omap_dma_global_context_save();
|
2011-01-26 01:40:01 +01:00
|
|
|
omap3_save_secure_ram_context();
|
2008-12-12 10:20:05 +01:00
|
|
|
omap_dma_global_context_restore();
|
|
|
|
|
|
|
|
local_irq_enable();
|
|
|
|
local_fiq_enable();
|
2008-10-13 12:15:00 +02:00
|
|
|
}
|
|
|
|
|
2008-12-12 10:20:05 +01:00
|
|
|
omap3_save_scratchpad_contents();
|
2009-05-28 19:56:16 +02:00
|
|
|
return ret;
|
2012-03-18 02:22:47 +01:00
|
|
|
|
|
|
|
err3:
|
2009-05-28 19:56:16 +02:00
|
|
|
list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
|
|
|
|
list_del(&pwrst->node);
|
|
|
|
kfree(pwrst);
|
|
|
|
}
|
2012-03-18 02:22:47 +01:00
|
|
|
free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
|
|
|
|
err2:
|
|
|
|
free_irq(omap_prcm_event_to_irq("wkup"), NULL);
|
|
|
|
err1:
|
2009-05-28 19:56:16 +02:00
|
|
|
return ret;
|
|
|
|
}
|