2008-08-19 10:08:40 +02:00
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/*
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2010-12-22 05:05:14 +01:00
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* OMAP2/3/4 powerdomain control
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2008-08-19 10:08:40 +02:00
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*
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2010-12-22 05:05:16 +01:00
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* Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
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2011-03-08 03:28:15 +01:00
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* Copyright (C) 2007-2011 Nokia Corporation
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2008-08-19 10:08:40 +02:00
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*
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2010-12-22 05:05:16 +01:00
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* Paul Walmsley
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2008-08-19 10:08:40 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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2010-12-22 04:01:20 +01:00
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*
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* XXX This should be moved to the mach-omap2/ directory at the earliest
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* opportunity.
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2008-08-19 10:08:40 +02:00
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*/
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2010-12-22 05:05:16 +01:00
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#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
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#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
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2008-08-19 10:08:40 +02:00
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#include <linux/types.h>
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#include <linux/list.h>
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2010-12-22 05:05:16 +01:00
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#include <linux/atomic.h>
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2008-08-19 10:08:40 +02:00
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2009-10-20 18:40:47 +02:00
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#include <plat/cpu.h>
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2008-08-19 10:08:40 +02:00
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2011-03-23 15:22:23 +01:00
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#include "voltage.h"
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2008-08-19 10:08:40 +02:00
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/* Powerdomain basic power states */
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#define PWRDM_POWER_OFF 0x0
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#define PWRDM_POWER_RET 0x1
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#define PWRDM_POWER_INACTIVE 0x2
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#define PWRDM_POWER_ON 0x3
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2009-12-09 00:33:12 +01:00
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#define PWRDM_MAX_PWRSTS 4
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2008-08-19 10:08:40 +02:00
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/* Powerdomain allowable state bitfields */
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2010-05-19 04:24:01 +02:00
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#define PWRSTS_ON (1 << PWRDM_POWER_ON)
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2011-03-08 03:28:15 +01:00
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#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
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#define PWRSTS_RET (1 << PWRDM_POWER_RET)
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2010-09-27 22:02:56 +02:00
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#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
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2008-08-19 10:08:40 +02:00
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2011-03-08 03:28:15 +01:00
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#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
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#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
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#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
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#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
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2008-08-19 10:08:40 +02:00
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[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 02:09:37 +02:00
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/* Powerdomain flags */
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#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
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2009-12-09 00:33:15 +01:00
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#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
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* in MEM bank 1 position. This is
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* true for OMAP3430
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*/
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2010-05-19 04:24:03 +02:00
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#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
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* support to transition from a
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* sleep state to a lower sleep
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* state without waking up the
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* powerdomain
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*/
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[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 02:09:37 +02:00
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2008-08-19 10:08:40 +02:00
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/*
|
2010-01-27 04:12:52 +01:00
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* Number of memory banks that are power-controllable. On OMAP4430, the
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* maximum is 5.
|
2008-08-19 10:08:40 +02:00
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*/
|
2010-01-27 04:12:52 +01:00
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#define PWRDM_MAX_MEM_BANKS 5
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2008-08-19 10:08:40 +02:00
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2008-08-19 10:08:44 +02:00
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/*
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* Maximum number of clockdomains that can be associated with a powerdomain.
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 08:47:27 +02:00
|
|
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* PER powerdomain on AM33XX is the worst case
|
2008-08-19 10:08:44 +02:00
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*/
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 08:47:27 +02:00
|
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#define PWRDM_MAX_CLKDMS 11
|
2008-08-19 10:08:44 +02:00
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2008-08-19 10:08:40 +02:00
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/* XXX A completely arbitrary number. What is reasonable here? */
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#define PWRDM_TRANSITION_BAILOUT 100000
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|
2008-08-19 10:08:44 +02:00
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struct clockdomain;
|
2008-08-19 10:08:40 +02:00
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struct powerdomain;
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|
2010-01-27 04:13:02 +01:00
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/**
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* struct powerdomain - OMAP powerdomain
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* @name: Powerdomain name
|
2011-03-23 15:22:23 +01:00
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* @voltdm: voltagedomain containing this powerdomain
|
2010-01-27 04:13:02 +01:00
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* @prcm_offs: the address offset from CM_BASE/PRM_BASE
|
2010-12-22 05:05:14 +01:00
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* @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
|
2010-01-27 04:13:02 +01:00
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* @pwrsts: Possible powerdomain power states
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* @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
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* @flags: Powerdomain flags
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* @banks: Number of software-controllable memory banks in this powerdomain
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* @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
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* @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
|
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* @pwrdm_clkdms: Clockdomains in this powerdomain
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* @node: list_head linking all powerdomains
|
2011-03-17 00:13:15 +01:00
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* @voltdm_node: list_head linking all powerdomains in a voltagedomain
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 08:47:27 +02:00
|
|
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* @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
|
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* @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
|
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* @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
|
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* in @pwrstctrl_offs
|
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* @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
|
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* @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
|
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* @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
|
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* @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
|
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* in @pwrstctrl_offs
|
2010-01-27 04:13:02 +01:00
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* @state:
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* @state_counter:
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* @timer:
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* @state_timer:
|
2010-12-22 05:05:14 +01:00
|
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*
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* @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
|
2010-01-27 04:13:02 +01:00
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*/
|
2008-08-19 10:08:40 +02:00
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struct powerdomain {
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const char *name;
|
2011-03-23 15:22:23 +01:00
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union {
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const char *name;
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struct voltagedomain *ptr;
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} voltdm;
|
2010-01-27 04:13:01 +01:00
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const s16 prcm_offs;
|
2008-08-19 10:08:40 +02:00
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const u8 pwrsts;
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const u8 pwrsts_logic_ret;
|
[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 02:09:37 +02:00
|
|
|
const u8 flags;
|
2008-08-19 10:08:40 +02:00
|
|
|
const u8 banks;
|
|
|
|
const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
|
|
|
|
const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
|
2010-12-22 05:05:14 +01:00
|
|
|
const u8 prcm_partition;
|
2008-08-19 10:08:44 +02:00
|
|
|
struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
|
2008-08-19 10:08:40 +02:00
|
|
|
struct list_head node;
|
2011-03-17 00:13:15 +01:00
|
|
|
struct list_head voltdm_node;
|
2008-10-15 16:48:43 +02:00
|
|
|
int state;
|
2009-12-09 00:33:12 +01:00
|
|
|
unsigned state_counter[PWRDM_MAX_PWRSTS];
|
2010-02-24 20:05:50 +01:00
|
|
|
unsigned ret_logic_off_counter;
|
|
|
|
unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
|
2008-10-15 17:13:48 +02:00
|
|
|
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 08:47:27 +02:00
|
|
|
const u8 pwrstctrl_offs;
|
|
|
|
const u8 pwrstst_offs;
|
|
|
|
const u32 logicretstate_mask;
|
|
|
|
const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
|
|
|
|
const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
|
|
|
|
const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
|
|
|
|
const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
|
|
|
|
|
2008-10-15 17:13:48 +02:00
|
|
|
#ifdef CONFIG_PM_DEBUG
|
|
|
|
s64 timer;
|
2009-12-09 00:33:12 +01:00
|
|
|
s64 state_timer[PWRDM_MAX_PWRSTS];
|
2008-10-15 17:13:48 +02:00
|
|
|
#endif
|
2008-08-19 10:08:40 +02:00
|
|
|
};
|
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2010-12-22 04:01:18 +01:00
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/**
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2011-03-31 03:57:33 +02:00
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* struct pwrdm_ops - Arch specific function implementations
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2010-12-22 04:01:18 +01:00
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* @pwrdm_set_next_pwrst: Set the target power state for a pd
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* @pwrdm_read_next_pwrst: Read the target power state set for a pd
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* @pwrdm_read_pwrst: Read the current power state of a pd
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* @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
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* @pwrdm_set_logic_retst: Set the logic state in RET for a pd
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* @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
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* @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
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* @pwrdm_read_logic_pwrst: Read the current logic state of a pd
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* @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
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* @pwrdm_read_logic_retst: Read the logic state in RET for a pd
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* @pwrdm_read_mem_pwrst: Read the current memory state of a pd
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* @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
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* @pwrdm_read_mem_retst: Read the memory state in RET for a pd
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* @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
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* @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
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* @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
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* @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
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* @pwrdm_wait_transition: Wait for a pd state transition to complete
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*/
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struct pwrdm_ops {
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int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
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int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
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int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
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int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
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int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
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int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
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int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
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int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
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int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
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};
|
2008-08-19 10:08:40 +02:00
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2011-09-15 00:01:21 +02:00
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int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
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int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
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int pwrdm_complete_init(void);
|
2008-08-19 10:08:40 +02:00
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struct powerdomain *pwrdm_lookup(const char *name);
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|
2008-10-15 17:13:47 +02:00
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int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
|
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void *user);
|
2009-10-01 09:01:55 +02:00
|
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int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
|
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void *user);
|
2008-08-19 10:08:40 +02:00
|
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|
2008-08-19 10:08:44 +02:00
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int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
|
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int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
|
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int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
|
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int (*fn)(struct powerdomain *pwrdm,
|
|
|
|
struct clockdomain *clkdm));
|
2011-03-16 23:52:47 +01:00
|
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|
struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
|
2008-08-19 10:08:44 +02:00
|
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|
2008-08-19 10:08:40 +02:00
|
|
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int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
|
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int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
|
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int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
|
2009-01-28 03:12:50 +01:00
|
|
|
int pwrdm_read_pwrst(struct powerdomain *pwrdm);
|
2008-08-19 10:08:40 +02:00
|
|
|
int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
|
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|
int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
|
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int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
|
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|
|
int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
|
|
|
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int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
|
|
|
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|
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int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
|
|
|
|
int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
|
2010-02-24 20:05:49 +01:00
|
|
|
int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
|
2008-08-19 10:08:40 +02:00
|
|
|
int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
|
|
|
|
int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
|
2010-02-24 20:05:49 +01:00
|
|
|
int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
|
2008-08-19 10:08:40 +02:00
|
|
|
|
[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 02:09:37 +02:00
|
|
|
int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
|
|
|
|
int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
|
|
|
|
bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
|
|
|
|
|
2008-08-19 10:08:40 +02:00
|
|
|
int pwrdm_wait_transition(struct powerdomain *pwrdm);
|
|
|
|
|
2008-10-15 16:48:43 +02:00
|
|
|
int pwrdm_state_switch(struct powerdomain *pwrdm);
|
2012-05-12 01:00:24 +02:00
|
|
|
int pwrdm_pre_transition(struct powerdomain *pwrdm);
|
|
|
|
int pwrdm_post_transition(struct powerdomain *pwrdm);
|
2010-10-08 18:58:35 +02:00
|
|
|
int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
|
2011-06-09 15:56:23 +02:00
|
|
|
int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
|
2011-03-08 03:28:15 +01:00
|
|
|
bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
|
2008-10-15 16:48:43 +02:00
|
|
|
|
2011-09-14 19:34:21 +02:00
|
|
|
extern void omap242x_powerdomains_init(void);
|
|
|
|
extern void omap243x_powerdomains_init(void);
|
2010-12-22 04:01:20 +01:00
|
|
|
extern void omap3xxx_powerdomains_init(void);
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 08:47:27 +02:00
|
|
|
extern void am33xx_powerdomains_init(void);
|
2010-12-22 04:01:20 +01:00
|
|
|
extern void omap44xx_powerdomains_init(void);
|
|
|
|
|
2010-12-22 05:05:16 +01:00
|
|
|
extern struct pwrdm_ops omap2_pwrdm_operations;
|
|
|
|
extern struct pwrdm_ops omap3_pwrdm_operations;
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 08:47:27 +02:00
|
|
|
extern struct pwrdm_ops am33xx_pwrdm_operations;
|
2010-12-22 05:05:16 +01:00
|
|
|
extern struct pwrdm_ops omap4_pwrdm_operations;
|
|
|
|
|
|
|
|
/* Common Internal functions used across OMAP rev's */
|
|
|
|
extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
|
|
|
|
extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
|
|
|
|
extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
|
|
|
|
|
|
|
|
extern struct powerdomain wkup_omap2_pwrdm;
|
|
|
|
extern struct powerdomain gfx_omap2_pwrdm;
|
|
|
|
|
|
|
|
|
2008-08-19 10:08:40 +02:00
|
|
|
#endif
|