2012-02-08 21:47:39 +01:00
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/* linux/drivers/video/exynos/exynos_mipi_dsi_common.c
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*
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* Samsung SoC MIPI-DSI common driver.
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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*
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* InKi Dae, <inki.dae@samsung.com>
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* Donghwa Lee, <dh09.lee@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/mutex.h>
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#include <linux/wait.h>
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#include <linux/fs.h>
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#include <linux/mm.h>
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#include <linux/fb.h>
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#include <linux/ctype.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/memory.h>
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#include <linux/delay.h>
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2013-02-14 23:26:51 +01:00
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#include <linux/irqreturn.h>
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2012-02-08 21:47:39 +01:00
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#include <linux/kthread.h>
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#include <video/mipi_display.h>
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#include <video/exynos_mipi_dsim.h>
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#include "exynos_mipi_dsi_regs.h"
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#include "exynos_mipi_dsi_lowlevel.h"
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#include "exynos_mipi_dsi_common.h"
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#define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)
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#define MIPI_RX_FIFO_READ_DONE 0x30800002
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#define MIPI_MAX_RX_FIFO 20
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#define MHZ (1000 * 1000)
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#define FIN_HZ (24 * MHZ)
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#define DFIN_PLL_MIN_HZ (6 * MHZ)
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#define DFIN_PLL_MAX_HZ (12 * MHZ)
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#define DFVCO_MIN_HZ (500 * MHZ)
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#define DFVCO_MAX_HZ (1000 * MHZ)
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#define TRY_GET_FIFO_TIMEOUT (5000 * 2)
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#define TRY_FIFO_CLEAR (10)
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/* MIPI-DSIM status types. */
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enum {
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DSIM_STATE_INIT, /* should be initialized. */
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DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
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DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
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DSIM_STATE_ULPS
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};
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/* define DSI lane types. */
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enum {
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DSIM_LANE_CLOCK = (1 << 0),
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DSIM_LANE_DATA0 = (1 << 1),
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DSIM_LANE_DATA1 = (1 << 2),
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DSIM_LANE_DATA2 = (1 << 3),
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DSIM_LANE_DATA3 = (1 << 4)
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};
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static unsigned int dpll_table[15] = {
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100, 120, 170, 220, 270,
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320, 390, 450, 510, 560,
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640, 690, 770, 870, 950
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};
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irqreturn_t exynos_mipi_dsi_interrupt_handler(int irq, void *dev_id)
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{
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2012-05-09 07:33:29 +02:00
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struct mipi_dsim_device *dsim = dev_id;
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unsigned int intsrc, intmsk;
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2012-02-08 21:47:39 +01:00
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intsrc = exynos_mipi_dsi_read_interrupt(dsim);
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intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim);
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2012-05-09 07:33:29 +02:00
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intmsk = ~intmsk & intsrc;
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2012-02-08 21:47:39 +01:00
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2012-05-09 07:33:29 +02:00
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if (intsrc & INTMSK_RX_DONE) {
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2012-02-08 21:47:39 +01:00
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complete(&dsim_rd_comp);
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dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n");
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2012-05-09 07:33:29 +02:00
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}
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if (intsrc & INTMSK_FIFO_EMPTY) {
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2012-02-08 21:47:39 +01:00
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complete(&dsim_wr_comp);
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dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n");
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}
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exynos_mipi_dsi_clear_interrupt(dsim, intmsk);
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return IRQ_HANDLED;
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}
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/*
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* write long packet to mipi dsi slave
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* @dsim: mipi dsim device structure.
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* @data0: packet data to send.
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* @data1: size of packet data
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*/
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static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
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const unsigned char *data0, unsigned int data_size)
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{
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unsigned int data_cnt = 0, payload = 0;
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/* in case that data count is more then 4 */
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for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) {
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/*
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* after sending 4bytes per one time,
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* send remainder data less then 4.
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*/
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if ((data_size - data_cnt) < 4) {
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if ((data_size - data_cnt) == 3) {
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payload = data0[data_cnt] |
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data0[data_cnt + 1] << 8 |
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data0[data_cnt + 2] << 16;
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dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
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payload, data0[data_cnt],
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data0[data_cnt + 1],
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data0[data_cnt + 2]);
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} else if ((data_size - data_cnt) == 2) {
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payload = data0[data_cnt] |
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data0[data_cnt + 1] << 8;
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dev_dbg(dsim->dev,
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"count = 2 payload = %x, %x %x\n", payload,
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data0[data_cnt],
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data0[data_cnt + 1]);
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} else if ((data_size - data_cnt) == 1) {
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payload = data0[data_cnt];
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}
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exynos_mipi_dsi_wr_tx_data(dsim, payload);
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/* send 4bytes per one time. */
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} else {
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payload = data0[data_cnt] |
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data0[data_cnt + 1] << 8 |
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data0[data_cnt + 2] << 16 |
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data0[data_cnt + 3] << 24;
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dev_dbg(dsim->dev,
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"count = 4 payload = %x, %x %x %x %x\n",
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payload, *(u8 *)(data0 + data_cnt),
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data0[data_cnt + 1],
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data0[data_cnt + 2],
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data0[data_cnt + 3]);
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exynos_mipi_dsi_wr_tx_data(dsim, payload);
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}
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}
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}
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int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
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const unsigned char *data0, unsigned int data_size)
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{
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unsigned int check_rx_ack = 0;
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if (dsim->state == DSIM_STATE_ULPS) {
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dev_err(dsim->dev, "state is ULPS.\n");
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return -EINVAL;
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}
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/* FIXME!!! why does it need this delay? */
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msleep(20);
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mutex_lock(&dsim->lock);
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switch (data_id) {
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/* short packet types of packet types for command. */
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case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
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case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
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case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
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case MIPI_DSI_DCS_SHORT_WRITE:
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
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exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
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if (check_rx_ack) {
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/* process response func should be implemented */
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mutex_unlock(&dsim->lock);
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return 0;
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} else {
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mutex_unlock(&dsim->lock);
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return -EINVAL;
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}
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/* general command */
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case MIPI_DSI_COLOR_MODE_OFF:
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case MIPI_DSI_COLOR_MODE_ON:
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case MIPI_DSI_SHUTDOWN_PERIPHERAL:
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case MIPI_DSI_TURN_ON_PERIPHERAL:
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exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
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if (check_rx_ack) {
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/* process response func should be implemented. */
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mutex_unlock(&dsim->lock);
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return 0;
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} else {
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mutex_unlock(&dsim->lock);
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return -EINVAL;
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}
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/* packet types for video data */
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case MIPI_DSI_V_SYNC_START:
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case MIPI_DSI_V_SYNC_END:
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case MIPI_DSI_H_SYNC_START:
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case MIPI_DSI_H_SYNC_END:
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case MIPI_DSI_END_OF_TRANSMISSION:
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mutex_unlock(&dsim->lock);
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return 0;
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/* long packet type and null packet */
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case MIPI_DSI_NULL_PACKET:
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case MIPI_DSI_BLANKING_PACKET:
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mutex_unlock(&dsim->lock);
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return 0;
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case MIPI_DSI_GENERIC_LONG_WRITE:
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case MIPI_DSI_DCS_LONG_WRITE:
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{
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unsigned int size, payload = 0;
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INIT_COMPLETION(dsim_wr_comp);
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size = data_size * 4;
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/* if data count is less then 4, then send 3bytes data. */
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if (data_size < 4) {
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payload = data0[0] |
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data0[1] << 8 |
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data0[2] << 16;
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exynos_mipi_dsi_wr_tx_data(dsim, payload);
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dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
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data_size, payload, data0[0],
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data0[1], data0[2]);
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/* in case that data count is more then 4 */
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} else
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exynos_mipi_dsi_long_data_wr(dsim, data0, data_size);
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/* put data into header fifo */
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exynos_mipi_dsi_wr_tx_header(dsim, data_id, data_size & 0xff,
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(data_size & 0xff00) >> 8);
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if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp,
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MIPI_FIFO_TIMEOUT)) {
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dev_warn(dsim->dev, "command write timeout.\n");
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mutex_unlock(&dsim->lock);
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return -EAGAIN;
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}
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if (check_rx_ack) {
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/* process response func should be implemented. */
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mutex_unlock(&dsim->lock);
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return 0;
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} else {
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mutex_unlock(&dsim->lock);
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return -EINVAL;
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}
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}
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/* packet typo for video data */
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case MIPI_DSI_PACKED_PIXEL_STREAM_16:
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case MIPI_DSI_PACKED_PIXEL_STREAM_18:
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case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
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case MIPI_DSI_PACKED_PIXEL_STREAM_24:
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if (check_rx_ack) {
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/* process response func should be implemented. */
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mutex_unlock(&dsim->lock);
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return 0;
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} else {
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mutex_unlock(&dsim->lock);
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return -EINVAL;
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}
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default:
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dev_warn(dsim->dev,
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"data id %x is not supported current DSI spec.\n",
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data_id);
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mutex_unlock(&dsim->lock);
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return -EINVAL;
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}
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}
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static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,
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unsigned int req_size, unsigned int rx_data, u8 *rx_buf)
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{
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unsigned int rcv_pkt, i, j;
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u16 rxsize;
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/* for long packet */
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rxsize = (u16)((rx_data & 0x00ffff00) >> 8);
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dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize);
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if (rxsize != req_size) {
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dev_dbg(dsim->dev,
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"received size mismatch received: %d, requested: %d\n",
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rxsize, req_size);
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goto err;
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}
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for (i = 0; i < (rxsize >> 2); i++) {
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rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
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dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
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for (j = 0; j < 4; j++) {
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rx_buf[(i * 4) + j] =
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(u8)(rcv_pkt >> (j * 8)) & 0xff;
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dev_dbg(dsim->dev, "received value : %02x\n",
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(rcv_pkt >> (j * 8)) & 0xff);
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}
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}
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if (rxsize % 4) {
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rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
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dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
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for (j = 0; j < (rxsize % 4); j++) {
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rx_buf[(i * 4) + j] =
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(u8)(rcv_pkt >> (j * 8)) & 0xff;
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dev_dbg(dsim->dev, "received value : %02x\n",
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(rcv_pkt >> (j * 8)) & 0xff);
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}
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}
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return rxsize;
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err:
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return -EINVAL;
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}
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static unsigned int exynos_mipi_dsi_response_size(unsigned int req_size)
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{
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switch (req_size) {
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case 1:
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return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE;
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case 2:
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return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE;
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default:
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return MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE;
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}
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}
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int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
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|
|
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unsigned int data0, unsigned int req_size, u8 *rx_buf)
|
|
|
|
{
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|
|
|
unsigned int rx_data, rcv_pkt, i;
|
|
|
|
u8 response = 0;
|
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|
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u16 rxsize;
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if (dsim->state == DSIM_STATE_ULPS) {
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dev_err(dsim->dev, "state is ULPS.\n");
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return -EINVAL;
|
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}
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|
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/* FIXME!!! */
|
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msleep(20);
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mutex_lock(&dsim->lock);
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INIT_COMPLETION(dsim_rd_comp);
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exynos_mipi_dsi_rd_tx_header(dsim,
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MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, req_size);
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response = exynos_mipi_dsi_response_size(req_size);
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switch (data_id) {
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case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
|
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case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
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case MIPI_DSI_DCS_READ:
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exynos_mipi_dsi_rd_tx_header(dsim,
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data_id, data0);
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/* process response func should be implemented. */
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break;
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default:
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dev_warn(dsim->dev,
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"data id %x is not supported current DSI spec.\n",
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data_id);
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return -EINVAL;
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}
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if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp,
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MIPI_FIFO_TIMEOUT)) {
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pr_err("RX done interrupt timeout\n");
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mutex_unlock(&dsim->lock);
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return 0;
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}
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msleep(20);
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rx_data = exynos_mipi_dsi_rd_rx_fifo(dsim);
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if ((u8)(rx_data & 0xff) != response) {
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printk(KERN_ERR
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"mipi dsi wrong response rx_data : %x, response:%x\n",
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rx_data, response);
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goto clear_rx_fifo;
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}
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if (req_size <= 2) {
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/* for short packet */
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for (i = 0; i < req_size; i++)
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rx_buf[i] = (rx_data >> (8 + (i * 8))) & 0xff;
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rxsize = req_size;
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} else {
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/* for long packet */
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rxsize = exynos_mipi_dsi_long_data_rd(dsim, req_size, rx_data,
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rx_buf);
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if (rxsize != req_size)
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goto clear_rx_fifo;
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}
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rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
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msleep(20);
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if (rcv_pkt != MIPI_RX_FIFO_READ_DONE) {
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dev_info(dsim->dev,
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"Can't found RX FIFO READ DONE FLAG : %x\n", rcv_pkt);
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goto clear_rx_fifo;
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}
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mutex_unlock(&dsim->lock);
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return rxsize;
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clear_rx_fifo:
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i = 0;
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while (1) {
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rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
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if ((rcv_pkt == MIPI_RX_FIFO_READ_DONE)
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|| (i > MIPI_MAX_RX_FIFO))
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break;
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dev_dbg(dsim->dev,
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"mipi dsi clear rx fifo : %08x\n", rcv_pkt);
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i++;
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}
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dev_info(dsim->dev,
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"mipi dsi rx done count : %d, rcv_pkt : %08x\n", i, rcv_pkt);
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mutex_unlock(&dsim->lock);
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return 0;
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}
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static int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim,
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unsigned int enable)
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{
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int sw_timeout;
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if (enable) {
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sw_timeout = 1000;
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exynos_mipi_dsi_enable_pll(dsim, 1);
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while (1) {
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sw_timeout--;
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if (exynos_mipi_dsi_is_pll_stable(dsim))
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return 0;
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if (sw_timeout == 0)
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return -EINVAL;
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}
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} else
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exynos_mipi_dsi_enable_pll(dsim, 0);
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return 0;
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}
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static unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
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unsigned int pre_divider, unsigned int main_divider,
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unsigned int scaler)
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{
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unsigned long dfin_pll, dfvco, dpll_out;
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unsigned int i, freq_band = 0xf;
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dfin_pll = (FIN_HZ / pre_divider);
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/******************************************************
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* Serial Clock(=ByteClk X 8) FreqBand[3:0] *
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******************************************************
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* ~ 99.99 MHz 0000
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* 100 ~ 119.99 MHz 0001
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* 120 ~ 159.99 MHz 0010
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* 160 ~ 199.99 MHz 0011
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* 200 ~ 239.99 MHz 0100
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* 140 ~ 319.99 MHz 0101
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* 320 ~ 389.99 MHz 0110
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* 390 ~ 449.99 MHz 0111
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* 450 ~ 509.99 MHz 1000
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* 510 ~ 559.99 MHz 1001
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* 560 ~ 639.99 MHz 1010
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* 640 ~ 689.99 MHz 1011
|
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* 690 ~ 769.99 MHz 1100
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* 770 ~ 869.99 MHz 1101
|
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|
* 870 ~ 949.99 MHz 1110
|
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|
|
* 950 ~ 1000 MHz 1111
|
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|
|
******************************************************/
|
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|
if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
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|
|
dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");
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|
exynos_mipi_dsi_enable_afc(dsim, 0, 0);
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} else {
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if (dfin_pll < 7 * MHZ)
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exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
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else if (dfin_pll < 8 * MHZ)
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|
exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
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else if (dfin_pll < 9 * MHZ)
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|
exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
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else if (dfin_pll < 10 * MHZ)
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|
|
exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
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|
else if (dfin_pll < 11 * MHZ)
|
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|
|
exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
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|
else
|
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|
|
exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
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|
|
}
|
|
|
|
|
|
|
|
dfvco = dfin_pll * main_divider;
|
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|
|
dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
|
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|
|
dfvco, dfin_pll, main_divider);
|
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|
|
if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
|
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|
|
dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");
|
|
|
|
|
|
|
|
dpll_out = dfvco / (1 << scaler);
|
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|
|
dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
|
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|
|
dpll_out, dfvco, scaler);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
|
|
|
|
if (dpll_out < dpll_table[i] * MHZ) {
|
|
|
|
freq_band = i;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
|
|
|
|
|
|
|
|
exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
|
|
|
|
|
|
|
|
exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
|
|
|
|
exynos_mipi_dsi_prep_ctrl(dsim, 0);
|
|
|
|
|
|
|
|
/* Freq Band */
|
|
|
|
exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
|
|
|
|
|
|
|
|
/* Stable time */
|
|
|
|
exynos_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);
|
|
|
|
|
|
|
|
/* Enable PLL */
|
|
|
|
dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
|
|
|
|
(dpll_out / MHZ));
|
|
|
|
|
|
|
|
return dpll_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
|
|
|
|
unsigned int byte_clk_sel, unsigned int enable)
|
|
|
|
{
|
|
|
|
unsigned int esc_div;
|
|
|
|
unsigned long esc_clk_error_rate;
|
|
|
|
unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
|
|
|
|
|
|
|
|
if (enable) {
|
|
|
|
dsim->e_clk_src = byte_clk_sel;
|
|
|
|
|
|
|
|
/* Escape mode clock and byte clock source */
|
|
|
|
exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
|
|
|
|
|
|
|
|
/* DPHY, DSIM Link : D-PHY clock out */
|
|
|
|
if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
|
|
|
|
hs_clk = exynos_mipi_dsi_change_pll(dsim,
|
|
|
|
dsim->dsim_config->p, dsim->dsim_config->m,
|
|
|
|
dsim->dsim_config->s);
|
|
|
|
if (hs_clk == 0) {
|
|
|
|
dev_err(dsim->dev,
|
|
|
|
"failed to get hs clock.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
byte_clk = hs_clk / 8;
|
|
|
|
exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
|
|
|
|
exynos_mipi_dsi_pll_on(dsim, 1);
|
|
|
|
/* DPHY : D-PHY clock out, DSIM link : external clock out */
|
|
|
|
} else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) {
|
|
|
|
dev_warn(dsim->dev, "this project is not support\n");
|
|
|
|
dev_warn(dsim->dev,
|
|
|
|
"external clock source for MIPI DSIM.\n");
|
|
|
|
} else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) {
|
|
|
|
dev_warn(dsim->dev, "this project is not support\n");
|
|
|
|
dev_warn(dsim->dev,
|
|
|
|
"external clock source for MIPI DSIM\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* escape clock divider */
|
|
|
|
esc_div = byte_clk / (dsim->dsim_config->esc_clk);
|
|
|
|
dev_dbg(dsim->dev,
|
|
|
|
"esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
|
|
|
|
esc_div, byte_clk, dsim->dsim_config->esc_clk);
|
|
|
|
if ((byte_clk / esc_div) >= (20 * MHZ) ||
|
|
|
|
(byte_clk / esc_div) >
|
|
|
|
dsim->dsim_config->esc_clk)
|
|
|
|
esc_div += 1;
|
|
|
|
|
|
|
|
escape_clk = byte_clk / esc_div;
|
|
|
|
dev_dbg(dsim->dev,
|
|
|
|
"escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
|
|
|
|
escape_clk, byte_clk, esc_div);
|
|
|
|
|
|
|
|
/* enable escape clock. */
|
|
|
|
exynos_mipi_dsi_enable_byte_clock(dsim, 1);
|
|
|
|
|
|
|
|
/* enable byte clk and escape clock */
|
|
|
|
exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
|
|
|
|
/* escape clock on lane */
|
|
|
|
exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
|
|
|
|
(DSIM_LANE_CLOCK | dsim->data_lane), 1);
|
|
|
|
|
|
|
|
dev_dbg(dsim->dev, "byte clock is %luMHz\n",
|
|
|
|
(byte_clk / MHZ));
|
|
|
|
dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
|
|
|
|
(dsim->dsim_config->esc_clk / MHZ));
|
|
|
|
dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
|
|
|
|
dev_dbg(dsim->dev, "escape clock is %luMHz\n",
|
|
|
|
((byte_clk / esc_div) / MHZ));
|
|
|
|
|
|
|
|
if ((byte_clk / esc_div) > escape_clk) {
|
|
|
|
esc_clk_error_rate = escape_clk /
|
|
|
|
(byte_clk / esc_div);
|
|
|
|
dev_warn(dsim->dev, "error rate is %lu over.\n",
|
|
|
|
(esc_clk_error_rate / 100));
|
|
|
|
} else if ((byte_clk / esc_div) < (escape_clk)) {
|
|
|
|
esc_clk_error_rate = (byte_clk / esc_div) /
|
|
|
|
escape_clk;
|
|
|
|
dev_warn(dsim->dev, "error rate is %lu under.\n",
|
|
|
|
(esc_clk_error_rate / 100));
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
|
|
|
|
(DSIM_LANE_CLOCK | dsim->data_lane), 0);
|
|
|
|
exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
|
|
|
|
|
|
|
|
/* disable escape clock. */
|
|
|
|
exynos_mipi_dsi_enable_byte_clock(dsim, 0);
|
|
|
|
|
|
|
|
if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
|
|
|
|
exynos_mipi_dsi_pll_on(dsim, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
|
|
|
|
{
|
|
|
|
dsim->state = DSIM_STATE_INIT;
|
|
|
|
|
|
|
|
switch (dsim->dsim_config->e_no_data_lane) {
|
|
|
|
case DSIM_DATA_LANE_1:
|
|
|
|
dsim->data_lane = DSIM_LANE_DATA0;
|
|
|
|
break;
|
|
|
|
case DSIM_DATA_LANE_2:
|
|
|
|
dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
|
|
|
|
break;
|
|
|
|
case DSIM_DATA_LANE_3:
|
|
|
|
dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
|
|
|
|
DSIM_LANE_DATA2;
|
|
|
|
break;
|
|
|
|
case DSIM_DATA_LANE_4:
|
|
|
|
dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
|
|
|
|
DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_info(dsim->dev, "data lane is invalid.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
};
|
|
|
|
|
|
|
|
exynos_mipi_dsi_sw_reset(dsim);
|
|
|
|
exynos_mipi_dsi_func_reset(dsim);
|
|
|
|
|
|
|
|
exynos_mipi_dsi_dp_dn_swap(dsim, 0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim)
|
|
|
|
{
|
|
|
|
unsigned int src = 0;
|
|
|
|
|
|
|
|
src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE);
|
|
|
|
exynos_mipi_dsi_set_interrupt(dsim, src, 1);
|
|
|
|
|
|
|
|
src = 0;
|
|
|
|
src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY);
|
|
|
|
exynos_mipi_dsi_set_interrupt_mask(dsim, src, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
|
|
|
|
unsigned int enable)
|
|
|
|
{
|
|
|
|
/* enable only frame done interrupt */
|
|
|
|
exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
|
|
|
|
unsigned int enable)
|
|
|
|
{
|
|
|
|
|
|
|
|
/* consider Main display and Sub display. */
|
|
|
|
|
|
|
|
exynos_mipi_dsi_set_main_stand_by(dsim, enable);
|
|
|
|
}
|
|
|
|
|
|
|
|
int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
|
|
|
|
struct mipi_dsim_config *dsim_config)
|
|
|
|
{
|
|
|
|
struct mipi_dsim_platform_data *dsim_pd;
|
|
|
|
struct fb_videomode *timing;
|
|
|
|
|
|
|
|
dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;
|
|
|
|
timing = (struct fb_videomode *)dsim_pd->lcd_panel_info;
|
|
|
|
|
|
|
|
/* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
|
|
|
|
if (dsim_config->e_interface == (u32) DSIM_VIDEO) {
|
|
|
|
if (dsim_config->auto_vertical_cnt == 0) {
|
|
|
|
exynos_mipi_dsi_set_main_disp_vporch(dsim,
|
|
|
|
dsim_config->cmd_allow,
|
2012-03-08 16:28:54 +01:00
|
|
|
timing->lower_margin,
|
|
|
|
timing->upper_margin);
|
2012-02-08 21:47:39 +01:00
|
|
|
exynos_mipi_dsi_set_main_disp_hporch(dsim,
|
2012-03-08 16:28:54 +01:00
|
|
|
timing->right_margin,
|
|
|
|
timing->left_margin);
|
2012-02-08 21:47:39 +01:00
|
|
|
exynos_mipi_dsi_set_main_disp_sync_area(dsim,
|
|
|
|
timing->vsync_len,
|
|
|
|
timing->hsync_len);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres,
|
|
|
|
timing->yres);
|
|
|
|
|
|
|
|
exynos_mipi_dsi_display_config(dsim, dsim_config);
|
|
|
|
|
|
|
|
dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n",
|
|
|
|
timing->xres, timing->yres);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
|
|
|
|
{
|
|
|
|
unsigned int time_out = 100;
|
|
|
|
|
|
|
|
switch (dsim->state) {
|
|
|
|
case DSIM_STATE_INIT:
|
|
|
|
exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
|
|
|
|
|
|
|
|
/* dsi configuration */
|
|
|
|
exynos_mipi_dsi_init_config(dsim);
|
|
|
|
exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
|
|
|
|
exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
|
|
|
|
|
|
|
|
/* set clock configuration */
|
|
|
|
exynos_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);
|
|
|
|
|
|
|
|
/* check clock and data lane state are stop state */
|
|
|
|
while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
|
|
|
|
time_out--;
|
|
|
|
if (time_out == 0) {
|
|
|
|
dev_err(dsim->dev,
|
|
|
|
"DSI Master is not stop state.\n");
|
|
|
|
dev_err(dsim->dev,
|
|
|
|
"Check initialization process\n");
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (time_out != 0) {
|
|
|
|
dev_info(dsim->dev,
|
|
|
|
"DSI Master driver has been completed.\n");
|
|
|
|
dev_info(dsim->dev, "DSI Master state is stop state\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
dsim->state = DSIM_STATE_STOP;
|
|
|
|
|
|
|
|
/* BTA sequence counters */
|
|
|
|
exynos_mipi_dsi_set_stop_state_counter(dsim,
|
|
|
|
dsim->dsim_config->stop_holding_cnt);
|
|
|
|
exynos_mipi_dsi_set_bta_timeout(dsim,
|
|
|
|
dsim->dsim_config->bta_timeout);
|
|
|
|
exynos_mipi_dsi_set_lpdr_timeout(dsim,
|
|
|
|
dsim->dsim_config->rx_timeout);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
dev_info(dsim->dev, "DSI Master is already init.\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
|
|
|
|
{
|
|
|
|
if (dsim->state != DSIM_STATE_STOP) {
|
|
|
|
dev_warn(dsim->dev, "DSIM is not in stop state.\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dsim->e_clk_src == DSIM_EXT_CLK_BYPASS) {
|
|
|
|
dev_warn(dsim->dev, "clock source is external bypass.\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dsim->state = DSIM_STATE_HSCLKEN;
|
|
|
|
|
|
|
|
/* set LCDC and CPU transfer mode to HS. */
|
|
|
|
exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
|
|
|
|
exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
|
|
|
|
exynos_mipi_dsi_enable_hs_clock(dsim, 1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
|
|
|
|
unsigned int mode)
|
|
|
|
{
|
|
|
|
if (mode) {
|
|
|
|
if (dsim->state != DSIM_STATE_HSCLKEN) {
|
|
|
|
dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
|
|
|
|
} else {
|
|
|
|
if (dsim->state == DSIM_STATE_INIT || dsim->state ==
|
|
|
|
DSIM_STATE_ULPS) {
|
|
|
|
dev_err(dsim->dev,
|
|
|
|
"DSI Master is not STOP or HSDT state.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
|
|
|
|
{
|
|
|
|
return _exynos_mipi_dsi_get_frame_done_status(dsim);
|
|
|
|
}
|
|
|
|
|
|
|
|
int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
|
|
|
|
{
|
|
|
|
_exynos_mipi_dsi_clear_frame_done(dsim);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,
|
|
|
|
unsigned int val)
|
|
|
|
{
|
|
|
|
int try = TRY_FIFO_CLEAR;
|
|
|
|
|
|
|
|
exynos_mipi_dsi_sw_reset_release(dsim);
|
|
|
|
exynos_mipi_dsi_func_reset(dsim);
|
|
|
|
|
|
|
|
do {
|
|
|
|
if (exynos_mipi_dsi_get_sw_reset_release(dsim)) {
|
|
|
|
exynos_mipi_dsi_init_interrupt(dsim);
|
|
|
|
dev_dbg(dsim->dev, "reset release done.\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
} while (--try);
|
|
|
|
|
|
|
|
dev_err(dsim->dev, "failed to clear dsim fifo.\n");
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
|
|
|
|
MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
|
|
|
|
MODULE_DESCRIPTION("Samusung SoC MIPI-DSI common driver");
|
|
|
|
MODULE_LICENSE("GPL");
|