2007-07-10 14:03:43 +02:00
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/*
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* TI DaVinci GPIO Support
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*
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2008-09-08 08:41:04 +02:00
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* Copyright (c) 2006-2007 David Brownell
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2007-07-10 14:03:43 +02:00
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* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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2008-12-07 20:46:23 +01:00
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#include <mach/cputype.h>
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2008-08-05 17:14:15 +02:00
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#include <mach/irqs.h>
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#include <mach/hardware.h>
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#include <mach/gpio.h>
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2007-07-10 14:03:43 +02:00
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#include <asm/mach/irq.h>
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2008-09-08 08:41:04 +02:00
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static DEFINE_SPINLOCK(gpio_lock);
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2007-07-10 14:03:43 +02:00
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2008-09-08 08:41:04 +02:00
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struct davinci_gpio {
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struct gpio_chip chip;
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struct gpio_controller *__iomem regs;
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};
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2007-07-10 14:03:43 +02:00
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2008-09-08 08:41:04 +02:00
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static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
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2007-07-10 14:03:43 +02:00
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2008-12-07 20:46:23 +01:00
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static unsigned __initdata ngpio;
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2007-07-10 14:03:43 +02:00
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/* create a non-inlined version */
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2008-12-07 20:46:23 +01:00
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static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
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2007-07-10 14:03:43 +02:00
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{
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return __gpio_to_controller(gpio);
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}
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2008-09-08 08:41:04 +02:00
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/*--------------------------------------------------------------------------*/
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2007-07-10 14:03:43 +02:00
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/*
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2008-09-08 08:41:04 +02:00
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* board setup code *MUST* set PINMUX0 and PINMUX1 as
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* needed, and enable the GPIO clock.
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2007-07-10 14:03:43 +02:00
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*/
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2008-09-08 08:41:04 +02:00
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static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
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2007-07-10 14:03:43 +02:00
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{
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2008-09-08 08:41:04 +02:00
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struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
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struct gpio_controller *__iomem g = d->regs;
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u32 temp;
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2007-07-10 14:03:43 +02:00
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2008-09-08 08:41:04 +02:00
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spin_lock(&gpio_lock);
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temp = __raw_readl(&g->dir);
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temp |= (1 << offset);
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__raw_writel(temp, &g->dir);
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spin_unlock(&gpio_lock);
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2007-07-10 14:03:43 +02:00
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2008-09-08 08:41:04 +02:00
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return 0;
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}
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2007-07-10 14:03:43 +02:00
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/*
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* Read the pin's value (works even if it's set up as output);
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* returns zero/nonzero.
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*
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* Note that changes are synched to the GPIO clock, so reading values back
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* right after you've set them may give old values.
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*/
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2008-09-08 08:41:04 +02:00
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static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
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2007-07-10 14:03:43 +02:00
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{
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2008-09-08 08:41:04 +02:00
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struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
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struct gpio_controller *__iomem g = d->regs;
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2007-07-10 14:03:43 +02:00
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2008-09-08 08:41:04 +02:00
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return (1 << offset) & __raw_readl(&g->in_data);
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2007-07-10 14:03:43 +02:00
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}
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2008-09-08 08:41:04 +02:00
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static int
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davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
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2007-07-10 14:03:43 +02:00
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{
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2008-09-08 08:41:04 +02:00
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struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
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struct gpio_controller *__iomem g = d->regs;
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2007-07-10 14:03:43 +02:00
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u32 temp;
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2008-09-08 08:41:04 +02:00
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u32 mask = 1 << offset;
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2007-07-10 14:03:43 +02:00
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spin_lock(&gpio_lock);
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temp = __raw_readl(&g->dir);
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2008-09-08 08:41:04 +02:00
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temp &= ~mask;
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__raw_writel(mask, value ? &g->set_data : &g->clr_data);
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2007-07-10 14:03:43 +02:00
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__raw_writel(temp, &g->dir);
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spin_unlock(&gpio_lock);
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return 0;
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}
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2008-09-08 08:41:04 +02:00
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/*
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* Assuming the pin is muxed as a gpio output, set its output value.
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*/
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static void
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davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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2007-07-10 14:03:43 +02:00
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{
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2008-09-08 08:41:04 +02:00
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struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
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struct gpio_controller *__iomem g = d->regs;
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2007-07-10 14:03:43 +02:00
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2008-09-08 08:41:04 +02:00
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__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
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}
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static int __init davinci_gpio_setup(void)
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{
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int i, base;
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2008-12-07 20:46:23 +01:00
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/* The gpio banks conceptually expose a segmented bitmap,
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* and "ngpio" is one more than the largest zero-based
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* bit index that's valid.
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*/
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if (cpu_is_davinci_dm355()) { /* or dm335() */
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ngpio = 104;
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} else if (cpu_is_davinci_dm644x()) { /* or dm337() */
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ngpio = 71;
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} else if (cpu_is_davinci_dm646x()) {
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/* NOTE: each bank has several "reserved" bits,
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* unusable as GPIOs. Only 33 of the GPIO numbers
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* are usable, and we're not rejecting the others.
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*/
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ngpio = 43;
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} else {
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/* if cpu_is_davinci_dm643x() ngpio = 111 */
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pr_err("GPIO setup: how many GPIOs?\n");
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return -EINVAL;
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}
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if (WARN_ON(DAVINCI_N_GPIO < ngpio))
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ngpio = DAVINCI_N_GPIO;
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for (i = 0, base = 0; base < ngpio; i++, base += 32) {
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2008-09-08 08:41:04 +02:00
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chips[i].chip.label = "DaVinci";
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chips[i].chip.direction_input = davinci_direction_in;
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chips[i].chip.get = davinci_gpio_get;
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chips[i].chip.direction_output = davinci_direction_out;
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chips[i].chip.set = davinci_gpio_set;
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chips[i].chip.base = base;
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2008-12-07 20:46:23 +01:00
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chips[i].chip.ngpio = ngpio - base;
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2008-09-08 08:41:04 +02:00
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if (chips[i].chip.ngpio > 32)
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chips[i].chip.ngpio = 32;
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chips[i].regs = gpio2controller(base);
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gpiochip_add(&chips[i].chip);
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}
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2007-07-10 14:03:43 +02:00
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return 0;
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}
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2008-09-08 08:41:04 +02:00
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pure_initcall(davinci_gpio_setup);
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2007-07-10 14:03:43 +02:00
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2008-09-08 08:41:04 +02:00
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/*--------------------------------------------------------------------------*/
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2007-07-10 14:03:43 +02:00
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/*
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* We expect irqs will normally be set up as input pins, but they can also be
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* used as output pins ... which is convenient for testing.
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*
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2008-12-07 20:46:23 +01:00
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* NOTE: The first few GPIOs also have direct INTC hookups in addition
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* to their GPIOBNK0 irq, with a bit less overhead but less flexibility
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* on triggering (e.g. no edge options). We don't try to use those.
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2007-07-10 14:03:43 +02:00
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*
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2008-12-07 20:46:23 +01:00
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* All those INTC hookups (direct, plus several IRQ banks) can also
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2007-07-10 14:03:43 +02:00
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* serve as EDMA event triggers.
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*/
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static void gpio_irq_disable(unsigned irq)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = __gpio_mask(irq_to_gpio(irq));
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__raw_writel(mask, &g->clr_falling);
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__raw_writel(mask, &g->clr_rising);
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}
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static void gpio_irq_enable(unsigned irq)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = __gpio_mask(irq_to_gpio(irq));
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2009-05-04 22:14:27 +02:00
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unsigned status = irq_desc[irq].status;
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2007-07-10 14:03:43 +02:00
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2009-05-04 22:14:27 +02:00
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status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
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if (!status)
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status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
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if (status & IRQ_TYPE_EDGE_FALLING)
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2007-07-10 14:03:43 +02:00
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__raw_writel(mask, &g->set_falling);
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2009-05-04 22:14:27 +02:00
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if (status & IRQ_TYPE_EDGE_RISING)
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2007-07-10 14:03:43 +02:00
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__raw_writel(mask, &g->set_rising);
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}
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static int gpio_irq_type(unsigned irq, unsigned trigger)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = __gpio_mask(irq_to_gpio(irq));
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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return -EINVAL;
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irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
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irq_desc[irq].status |= trigger;
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2009-05-04 22:14:27 +02:00
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/* don't enable the IRQ if it's currently disabled */
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if (irq_desc[irq].depth == 0) {
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__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
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? &g->set_falling : &g->clr_falling);
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__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
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? &g->set_rising : &g->clr_rising);
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}
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2007-07-10 14:03:43 +02:00
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return 0;
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}
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static struct irq_chip gpio_irqchip = {
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.name = "GPIO",
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.enable = gpio_irq_enable,
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.disable = gpio_irq_disable,
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.set_type = gpio_irq_type,
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};
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static void
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gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = 0xffff;
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/* we only care about one bank */
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if (irq & 1)
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mask <<= 16;
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/* temporarily mask (level sensitive) parent IRQ */
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desc->chip->ack(irq);
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while (1) {
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u32 status;
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int n;
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int res;
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/* ack any irqs */
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status = __raw_readl(&g->intstat) & mask;
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if (!status)
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break;
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__raw_writel(status, &g->intstat);
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if (irq & 1)
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status >>= 16;
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/* now demux them to the right lowlevel handler */
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n = (int)get_irq_data(irq);
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while (status) {
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res = ffs(status);
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n += res;
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2008-10-09 14:36:24 +02:00
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generic_handle_irq(n - 1);
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2007-07-10 14:03:43 +02:00
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status >>= res;
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}
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}
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desc->chip->unmask(irq);
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/* now it may re-trigger */
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}
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/*
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2008-12-07 20:46:23 +01:00
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* NOTE: for suspend/resume, probably best to make a platform_device with
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* suspend_late/resume_resume calls hooking into results of the set_wake()
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2007-07-10 14:03:43 +02:00
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* calls ... so if no gpios are wakeup events the clock can be disabled,
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* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
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2008-12-07 20:46:23 +01:00
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* (dm6446) can be set appropriately for GPIOV33 pins.
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2007-07-10 14:03:43 +02:00
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*/
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static int __init davinci_gpio_irq_setup(void)
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{
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unsigned gpio, irq, bank;
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2008-12-07 20:46:23 +01:00
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unsigned bank_irq;
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2007-07-10 14:03:43 +02:00
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struct clk *clk;
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2008-12-07 20:46:23 +01:00
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u32 binten = 0;
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if (cpu_is_davinci_dm355()) { /* or dm335() */
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bank_irq = IRQ_DM355_GPIOBNK0;
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} else if (cpu_is_davinci_dm644x()) {
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bank_irq = IRQ_GPIOBNK0;
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} else if (cpu_is_davinci_dm646x()) {
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bank_irq = IRQ_DM646X_GPIOBNK0;
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} else {
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printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
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return -EINVAL;
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}
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2007-07-10 14:03:43 +02:00
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clk = clk_get(NULL, "gpio");
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if (IS_ERR(clk)) {
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printk(KERN_ERR "Error %ld getting gpio clock?\n",
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PTR_ERR(clk));
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2008-12-07 20:46:23 +01:00
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return PTR_ERR(clk);
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2007-07-10 14:03:43 +02:00
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}
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clk_enable(clk);
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2008-12-07 20:46:23 +01:00
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for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
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gpio < ngpio;
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bank++, bank_irq++) {
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2007-07-10 14:03:43 +02:00
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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unsigned i;
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__raw_writel(~0, &g->clr_falling);
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__raw_writel(~0, &g->clr_rising);
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|
|
|
|
|
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/* set up all irqs in this bank */
|
2008-12-07 20:46:23 +01:00
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|
|
set_irq_chained_handler(bank_irq, gpio_irq_handler);
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|
|
|
set_irq_chip_data(bank_irq, g);
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|
|
set_irq_data(bank_irq, (void *)irq);
|
2007-07-10 14:03:43 +02:00
|
|
|
|
2008-12-07 20:46:23 +01:00
|
|
|
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
|
2007-07-10 14:03:43 +02:00
|
|
|
set_irq_chip(irq, &gpio_irqchip);
|
|
|
|
set_irq_chip_data(irq, g);
|
|
|
|
set_irq_handler(irq, handle_simple_irq);
|
|
|
|
set_irq_flags(irq, IRQF_VALID);
|
|
|
|
}
|
2008-12-07 20:46:23 +01:00
|
|
|
|
|
|
|
binten |= BIT(bank);
|
2007-07-10 14:03:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* BINTEN -- per-bank interrupt enable. genirq would also let these
|
|
|
|
* bits be set/cleared dynamically.
|
|
|
|
*/
|
2008-12-07 20:46:23 +01:00
|
|
|
__raw_writel(binten, (void *__iomem)
|
2007-07-10 14:03:43 +02:00
|
|
|
IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
|
|
|
|
|
|
|
|
printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
arch_initcall(davinci_gpio_irq_setup);
|