2013-10-11 13:27:06 +02:00
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/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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2014-09-07 08:14:29 +02:00
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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2013-10-11 13:27:06 +02:00
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#include "pmc.h"
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#define SMD_SOURCE_MAX 2
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#define SMD_DIV_SHIFT 8
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#define SMD_MAX_DIV 0xf
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struct at91sam9x5_clk_smd {
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struct clk_hw hw;
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2014-09-07 08:14:29 +02:00
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struct regmap *regmap;
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2013-10-11 13:27:06 +02:00
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};
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#define to_at91sam9x5_clk_smd(hw) \
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container_of(hw, struct at91sam9x5_clk_smd, hw)
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static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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2014-09-07 08:14:29 +02:00
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unsigned int smdr;
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u8 smddiv;
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regmap_read(smd->regmap, AT91_PMC_SMD, &smdr);
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smddiv = (smdr & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT;
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2013-10-11 13:27:06 +02:00
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return parent_rate / (smddiv + 1);
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}
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static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long div;
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unsigned long bestrate;
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unsigned long tmp;
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if (rate >= *parent_rate)
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return *parent_rate;
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div = *parent_rate / rate;
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if (div > SMD_MAX_DIV)
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return *parent_rate / (SMD_MAX_DIV + 1);
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bestrate = *parent_rate / div;
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tmp = *parent_rate / (div + 1);
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if (bestrate - rate > rate - tmp)
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bestrate = tmp;
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return bestrate;
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}
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static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
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{
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struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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if (index > 1)
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return -EINVAL;
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2014-09-07 08:14:29 +02:00
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regmap_update_bits(smd->regmap, AT91_PMC_SMD, AT91_PMC_SMDS,
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index ? AT91_PMC_SMDS : 0);
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2013-10-11 13:27:06 +02:00
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return 0;
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}
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static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw)
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{
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struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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2014-09-07 08:14:29 +02:00
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unsigned int smdr;
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2013-10-11 13:27:06 +02:00
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2014-09-07 08:14:29 +02:00
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regmap_read(smd->regmap, AT91_PMC_SMD, &smdr);
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return smdr & AT91_PMC_SMDS;
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2013-10-11 13:27:06 +02:00
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}
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static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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unsigned long div = parent_rate / rate;
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if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1))
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return -EINVAL;
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2014-09-07 08:14:29 +02:00
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regmap_update_bits(smd->regmap, AT91_PMC_SMD, AT91_PMC_SMD_DIV,
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(div - 1) << SMD_DIV_SHIFT);
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2013-10-11 13:27:06 +02:00
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return 0;
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}
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static const struct clk_ops at91sam9x5_smd_ops = {
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.recalc_rate = at91sam9x5_clk_smd_recalc_rate,
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.round_rate = at91sam9x5_clk_smd_round_rate,
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.get_parent = at91sam9x5_clk_smd_get_parent,
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.set_parent = at91sam9x5_clk_smd_set_parent,
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.set_rate = at91sam9x5_clk_smd_set_rate,
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};
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2016-06-01 23:31:22 +02:00
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static struct clk_hw * __init
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2014-09-07 08:14:29 +02:00
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at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
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2013-10-11 13:27:06 +02:00
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const char **parent_names, u8 num_parents)
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{
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struct at91sam9x5_clk_smd *smd;
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2016-06-01 23:31:22 +02:00
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struct clk_hw *hw;
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2013-10-11 13:27:06 +02:00
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struct clk_init_data init;
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2016-06-01 23:31:22 +02:00
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int ret;
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2013-10-11 13:27:06 +02:00
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smd = kzalloc(sizeof(*smd), GFP_KERNEL);
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if (!smd)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &at91sam9x5_smd_ops;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
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smd->hw.init = &init;
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2014-09-07 08:14:29 +02:00
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smd->regmap = regmap;
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2013-10-11 13:27:06 +02:00
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2016-06-01 23:31:22 +02:00
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hw = &smd->hw;
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ret = clk_hw_register(NULL, &smd->hw);
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if (ret) {
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2013-10-11 13:27:06 +02:00
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kfree(smd);
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2016-06-01 23:31:22 +02:00
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hw = ERR_PTR(ret);
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}
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2013-10-11 13:27:06 +02:00
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2016-06-01 23:31:22 +02:00
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return hw;
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2013-10-11 13:27:06 +02:00
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}
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2014-09-07 08:14:29 +02:00
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static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
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2013-10-11 13:27:06 +02:00
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{
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2016-06-01 23:31:22 +02:00
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struct clk_hw *hw;
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2016-02-20 02:29:17 +01:00
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unsigned int num_parents;
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2013-10-11 13:27:06 +02:00
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const char *parent_names[SMD_SOURCE_MAX];
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const char *name = np->name;
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2014-09-07 08:14:29 +02:00
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struct regmap *regmap;
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2013-10-11 13:27:06 +02:00
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2015-05-29 11:25:45 +02:00
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num_parents = of_clk_get_parent_count(np);
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2016-02-20 02:29:17 +01:00
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if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
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2013-10-11 13:27:06 +02:00
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return;
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2015-07-07 05:59:01 +02:00
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of_clk_parent_fill(np, parent_names, num_parents);
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2013-10-11 13:27:06 +02:00
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of_property_read_string(np, "clock-output-names", &name);
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2014-09-07 08:14:29 +02:00
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regmap = syscon_node_to_regmap(of_get_parent(np));
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if (IS_ERR(regmap))
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return;
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2016-06-01 23:31:22 +02:00
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hw = at91sam9x5_clk_register_smd(regmap, name, parent_names,
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2013-10-11 13:27:06 +02:00
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num_parents);
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2016-06-01 23:31:22 +02:00
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if (IS_ERR(hw))
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2013-10-11 13:27:06 +02:00
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return;
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2016-06-01 23:31:22 +02:00
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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2013-10-11 13:27:06 +02:00
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}
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2014-09-07 08:14:29 +02:00
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CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
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of_at91sam9x5_clk_smd_setup);
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