2013-10-11 12:22:06 +02:00
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/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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2014-09-07 08:14:29 +02:00
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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2017-09-06 11:51:59 +02:00
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#include <soc/at91/atmel-sfr.h>
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2013-10-11 12:22:06 +02:00
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#include "pmc.h"
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2017-09-06 11:51:59 +02:00
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/*
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* The purpose of this clock is to generate a 480 MHz signal. A different
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* rate can't be configured.
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*/
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#define UTMI_RATE 480000000
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2013-10-11 12:22:06 +02:00
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struct clk_utmi {
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struct clk_hw hw;
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2017-09-06 11:51:59 +02:00
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struct regmap *regmap_pmc;
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struct regmap *regmap_sfr;
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2013-10-11 12:22:06 +02:00
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};
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#define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
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2014-09-07 08:14:29 +02:00
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static inline bool clk_utmi_ready(struct regmap *regmap)
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{
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unsigned int status;
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regmap_read(regmap, AT91_PMC_SR, &status);
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return status & AT91_PMC_LOCKU;
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}
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2013-10-11 12:22:06 +02:00
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static int clk_utmi_prepare(struct clk_hw *hw)
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{
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2017-09-06 11:51:59 +02:00
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struct clk_hw *hw_parent;
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2013-10-11 12:22:06 +02:00
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struct clk_utmi *utmi = to_clk_utmi(hw);
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2014-09-07 08:14:29 +02:00
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unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT |
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AT91_PMC_BIASEN;
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2017-09-06 11:51:59 +02:00
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unsigned int utmi_ref_clk_freq;
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unsigned long parent_rate;
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/*
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* If mainck rate is different from 12 MHz, we have to configure the
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* FREQ field of the SFR_UTMICKTRIM register to generate properly
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* the utmi clock.
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*/
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hw_parent = clk_hw_get_parent(hw);
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parent_rate = clk_hw_get_rate(hw_parent);
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switch (parent_rate) {
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case 12000000:
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utmi_ref_clk_freq = 0;
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break;
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case 16000000:
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utmi_ref_clk_freq = 1;
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break;
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case 24000000:
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utmi_ref_clk_freq = 2;
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break;
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/*
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* Not supported on SAMA5D2 but it's not an issue since MAINCK
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* maximum value is 24 MHz.
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*/
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case 48000000:
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utmi_ref_clk_freq = 3;
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break;
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default:
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pr_err("UTMICK: unsupported mainck rate\n");
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return -EINVAL;
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}
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2013-10-11 12:22:06 +02:00
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2017-09-06 11:51:59 +02:00
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if (utmi->regmap_sfr) {
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regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM,
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AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq);
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} else if (utmi_ref_clk_freq) {
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pr_err("UTMICK: sfr node required\n");
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return -EINVAL;
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}
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2013-10-11 12:22:06 +02:00
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2017-09-06 11:51:59 +02:00
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regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr);
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while (!clk_utmi_ready(utmi->regmap_pmc))
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2015-09-16 23:47:39 +02:00
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cpu_relax();
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2013-10-11 12:22:06 +02:00
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return 0;
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}
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static int clk_utmi_is_prepared(struct clk_hw *hw)
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{
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struct clk_utmi *utmi = to_clk_utmi(hw);
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2017-09-06 11:51:59 +02:00
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return clk_utmi_ready(utmi->regmap_pmc);
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2013-10-11 12:22:06 +02:00
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}
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static void clk_utmi_unprepare(struct clk_hw *hw)
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{
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struct clk_utmi *utmi = to_clk_utmi(hw);
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2017-09-06 11:51:59 +02:00
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regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR,
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AT91_PMC_UPLLEN, 0);
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2013-10-11 12:22:06 +02:00
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}
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static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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2017-09-06 11:51:59 +02:00
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/* UTMI clk rate is fixed. */
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return UTMI_RATE;
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2013-10-11 12:22:06 +02:00
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}
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static const struct clk_ops utmi_ops = {
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.prepare = clk_utmi_prepare,
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.unprepare = clk_utmi_unprepare,
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.is_prepared = clk_utmi_is_prepared,
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.recalc_rate = clk_utmi_recalc_rate,
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};
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2016-06-01 23:31:22 +02:00
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static struct clk_hw * __init
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2017-09-06 11:51:59 +02:00
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at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
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2013-10-11 12:22:06 +02:00
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const char *name, const char *parent_name)
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{
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struct clk_utmi *utmi;
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2016-06-01 23:31:22 +02:00
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struct clk_hw *hw;
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2013-10-11 12:22:06 +02:00
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struct clk_init_data init;
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2016-06-01 23:31:22 +02:00
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int ret;
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2013-10-11 12:22:06 +02:00
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utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
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if (!utmi)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &utmi_ops;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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init.flags = CLK_SET_RATE_GATE;
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utmi->hw.init = &init;
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2017-09-06 11:51:59 +02:00
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utmi->regmap_pmc = regmap_pmc;
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utmi->regmap_sfr = regmap_sfr;
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2013-10-11 12:22:06 +02:00
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2016-06-01 23:31:22 +02:00
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hw = &utmi->hw;
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ret = clk_hw_register(NULL, &utmi->hw);
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if (ret) {
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2013-10-11 12:22:06 +02:00
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kfree(utmi);
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2016-06-01 23:31:22 +02:00
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hw = ERR_PTR(ret);
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}
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2013-10-11 12:22:06 +02:00
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2016-06-01 23:31:22 +02:00
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return hw;
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2013-10-11 12:22:06 +02:00
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}
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2014-09-07 08:14:29 +02:00
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static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
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2013-10-11 12:22:06 +02:00
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{
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2016-06-01 23:31:22 +02:00
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struct clk_hw *hw;
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2013-10-11 12:22:06 +02:00
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const char *parent_name;
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const char *name = np->name;
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2017-09-06 11:51:59 +02:00
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struct regmap *regmap_pmc, *regmap_sfr;
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2013-10-11 12:22:06 +02:00
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parent_name = of_clk_get_parent_name(np, 0);
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of_property_read_string(np, "clock-output-names", &name);
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2017-09-06 11:51:59 +02:00
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regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
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if (IS_ERR(regmap_pmc))
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2014-09-07 08:14:29 +02:00
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return;
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2017-09-06 11:51:59 +02:00
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/*
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* If the device supports different mainck rates, this value has to be
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* set in the UTMI Clock Trimming register.
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* - 9x5: mainck supports several rates but it is indicated that a
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* 12 MHz is needed in case of USB.
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* - sama5d3 and sama5d2: mainck supports several rates. Configuring
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* the FREQ field of the UTMI Clock Trimming register is mandatory.
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* - sama5d4: mainck is at 12 MHz.
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*
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* We only need to retrieve sama5d3 or sama5d2 sfr regmap.
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*/
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regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
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if (IS_ERR(regmap_sfr)) {
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regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
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if (IS_ERR(regmap_sfr))
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regmap_sfr = NULL;
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}
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hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
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2016-06-01 23:31:22 +02:00
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if (IS_ERR(hw))
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2013-10-11 12:22:06 +02:00
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return;
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2016-06-01 23:31:22 +02:00
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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2013-10-11 12:22:06 +02:00
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return;
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}
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2014-09-07 08:14:29 +02:00
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CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
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of_at91sam9x5_clk_utmi_setup);
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