2014-07-03 01:58:39 +02:00
|
|
|
/*
|
|
|
|
* Copyright (c) 2014 MundoReader S.L.
|
|
|
|
* Author: Heiko Stuebner <heiko@sntech.de>
|
|
|
|
*
|
2015-11-05 08:33:57 +01:00
|
|
|
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
|
|
|
|
* Author: Xing Zheng <zhengxing@rock-chips.com>
|
|
|
|
*
|
2014-07-03 01:58:39 +02:00
|
|
|
* based on
|
|
|
|
*
|
|
|
|
* samsung/clk.h
|
|
|
|
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
|
|
|
* Copyright (c) 2013 Linaro Ltd.
|
|
|
|
* Author: Thomas Abraham <thomas.ab@samsung.com>
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef CLK_ROCKCHIP_CLK_H
|
|
|
|
#define CLK_ROCKCHIP_CLK_H
|
|
|
|
|
|
|
|
#include <linux/io.h>
|
2016-03-09 03:37:04 +01:00
|
|
|
#include <linux/clk-provider.h>
|
2015-06-20 00:00:46 +02:00
|
|
|
|
|
|
|
struct clk;
|
2014-07-03 01:58:39 +02:00
|
|
|
|
|
|
|
#define HIWORD_UPDATE(val, mask, shift) \
|
|
|
|
((val) << (shift) | (mask) << ((shift) + 16))
|
|
|
|
|
2017-03-17 18:18:38 +01:00
|
|
|
/* register positions shared by RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
|
|
|
|
#define RV1108_PLL_CON(x) ((x) * 0x4)
|
|
|
|
#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
|
|
|
|
#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
|
|
|
|
#define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
|
|
|
|
#define RV1108_GLB_SRST_FST 0x1c0
|
|
|
|
#define RV1108_GLB_SRST_SND 0x1c4
|
|
|
|
#define RV1108_MISC_CON 0x1cc
|
|
|
|
#define RV1108_SDMMC_CON0 0x1d8
|
|
|
|
#define RV1108_SDMMC_CON1 0x1dc
|
|
|
|
#define RV1108_SDIO_CON0 0x1e0
|
|
|
|
#define RV1108_SDIO_CON1 0x1e4
|
|
|
|
#define RV1108_EMMC_CON0 0x1e8
|
|
|
|
#define RV1108_EMMC_CON1 0x1ec
|
2016-11-16 09:49:23 +01:00
|
|
|
|
2015-06-18 16:18:30 +02:00
|
|
|
#define RK2928_PLL_CON(x) ((x) * 0x4)
|
2014-07-03 01:58:39 +02:00
|
|
|
#define RK2928_MODE_CON 0x40
|
2015-06-18 16:18:30 +02:00
|
|
|
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
|
|
|
|
#define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
|
2014-07-03 01:58:39 +02:00
|
|
|
#define RK2928_GLB_SRST_FST 0x100
|
|
|
|
#define RK2928_GLB_SRST_SND 0x104
|
2015-06-18 16:18:30 +02:00
|
|
|
#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
|
2014-07-03 01:58:39 +02:00
|
|
|
#define RK2928_MISC_CON 0x134
|
|
|
|
|
2015-11-05 08:33:58 +01:00
|
|
|
#define RK3036_SDMMC_CON0 0x144
|
|
|
|
#define RK3036_SDMMC_CON1 0x148
|
|
|
|
#define RK3036_SDIO_CON0 0x14c
|
|
|
|
#define RK3036_SDIO_CON1 0x150
|
|
|
|
#define RK3036_EMMC_CON0 0x154
|
|
|
|
#define RK3036_EMMC_CON1 0x158
|
|
|
|
|
2015-12-11 02:30:50 +01:00
|
|
|
#define RK3228_GLB_SRST_FST 0x1f0
|
|
|
|
#define RK3228_GLB_SRST_SND 0x1f4
|
|
|
|
#define RK3228_SDMMC_CON0 0x1c0
|
|
|
|
#define RK3228_SDMMC_CON1 0x1c4
|
|
|
|
#define RK3228_SDIO_CON0 0x1c8
|
|
|
|
#define RK3228_SDIO_CON1 0x1cc
|
|
|
|
#define RK3228_EMMC_CON0 0x1d8
|
|
|
|
#define RK3228_EMMC_CON1 0x1dc
|
|
|
|
|
2014-07-03 02:02:37 +02:00
|
|
|
#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
|
|
|
|
#define RK3288_MODE_CON 0x50
|
2015-06-18 16:18:30 +02:00
|
|
|
#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
|
|
|
|
#define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
|
2014-07-03 02:02:37 +02:00
|
|
|
#define RK3288_GLB_SRST_FST 0x1b0
|
|
|
|
#define RK3288_GLB_SRST_SND 0x1b4
|
2015-06-18 16:18:30 +02:00
|
|
|
#define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
|
2014-07-03 02:02:37 +02:00
|
|
|
#define RK3288_MISC_CON 0x1e8
|
2014-11-27 02:30:27 +01:00
|
|
|
#define RK3288_SDMMC_CON0 0x200
|
|
|
|
#define RK3288_SDMMC_CON1 0x204
|
|
|
|
#define RK3288_SDIO0_CON0 0x208
|
|
|
|
#define RK3288_SDIO0_CON1 0x20c
|
|
|
|
#define RK3288_SDIO1_CON0 0x210
|
|
|
|
#define RK3288_SDIO1_CON1 0x214
|
|
|
|
#define RK3288_EMMC_CON0 0x218
|
|
|
|
#define RK3288_EMMC_CON1 0x21c
|
2014-07-03 02:02:37 +02:00
|
|
|
|
2016-12-29 03:45:11 +01:00
|
|
|
#define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
|
|
|
|
#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
|
|
|
#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
|
|
|
|
#define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
|
|
|
#define RK3328_GLB_SRST_FST 0x9c
|
|
|
|
#define RK3328_GLB_SRST_SND 0x98
|
|
|
|
#define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
|
|
|
|
#define RK3328_MODE_CON 0x80
|
|
|
|
#define RK3328_MISC_CON 0x84
|
|
|
|
#define RK3328_SDMMC_CON0 0x380
|
|
|
|
#define RK3328_SDMMC_CON1 0x384
|
|
|
|
#define RK3328_SDIO_CON0 0x388
|
|
|
|
#define RK3328_SDIO_CON1 0x38c
|
|
|
|
#define RK3328_EMMC_CON0 0x390
|
|
|
|
#define RK3328_EMMC_CON1 0x394
|
|
|
|
#define RK3328_SDMMC_EXT_CON0 0x398
|
|
|
|
#define RK3328_SDMMC_EXT_CON1 0x39C
|
|
|
|
|
2015-07-05 11:00:20 +02:00
|
|
|
#define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
|
|
|
|
#define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
|
|
|
#define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
|
|
|
|
#define RK3368_GLB_SRST_FST 0x280
|
|
|
|
#define RK3368_GLB_SRST_SND 0x284
|
|
|
|
#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
|
|
|
|
#define RK3368_MISC_CON 0x380
|
|
|
|
#define RK3368_SDMMC_CON0 0x400
|
|
|
|
#define RK3368_SDMMC_CON1 0x404
|
|
|
|
#define RK3368_SDIO0_CON0 0x408
|
|
|
|
#define RK3368_SDIO0_CON1 0x40c
|
|
|
|
#define RK3368_SDIO1_CON0 0x410
|
|
|
|
#define RK3368_SDIO1_CON1 0x414
|
|
|
|
#define RK3368_EMMC_CON0 0x418
|
|
|
|
#define RK3368_EMMC_CON1 0x41c
|
|
|
|
|
2016-03-28 11:51:37 +02:00
|
|
|
#define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
|
|
|
|
#define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
|
|
|
#define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
|
|
|
|
#define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
|
|
|
|
#define RK3399_GLB_SRST_FST 0x500
|
|
|
|
#define RK3399_GLB_SRST_SND 0x504
|
|
|
|
#define RK3399_GLB_CNT_TH 0x508
|
|
|
|
#define RK3399_MISC_CON 0x50c
|
|
|
|
#define RK3399_RST_CON 0x510
|
|
|
|
#define RK3399_RST_ST 0x514
|
|
|
|
#define RK3399_SDMMC_CON0 0x580
|
|
|
|
#define RK3399_SDMMC_CON1 0x584
|
|
|
|
#define RK3399_SDIO_CON0 0x588
|
|
|
|
#define RK3399_SDIO_CON1 0x58c
|
|
|
|
|
|
|
|
#define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
|
|
|
|
#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
|
|
|
|
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
|
|
|
|
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
|
|
|
|
|
2014-07-03 01:59:10 +02:00
|
|
|
enum rockchip_pll_type {
|
2015-11-05 08:33:57 +01:00
|
|
|
pll_rk3036,
|
2014-07-03 01:59:10 +02:00
|
|
|
pll_rk3066,
|
2016-12-29 03:45:10 +01:00
|
|
|
pll_rk3328,
|
2016-03-10 04:47:01 +01:00
|
|
|
pll_rk3399,
|
2014-07-03 01:59:10 +02:00
|
|
|
};
|
|
|
|
|
2015-11-05 08:33:57 +01:00
|
|
|
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
|
|
|
|
_postdiv2, _dsmpd, _frac) \
|
|
|
|
{ \
|
|
|
|
.rate = _rate##U, \
|
|
|
|
.fbdiv = _fbdiv, \
|
|
|
|
.postdiv1 = _postdiv1, \
|
|
|
|
.refdiv = _refdiv, \
|
|
|
|
.postdiv2 = _postdiv2, \
|
|
|
|
.dsmpd = _dsmpd, \
|
|
|
|
.frac = _frac, \
|
|
|
|
}
|
|
|
|
|
2014-07-03 01:59:10 +02:00
|
|
|
#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
|
|
|
|
{ \
|
|
|
|
.rate = _rate##U, \
|
|
|
|
.nr = _nr, \
|
|
|
|
.nf = _nf, \
|
|
|
|
.no = _no, \
|
clk: rockchip: Fix PLL bandwidth
In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.
So:
NB = NF / 2
BWADJ[11:0] + 1 = NF / 2
BWADJ[11:0] = NF / 2 - 1
Right now, we have:
{ \
.rate = _rate##U, \
.nr = _nr, \
.nf = _nf, \
.no = _no, \
.bwadj = (_nf >> 1), \
}
That means we set bwadj to NF / 2, not NF / 2 - 1
All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).
Let's change to working with "NB" and fix the off by one error. This
may affect PLL jitter in a small way (hopefully for the better).
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-21 22:41:23 +02:00
|
|
|
.nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
|
2014-07-03 01:59:10 +02:00
|
|
|
}
|
|
|
|
|
clk: rockchip: Fix PLL bandwidth
In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.
So:
NB = NF / 2
BWADJ[11:0] + 1 = NF / 2
BWADJ[11:0] = NF / 2 - 1
Right now, we have:
{ \
.rate = _rate##U, \
.nr = _nr, \
.nf = _nf, \
.no = _no, \
.bwadj = (_nf >> 1), \
}
That means we set bwadj to NF / 2, not NF / 2 - 1
All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).
Let's change to working with "NB" and fix the off by one error. This
may affect PLL jitter in a small way (hopefully for the better).
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-21 22:41:23 +02:00
|
|
|
#define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
|
clk: rockchip: change PLL setting for better clock jitter
dclk_vop0/1 is the source of HDMI TMDS clock in rk3288, usually we
use 594MHz for clock source of dclk_vop0/1.
HDMI CTS 7-9 require TMDS Clock jitter is lower than 0.25*Tbit:
TMDS clock(MHz) CTS require jitter (ps)
297 84.2
148.5 168
74.25 336
27 1247
PLL BW and VCO frequency effects the jitter of PLL output clock,
clock jitter is better if BW is lower or VCO frequency is higher.
If PLL use default setting of RK3066_PLL_RATE( 594000000, 2, 198, 4),
the TMDS Clock jitter is higher than 250ps, which means we can't
pass the test when TMDS clock is 297MHz or 148.5MHz.
If we use RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
the TMDS Clock jitter is about 60ps and we can pass all test case.
So we need this patch to make hdmi si test pass.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-10 07:23:57 +02:00
|
|
|
{ \
|
|
|
|
.rate = _rate##U, \
|
|
|
|
.nr = _nr, \
|
|
|
|
.nf = _nf, \
|
|
|
|
.no = _no, \
|
clk: rockchip: Fix PLL bandwidth
In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.
So:
NB = NF / 2
BWADJ[11:0] + 1 = NF / 2
BWADJ[11:0] = NF / 2 - 1
Right now, we have:
{ \
.rate = _rate##U, \
.nr = _nr, \
.nf = _nf, \
.no = _no, \
.bwadj = (_nf >> 1), \
}
That means we set bwadj to NF / 2, not NF / 2 - 1
All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).
Let's change to working with "NB" and fix the off by one error. This
may affect PLL jitter in a small way (hopefully for the better).
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-21 22:41:23 +02:00
|
|
|
.nb = _nb, \
|
clk: rockchip: change PLL setting for better clock jitter
dclk_vop0/1 is the source of HDMI TMDS clock in rk3288, usually we
use 594MHz for clock source of dclk_vop0/1.
HDMI CTS 7-9 require TMDS Clock jitter is lower than 0.25*Tbit:
TMDS clock(MHz) CTS require jitter (ps)
297 84.2
148.5 168
74.25 336
27 1247
PLL BW and VCO frequency effects the jitter of PLL output clock,
clock jitter is better if BW is lower or VCO frequency is higher.
If PLL use default setting of RK3066_PLL_RATE( 594000000, 2, 198, 4),
the TMDS Clock jitter is higher than 250ps, which means we can't
pass the test when TMDS clock is 297MHz or 148.5MHz.
If we use RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
the TMDS Clock jitter is about 60ps and we can pass all test case.
So we need this patch to make hdmi si test pass.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-10 07:23:57 +02:00
|
|
|
}
|
|
|
|
|
2016-03-09 03:37:04 +01:00
|
|
|
/**
|
2016-03-12 17:25:14 +01:00
|
|
|
* struct rockchip_clk_provider - information about clock provider
|
2016-03-09 03:37:04 +01:00
|
|
|
* @reg_base: virtual address for the register base.
|
|
|
|
* @clk_data: holds clock related data like clk* and number of clocks.
|
|
|
|
* @cru_node: device-node of the clock-provider
|
|
|
|
* @grf: regmap of the general-register-files syscon
|
|
|
|
* @lock: maintains exclusion between callbacks for a given clock-provider.
|
|
|
|
*/
|
|
|
|
struct rockchip_clk_provider {
|
|
|
|
void __iomem *reg_base;
|
|
|
|
struct clk_onecell_data clk_data;
|
|
|
|
struct device_node *cru_node;
|
|
|
|
struct regmap *grf;
|
|
|
|
spinlock_t lock;
|
|
|
|
};
|
|
|
|
|
2014-07-03 01:59:10 +02:00
|
|
|
struct rockchip_pll_rate_table {
|
|
|
|
unsigned long rate;
|
|
|
|
unsigned int nr;
|
|
|
|
unsigned int nf;
|
|
|
|
unsigned int no;
|
clk: rockchip: Fix PLL bandwidth
In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.
So:
NB = NF / 2
BWADJ[11:0] + 1 = NF / 2
BWADJ[11:0] = NF / 2 - 1
Right now, we have:
{ \
.rate = _rate##U, \
.nr = _nr, \
.nf = _nf, \
.no = _no, \
.bwadj = (_nf >> 1), \
}
That means we set bwadj to NF / 2, not NF / 2 - 1
All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).
Let's change to working with "NB" and fix the off by one error. This
may affect PLL jitter in a small way (hopefully for the better).
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-21 22:41:23 +02:00
|
|
|
unsigned int nb;
|
2016-03-10 04:47:01 +01:00
|
|
|
/* for RK3036/RK3399 */
|
2015-11-05 08:33:57 +01:00
|
|
|
unsigned int fbdiv;
|
|
|
|
unsigned int postdiv1;
|
|
|
|
unsigned int refdiv;
|
|
|
|
unsigned int postdiv2;
|
|
|
|
unsigned int dsmpd;
|
|
|
|
unsigned int frac;
|
2014-07-03 01:59:10 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
2016-03-12 17:25:14 +01:00
|
|
|
* struct rockchip_pll_clock - information about pll clock
|
2014-07-03 01:59:10 +02:00
|
|
|
* @id: platform specific id of the clock.
|
|
|
|
* @name: name of this pll clock.
|
2016-03-12 17:25:14 +01:00
|
|
|
* @parent_names: name of the parent clock.
|
|
|
|
* @num_parents: number of parents
|
2014-07-03 01:59:10 +02:00
|
|
|
* @flags: optional flags for basic clock.
|
|
|
|
* @con_offset: offset of the register for configuring the PLL.
|
|
|
|
* @mode_offset: offset of the register for configuring the PLL-mode.
|
|
|
|
* @mode_shift: offset inside the mode-register for the mode of this pll.
|
|
|
|
* @lock_shift: offset inside the lock register for the lock status.
|
|
|
|
* @type: Type of PLL to be registered.
|
2014-11-20 20:38:50 +01:00
|
|
|
* @pll_flags: hardware-specific flags
|
2014-07-03 01:59:10 +02:00
|
|
|
* @rate_table: Table of usable pll rates
|
2014-11-20 20:38:52 +01:00
|
|
|
*
|
|
|
|
* Flags:
|
|
|
|
* ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
|
|
|
|
* rate_table parameters and ajust them if necessary.
|
2014-07-03 01:59:10 +02:00
|
|
|
*/
|
|
|
|
struct rockchip_pll_clock {
|
|
|
|
unsigned int id;
|
|
|
|
const char *name;
|
2015-05-28 10:45:51 +02:00
|
|
|
const char *const *parent_names;
|
2014-07-03 01:59:10 +02:00
|
|
|
u8 num_parents;
|
|
|
|
unsigned long flags;
|
|
|
|
int con_offset;
|
|
|
|
int mode_offset;
|
|
|
|
int mode_shift;
|
|
|
|
int lock_shift;
|
|
|
|
enum rockchip_pll_type type;
|
2014-11-20 20:38:50 +01:00
|
|
|
u8 pll_flags;
|
2014-07-03 01:59:10 +02:00
|
|
|
struct rockchip_pll_rate_table *rate_table;
|
|
|
|
};
|
|
|
|
|
2014-11-20 20:38:52 +01:00
|
|
|
#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
|
|
|
|
|
2014-07-03 01:59:10 +02:00
|
|
|
#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
|
2014-11-20 20:38:50 +01:00
|
|
|
_lshift, _pflags, _rtable) \
|
2014-07-03 01:59:10 +02:00
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.type = _type, \
|
|
|
|
.name = _name, \
|
|
|
|
.parent_names = _pnames, \
|
|
|
|
.num_parents = ARRAY_SIZE(_pnames), \
|
|
|
|
.flags = CLK_GET_RATE_NOCACHE | _flags, \
|
|
|
|
.con_offset = _con, \
|
|
|
|
.mode_offset = _mode, \
|
|
|
|
.mode_shift = _mshift, \
|
|
|
|
.lock_shift = _lshift, \
|
2014-11-20 20:38:50 +01:00
|
|
|
.pll_flags = _pflags, \
|
2014-07-03 01:59:10 +02:00
|
|
|
.rate_table = _rtable, \
|
|
|
|
}
|
|
|
|
|
2016-03-09 03:37:04 +01:00
|
|
|
struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
|
|
|
|
enum rockchip_pll_type pll_type,
|
2015-05-28 10:45:51 +02:00
|
|
|
const char *name, const char *const *parent_names,
|
2016-03-09 03:37:04 +01:00
|
|
|
u8 num_parents, int con_offset, int grf_lock_offset,
|
|
|
|
int lock_shift, int mode_offset, int mode_shift,
|
|
|
|
struct rockchip_pll_rate_table *rate_table,
|
2016-07-29 09:56:55 +02:00
|
|
|
unsigned long flags, u8 clk_pll_flags);
|
2014-07-03 01:59:10 +02:00
|
|
|
|
2014-09-04 22:10:43 +02:00
|
|
|
struct rockchip_cpuclk_clksel {
|
|
|
|
int reg;
|
|
|
|
u32 val;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
|
|
|
|
struct rockchip_cpuclk_rate_table {
|
|
|
|
unsigned long prate;
|
|
|
|
struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
2016-04-19 21:29:27 +02:00
|
|
|
* struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock
|
2014-09-04 22:10:43 +02:00
|
|
|
* @core_reg: register offset of the core settings register
|
|
|
|
* @div_core_shift: core divider offset used to divide the pll value
|
|
|
|
* @div_core_mask: core divider mask
|
2016-03-09 03:37:03 +01:00
|
|
|
* @mux_core_alt: mux value to select alternate parent
|
|
|
|
* @mux_core_main: mux value to select main parent of core
|
2014-09-04 22:10:43 +02:00
|
|
|
* @mux_core_shift: offset of the core multiplexer
|
2016-03-09 03:37:03 +01:00
|
|
|
* @mux_core_mask: core multiplexer mask
|
2014-09-04 22:10:43 +02:00
|
|
|
*/
|
|
|
|
struct rockchip_cpuclk_reg_data {
|
|
|
|
int core_reg;
|
|
|
|
u8 div_core_shift;
|
|
|
|
u32 div_core_mask;
|
2016-03-09 03:37:03 +01:00
|
|
|
u8 mux_core_alt;
|
|
|
|
u8 mux_core_main;
|
2014-09-04 22:10:43 +02:00
|
|
|
u8 mux_core_shift;
|
2016-03-09 03:37:03 +01:00
|
|
|
u32 mux_core_mask;
|
2014-09-04 22:10:43 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
struct clk *rockchip_clk_register_cpuclk(const char *name,
|
2015-05-28 10:45:51 +02:00
|
|
|
const char *const *parent_names, u8 num_parents,
|
2014-09-04 22:10:43 +02:00
|
|
|
const struct rockchip_cpuclk_reg_data *reg_data,
|
|
|
|
const struct rockchip_cpuclk_rate_table *rates,
|
|
|
|
int nrates, void __iomem *reg_base, spinlock_t *lock);
|
|
|
|
|
2014-11-27 02:30:27 +01:00
|
|
|
struct clk *rockchip_clk_register_mmc(const char *name,
|
2015-05-28 10:45:51 +02:00
|
|
|
const char *const *parent_names, u8 num_parents,
|
2014-11-27 02:30:27 +01:00
|
|
|
void __iomem *reg, int shift);
|
|
|
|
|
2016-08-22 05:36:17 +02:00
|
|
|
/*
|
|
|
|
* DDRCLK flags, including method of setting the rate
|
|
|
|
* ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
|
|
|
|
*/
|
|
|
|
#define ROCKCHIP_DDRCLK_SIP BIT(0)
|
|
|
|
|
|
|
|
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
|
|
|
const char *const *parent_names,
|
|
|
|
u8 num_parents, int mux_offset,
|
|
|
|
int mux_shift, int mux_width,
|
|
|
|
int div_shift, int div_width,
|
|
|
|
int ddr_flags, void __iomem *reg_base,
|
|
|
|
spinlock_t *lock);
|
|
|
|
|
2015-07-05 11:00:14 +02:00
|
|
|
#define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
|
|
|
|
|
|
|
|
struct clk *rockchip_clk_register_inverter(const char *name,
|
|
|
|
const char *const *parent_names, u8 num_parents,
|
|
|
|
void __iomem *reg, int shift, int flags,
|
|
|
|
spinlock_t *lock);
|
|
|
|
|
2016-12-27 00:00:38 +01:00
|
|
|
struct clk *rockchip_clk_register_muxgrf(const char *name,
|
|
|
|
const char *const *parent_names, u8 num_parents,
|
|
|
|
int flags, struct regmap *grf, int reg,
|
|
|
|
int shift, int width, int mux_flags);
|
|
|
|
|
2015-05-28 10:45:51 +02:00
|
|
|
#define PNAME(x) static const char *const x[] __initconst
|
2014-07-03 01:58:39 +02:00
|
|
|
|
|
|
|
enum rockchip_clk_branch_type {
|
|
|
|
branch_composite,
|
|
|
|
branch_mux,
|
2016-12-27 00:00:38 +01:00
|
|
|
branch_muxgrf,
|
2014-07-03 01:58:39 +02:00
|
|
|
branch_divider,
|
|
|
|
branch_fraction_divider,
|
|
|
|
branch_gate,
|
2014-11-27 02:30:27 +01:00
|
|
|
branch_mmc,
|
2015-07-05 11:00:14 +02:00
|
|
|
branch_inverter,
|
2015-06-20 13:08:57 +02:00
|
|
|
branch_factor,
|
2016-08-22 05:36:17 +02:00
|
|
|
branch_ddrclk,
|
2014-07-03 01:58:39 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
struct rockchip_clk_branch {
|
|
|
|
unsigned int id;
|
|
|
|
enum rockchip_clk_branch_type branch_type;
|
|
|
|
const char *name;
|
2015-05-28 10:45:51 +02:00
|
|
|
const char *const *parent_names;
|
2014-07-03 01:58:39 +02:00
|
|
|
u8 num_parents;
|
|
|
|
unsigned long flags;
|
|
|
|
int muxdiv_offset;
|
|
|
|
u8 mux_shift;
|
|
|
|
u8 mux_width;
|
|
|
|
u8 mux_flags;
|
|
|
|
u8 div_shift;
|
|
|
|
u8 div_width;
|
|
|
|
u8 div_flags;
|
|
|
|
struct clk_div_table *div_table;
|
|
|
|
int gate_offset;
|
|
|
|
u8 gate_shift;
|
|
|
|
u8 gate_flags;
|
2015-12-22 22:27:59 +01:00
|
|
|
struct rockchip_clk_branch *child;
|
2014-07-03 01:58:39 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
#define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
|
|
|
|
df, go, gs, gf) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_composite, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = pnames, \
|
|
|
|
.num_parents = ARRAY_SIZE(pnames), \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = mo, \
|
|
|
|
.mux_shift = ms, \
|
|
|
|
.mux_width = mw, \
|
|
|
|
.mux_flags = mf, \
|
|
|
|
.div_shift = ds, \
|
|
|
|
.div_width = dw, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.gate_offset = go, \
|
|
|
|
.gate_shift = gs, \
|
|
|
|
.gate_flags = gf, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
|
|
|
|
go, gs, gf) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_composite, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = mo, \
|
|
|
|
.div_shift = ds, \
|
|
|
|
.div_width = dw, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.gate_offset = go, \
|
|
|
|
.gate_shift = gs, \
|
|
|
|
.gate_flags = gf, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
|
|
|
|
df, dt, go, gs, gf) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_composite, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = mo, \
|
|
|
|
.div_shift = ds, \
|
|
|
|
.div_width = dw, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.div_table = dt, \
|
|
|
|
.gate_offset = go, \
|
|
|
|
.gate_shift = gs, \
|
|
|
|
.gate_flags = gf, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
|
|
|
|
go, gs, gf) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_composite, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = pnames, \
|
|
|
|
.num_parents = ARRAY_SIZE(pnames), \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = mo, \
|
|
|
|
.mux_shift = ms, \
|
|
|
|
.mux_width = mw, \
|
|
|
|
.mux_flags = mf, \
|
|
|
|
.gate_offset = go, \
|
|
|
|
.gate_shift = gs, \
|
|
|
|
.gate_flags = gf, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
|
|
|
|
ds, dw, df) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_composite, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = pnames, \
|
|
|
|
.num_parents = ARRAY_SIZE(pnames), \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = mo, \
|
|
|
|
.mux_shift = ms, \
|
|
|
|
.mux_width = mw, \
|
|
|
|
.mux_flags = mf, \
|
|
|
|
.div_shift = ds, \
|
|
|
|
.div_width = dw, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.gate_offset = -1, \
|
|
|
|
}
|
|
|
|
|
2015-06-18 16:18:31 +02:00
|
|
|
#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
|
|
|
|
mw, mf, ds, dw, df, dt) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_composite, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = pnames, \
|
|
|
|
.num_parents = ARRAY_SIZE(pnames), \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = mo, \
|
|
|
|
.mux_shift = ms, \
|
|
|
|
.mux_width = mw, \
|
|
|
|
.mux_flags = mf, \
|
|
|
|
.div_shift = ds, \
|
|
|
|
.div_width = dw, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.div_table = dt, \
|
|
|
|
.gate_offset = -1, \
|
|
|
|
}
|
|
|
|
|
2014-07-03 01:58:39 +02:00
|
|
|
#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_fraction_divider, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = mo, \
|
|
|
|
.div_shift = 16, \
|
|
|
|
.div_width = 16, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.gate_offset = go, \
|
|
|
|
.gate_shift = gs, \
|
|
|
|
.gate_flags = gf, \
|
|
|
|
}
|
|
|
|
|
2015-12-22 22:27:59 +01:00
|
|
|
#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_fraction_divider, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = mo, \
|
|
|
|
.div_shift = 16, \
|
|
|
|
.div_width = 16, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.gate_offset = go, \
|
|
|
|
.gate_shift = gs, \
|
|
|
|
.gate_flags = gf, \
|
2015-12-26 14:07:15 +01:00
|
|
|
.child = ch, \
|
2015-12-22 22:27:59 +01:00
|
|
|
}
|
|
|
|
|
2016-03-09 03:43:31 +01:00
|
|
|
#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_fraction_divider, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = mo, \
|
|
|
|
.div_shift = 16, \
|
|
|
|
.div_width = 16, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.gate_offset = -1, \
|
|
|
|
.child = ch, \
|
|
|
|
}
|
|
|
|
|
2016-08-22 05:36:17 +02:00
|
|
|
#define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
|
|
|
|
ds, dw, df) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_ddrclk, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = pnames, \
|
|
|
|
.num_parents = ARRAY_SIZE(pnames), \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = mo, \
|
|
|
|
.mux_shift = ms, \
|
|
|
|
.mux_width = mw, \
|
|
|
|
.div_shift = ds, \
|
|
|
|
.div_width = dw, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.gate_offset = -1, \
|
|
|
|
}
|
|
|
|
|
2014-07-03 01:58:39 +02:00
|
|
|
#define MUX(_id, cname, pnames, f, o, s, w, mf) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_mux, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = pnames, \
|
|
|
|
.num_parents = ARRAY_SIZE(pnames), \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = o, \
|
|
|
|
.mux_shift = s, \
|
|
|
|
.mux_width = w, \
|
|
|
|
.mux_flags = mf, \
|
|
|
|
.gate_offset = -1, \
|
|
|
|
}
|
|
|
|
|
2016-12-27 00:00:38 +01:00
|
|
|
#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_muxgrf, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = pnames, \
|
|
|
|
.num_parents = ARRAY_SIZE(pnames), \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = o, \
|
|
|
|
.mux_shift = s, \
|
|
|
|
.mux_width = w, \
|
|
|
|
.mux_flags = mf, \
|
|
|
|
.gate_offset = -1, \
|
|
|
|
}
|
|
|
|
|
2014-07-03 01:58:39 +02:00
|
|
|
#define DIV(_id, cname, pname, f, o, s, w, df) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_divider, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = o, \
|
|
|
|
.div_shift = s, \
|
|
|
|
.div_width = w, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.gate_offset = -1, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_divider, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.flags = f, \
|
|
|
|
.muxdiv_offset = o, \
|
|
|
|
.div_shift = s, \
|
|
|
|
.div_width = w, \
|
|
|
|
.div_flags = df, \
|
|
|
|
.div_table = dt, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define GATE(_id, cname, pname, f, o, b, gf) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_gate, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.flags = f, \
|
|
|
|
.gate_offset = o, \
|
|
|
|
.gate_shift = b, \
|
|
|
|
.gate_flags = gf, \
|
|
|
|
}
|
|
|
|
|
2014-11-27 02:30:27 +01:00
|
|
|
#define MMC(_id, cname, pname, offset, shift) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_mmc, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.muxdiv_offset = offset, \
|
|
|
|
.div_shift = shift, \
|
|
|
|
}
|
2014-07-03 01:58:39 +02:00
|
|
|
|
2015-07-05 11:00:14 +02:00
|
|
|
#define INVERTER(_id, cname, pname, io, is, if) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_inverter, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.muxdiv_offset = io, \
|
|
|
|
.div_shift = is, \
|
|
|
|
.div_flags = if, \
|
|
|
|
}
|
|
|
|
|
2015-06-20 13:08:57 +02:00
|
|
|
#define FACTOR(_id, cname, pname, f, fm, fd) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_factor, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.flags = f, \
|
|
|
|
.div_shift = fm, \
|
|
|
|
.div_width = fd, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
|
|
|
|
{ \
|
|
|
|
.id = _id, \
|
|
|
|
.branch_type = branch_factor, \
|
|
|
|
.name = cname, \
|
|
|
|
.parent_names = (const char *[]){ pname }, \
|
|
|
|
.num_parents = 1, \
|
|
|
|
.flags = f, \
|
|
|
|
.div_shift = fm, \
|
|
|
|
.div_width = fd, \
|
|
|
|
.gate_offset = go, \
|
|
|
|
.gate_shift = gb, \
|
|
|
|
.gate_flags = gf, \
|
|
|
|
}
|
|
|
|
|
2016-03-09 03:37:04 +01:00
|
|
|
struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
|
|
|
|
void __iomem *base, unsigned long nr_clks);
|
|
|
|
void rockchip_clk_of_add_provider(struct device_node *np,
|
|
|
|
struct rockchip_clk_provider *ctx);
|
|
|
|
void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
|
|
|
|
struct clk *clk, unsigned int id);
|
|
|
|
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
|
|
|
|
struct rockchip_clk_branch *list,
|
2014-07-03 01:58:39 +02:00
|
|
|
unsigned int nr_clk);
|
2016-03-09 03:37:04 +01:00
|
|
|
void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
|
|
|
|
struct rockchip_pll_clock *pll_list,
|
2014-07-03 01:59:10 +02:00
|
|
|
unsigned int nr_pll, int grf_lock_offset);
|
2016-03-09 03:37:04 +01:00
|
|
|
void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
|
|
|
|
unsigned int lookup_id, const char *name,
|
2015-05-28 10:45:51 +02:00
|
|
|
const char *const *parent_names, u8 num_parents,
|
2014-09-04 22:10:43 +02:00
|
|
|
const struct rockchip_cpuclk_reg_data *reg_data,
|
|
|
|
const struct rockchip_cpuclk_rate_table *rates,
|
|
|
|
int nrates);
|
2015-02-18 10:59:45 +01:00
|
|
|
void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
|
2016-03-09 03:37:04 +01:00
|
|
|
void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
|
|
|
|
unsigned int reg, void (*cb)(void));
|
2014-07-03 01:58:39 +02:00
|
|
|
|
2014-07-03 01:59:39 +02:00
|
|
|
#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
|
|
|
|
|
|
|
|
#ifdef CONFIG_RESET_CONTROLLER
|
|
|
|
void rockchip_register_softrst(struct device_node *np,
|
|
|
|
unsigned int num_regs,
|
|
|
|
void __iomem *base, u8 flags);
|
|
|
|
#else
|
|
|
|
static inline void rockchip_register_softrst(struct device_node *np,
|
|
|
|
unsigned int num_regs,
|
|
|
|
void __iomem *base, u8 flags)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-07-03 01:58:39 +02:00
|
|
|
#endif
|