2011-11-08 11:49:46 +01:00
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/*
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* i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
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*
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* Copyright (C) 2011 Weinmann Medical GmbH
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* Author: Nikolaus Voss <n.voss@weinmann.de>
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*
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* Evolved from original work by:
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* Copyright (C) 2004 Rick Bronson
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* Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
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*
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* Borrowed heavily from original work by:
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* Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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2012-11-23 10:09:04 +01:00
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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2011-11-08 11:49:46 +01:00
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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2012-09-12 08:42:14 +02:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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2011-11-08 11:49:46 +01:00
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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2012-11-23 10:09:04 +01:00
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#include <linux/platform_data/dma-atmel.h>
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2014-10-24 08:50:15 +02:00
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#include <linux/pm_runtime.h>
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2014-11-10 02:55:52 +01:00
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#include <linux/pinctrl/consumer.h>
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2011-11-08 11:49:46 +01:00
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2014-03-11 05:25:38 +01:00
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#define DEFAULT_TWI_CLK_HZ 100000 /* max 400 Kbits/s */
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2011-11-08 11:49:46 +01:00
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#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
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2012-11-23 10:09:04 +01:00
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#define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */
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2014-10-24 08:50:15 +02:00
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#define AUTOSUSPEND_TIMEOUT 2000
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2016-08-03 16:58:26 +02:00
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#define AT91_I2C_MAX_ALT_CMD_DATA_SIZE 256
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2011-11-08 11:49:46 +01:00
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/* AT91 TWI register definitions */
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#define AT91_TWI_CR 0x0000 /* Control Register */
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2015-06-09 18:22:15 +02:00
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#define AT91_TWI_START BIT(0) /* Send a Start Condition */
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#define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */
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#define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */
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#define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
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#define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */
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#define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
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#define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
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#define AT91_TWI_SWRST BIT(7) /* Software Reset */
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i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
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#define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */
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#define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
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#define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */
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#define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */
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#define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */
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2015-06-09 18:22:19 +02:00
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#define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */
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#define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
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2011-11-08 11:49:46 +01:00
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#define AT91_TWI_MMR 0x0004 /* Master Mode Register */
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#define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
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2015-06-09 18:22:15 +02:00
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#define AT91_TWI_MREAD BIT(12) /* Master Read Direction */
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2011-11-08 11:49:46 +01:00
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#define AT91_TWI_IADR 0x000c /* Internal Address Register */
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#define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
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2015-12-03 10:53:50 +01:00
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#define AT91_TWI_CWGR_HOLD_MAX 0x1f
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#define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
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2011-11-08 11:49:46 +01:00
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#define AT91_TWI_SR 0x0020 /* Status Register */
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2015-06-09 18:22:15 +02:00
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#define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */
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#define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */
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#define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */
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#define AT91_TWI_OVRE BIT(6) /* Overrun Error */
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#define AT91_TWI_UNRE BIT(7) /* Underrun Error */
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#define AT91_TWI_NACK BIT(8) /* Not Acknowledged */
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i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
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#define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */
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2011-11-08 11:49:46 +01:00
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i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
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#define AT91_TWI_INT_MASK \
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(AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK)
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2011-11-08 11:49:46 +01:00
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#define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
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#define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
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#define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */
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#define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
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#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
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i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
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#define AT91_TWI_ACR 0x0040 /* Alternative Command Register */
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#define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
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#define AT91_TWI_ACR_DIR BIT(8)
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2015-06-09 18:22:19 +02:00
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#define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */
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#define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
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#define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
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#define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
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#define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
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#define AT91_TWI_ONE_DATA 0x0
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#define AT91_TWI_TWO_DATA 0x1
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#define AT91_TWI_FOUR_DATA 0x2
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#define AT91_TWI_FLR 0x0054 /* FIFO Level Register */
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#define AT91_TWI_FSR 0x0060 /* FIFO Status Register */
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#define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */
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#define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */
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#define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */
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2015-06-09 18:22:18 +02:00
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#define AT91_TWI_VER 0x00fc /* Version Register */
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2011-11-08 11:49:46 +01:00
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struct at91_twi_pdata {
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2012-11-23 10:09:03 +01:00
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unsigned clk_max_div;
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unsigned clk_offset;
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bool has_unre_flag;
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i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
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bool has_alt_cmd;
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2015-12-03 10:53:50 +01:00
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bool has_hold_field;
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2012-11-23 10:09:04 +01:00
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struct at_dma_slave dma_slave;
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};
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struct at91_twi_dma {
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struct dma_chan *chan_rx;
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struct dma_chan *chan_tx;
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2015-06-09 18:22:19 +02:00
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struct scatterlist sg[2];
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2012-11-23 10:09:04 +01:00
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struct dma_async_tx_descriptor *data_desc;
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enum dma_data_direction direction;
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bool buf_mapped;
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bool xfer_in_progress;
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2011-11-08 11:49:46 +01:00
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};
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struct at91_twi_dev {
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2012-11-23 10:09:03 +01:00
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struct device *dev;
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void __iomem *base;
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struct completion cmd_complete;
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struct clk *clk;
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u8 *buf;
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size_t buf_len;
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struct i2c_msg *msg;
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int irq;
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2012-11-23 10:09:04 +01:00
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unsigned imr;
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2012-11-23 10:09:03 +01:00
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unsigned transfer_status;
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struct i2c_adapter adapter;
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unsigned twi_cwgr_reg;
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struct at91_twi_pdata *pdata;
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2012-11-23 10:09:04 +01:00
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bool use_dma;
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2016-08-03 16:58:26 +02:00
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bool use_alt_cmd;
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2014-08-21 03:39:41 +02:00
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bool recv_len_abort;
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2015-06-09 18:22:19 +02:00
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u32 fifo_size;
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2012-11-23 10:09:04 +01:00
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struct at91_twi_dma dma;
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2011-11-08 11:49:46 +01:00
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};
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static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
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{
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return readl_relaxed(dev->base + reg);
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}
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static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
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{
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writel_relaxed(val, dev->base + reg);
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}
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static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
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{
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i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK);
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
|
2012-11-23 10:09:04 +01:00
|
|
|
static void at91_twi_irq_save(struct at91_twi_dev *dev)
|
|
|
|
{
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK;
|
2012-11-23 10:09:04 +01:00
|
|
|
at91_disable_twi_interrupts(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void at91_twi_irq_restore(struct at91_twi_dev *dev)
|
|
|
|
{
|
|
|
|
at91_twi_write(dev, AT91_TWI_IER, dev->imr);
|
|
|
|
}
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
static void at91_init_twi_bus(struct at91_twi_dev *dev)
|
|
|
|
{
|
|
|
|
at91_disable_twi_interrupts(dev);
|
|
|
|
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
|
2015-06-09 18:22:19 +02:00
|
|
|
/* FIFO should be enabled immediately after the software reset */
|
|
|
|
if (dev->fifo_size)
|
|
|
|
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_FIFOEN);
|
2011-11-08 11:49:46 +01:00
|
|
|
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
|
|
|
|
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
|
|
|
|
at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Calculate symmetric clock as stated in datasheet:
|
|
|
|
* twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
|
|
|
|
*/
|
2012-11-27 21:59:38 +01:00
|
|
|
static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
|
2011-11-08 11:49:46 +01:00
|
|
|
{
|
2015-12-03 10:53:50 +01:00
|
|
|
int ckdiv, cdiv, div, hold = 0;
|
2011-11-08 11:49:46 +01:00
|
|
|
struct at91_twi_pdata *pdata = dev->pdata;
|
|
|
|
int offset = pdata->clk_offset;
|
|
|
|
int max_ckdiv = pdata->clk_max_div;
|
2015-12-03 10:53:50 +01:00
|
|
|
u32 twd_hold_time_ns = 0;
|
2011-11-08 11:49:46 +01:00
|
|
|
|
|
|
|
div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
|
|
|
|
2 * twi_clk) - offset);
|
|
|
|
ckdiv = fls(div >> 8);
|
|
|
|
cdiv = div >> ckdiv;
|
|
|
|
|
|
|
|
if (ckdiv > max_ckdiv) {
|
|
|
|
dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
|
|
|
|
ckdiv, max_ckdiv);
|
|
|
|
ckdiv = max_ckdiv;
|
|
|
|
cdiv = 255;
|
|
|
|
}
|
|
|
|
|
2015-12-03 10:53:50 +01:00
|
|
|
if (pdata->has_hold_field) {
|
|
|
|
of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
|
|
|
|
&twd_hold_time_ns);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* hold time = HOLD + 3 x T_peripheral_clock
|
|
|
|
* Use clk rate in kHz to prevent overflows when computing
|
|
|
|
* hold.
|
|
|
|
*/
|
|
|
|
hold = DIV_ROUND_UP(twd_hold_time_ns
|
|
|
|
* (clk_get_rate(dev->clk) / 1000), 1000000);
|
|
|
|
hold -= 3;
|
|
|
|
if (hold < 0)
|
|
|
|
hold = 0;
|
|
|
|
if (hold > AT91_TWI_CWGR_HOLD_MAX) {
|
|
|
|
dev_warn(dev->dev,
|
|
|
|
"HOLD field set to its maximum value (%d instead of %d)\n",
|
|
|
|
AT91_TWI_CWGR_HOLD_MAX, hold);
|
|
|
|
hold = AT91_TWI_CWGR_HOLD_MAX;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
|
|
|
|
| AT91_TWI_CWGR_HOLD(hold);
|
|
|
|
|
|
|
|
dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
|
|
|
|
cdiv, ckdiv, hold, twd_hold_time_ns);
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
|
2012-11-23 10:09:04 +01:00
|
|
|
static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
|
|
|
|
{
|
|
|
|
struct at91_twi_dma *dma = &dev->dma;
|
|
|
|
|
|
|
|
at91_twi_irq_save(dev);
|
|
|
|
|
|
|
|
if (dma->xfer_in_progress) {
|
|
|
|
if (dma->direction == DMA_FROM_DEVICE)
|
|
|
|
dmaengine_terminate_all(dma->chan_rx);
|
|
|
|
else
|
|
|
|
dmaengine_terminate_all(dma->chan_tx);
|
|
|
|
dma->xfer_in_progress = false;
|
|
|
|
}
|
|
|
|
if (dma->buf_mapped) {
|
2015-06-09 18:22:19 +02:00
|
|
|
dma_unmap_single(dev->dev, sg_dma_address(&dma->sg[0]),
|
2012-11-23 10:09:04 +01:00
|
|
|
dev->buf_len, dma->direction);
|
|
|
|
dma->buf_mapped = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
at91_twi_irq_restore(dev);
|
|
|
|
}
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
|
|
|
|
{
|
2015-06-11 11:16:32 +02:00
|
|
|
if (!dev->buf_len)
|
2011-11-08 11:49:46 +01:00
|
|
|
return;
|
|
|
|
|
2015-06-09 18:22:19 +02:00
|
|
|
/* 8bit write works with and without FIFO */
|
|
|
|
writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR);
|
2011-11-08 11:49:46 +01:00
|
|
|
|
|
|
|
/* send stop when last byte has been written */
|
|
|
|
if (--dev->buf_len == 0)
|
2016-08-03 16:58:26 +02:00
|
|
|
if (!dev->use_alt_cmd)
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
|
2011-11-08 11:49:46 +01:00
|
|
|
|
2017-05-31 09:15:38 +02:00
|
|
|
dev_dbg(dev->dev, "wrote 0x%x, to go %zu\n", *dev->buf, dev->buf_len);
|
2011-11-08 11:49:46 +01:00
|
|
|
|
|
|
|
++dev->buf;
|
|
|
|
}
|
|
|
|
|
2012-11-23 10:09:04 +01:00
|
|
|
static void at91_twi_write_data_dma_callback(void *data)
|
|
|
|
{
|
|
|
|
struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
|
|
|
|
|
2015-06-09 18:22:19 +02:00
|
|
|
dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
|
2014-07-21 11:42:03 +02:00
|
|
|
dev->buf_len, DMA_TO_DEVICE);
|
2012-11-23 10:09:04 +01:00
|
|
|
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
/*
|
|
|
|
* When this callback is called, THR/TX FIFO is likely not to be empty
|
|
|
|
* yet. So we have to wait for TXCOMP or NACK bits to be set into the
|
|
|
|
* Status Register to be sure that the STOP bit has been sent and the
|
|
|
|
* transfer is completed. The NACK interrupt has already been enabled,
|
|
|
|
* we just have to enable TXCOMP one.
|
|
|
|
*/
|
|
|
|
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
|
2016-08-03 16:58:26 +02:00
|
|
|
if (!dev->use_alt_cmd)
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
|
2012-11-23 10:09:04 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
|
|
|
|
{
|
|
|
|
dma_addr_t dma_addr;
|
|
|
|
struct dma_async_tx_descriptor *txdesc;
|
|
|
|
struct at91_twi_dma *dma = &dev->dma;
|
|
|
|
struct dma_chan *chan_tx = dma->chan_tx;
|
2015-06-09 18:22:19 +02:00
|
|
|
unsigned int sg_len = 1;
|
2012-11-23 10:09:04 +01:00
|
|
|
|
2015-06-11 11:16:32 +02:00
|
|
|
if (!dev->buf_len)
|
2012-11-23 10:09:04 +01:00
|
|
|
return;
|
|
|
|
|
|
|
|
dma->direction = DMA_TO_DEVICE;
|
|
|
|
|
|
|
|
at91_twi_irq_save(dev);
|
|
|
|
dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (dma_mapping_error(dev->dev, dma_addr)) {
|
|
|
|
dev_err(dev->dev, "dma map failed\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
dma->buf_mapped = true;
|
|
|
|
at91_twi_irq_restore(dev);
|
|
|
|
|
2015-06-09 18:22:19 +02:00
|
|
|
if (dev->fifo_size) {
|
|
|
|
size_t part1_len, part2_len;
|
|
|
|
struct scatterlist *sg;
|
|
|
|
unsigned fifo_mr;
|
|
|
|
|
|
|
|
sg_len = 0;
|
|
|
|
|
|
|
|
part1_len = dev->buf_len & ~0x3;
|
|
|
|
if (part1_len) {
|
|
|
|
sg = &dma->sg[sg_len++];
|
|
|
|
sg_dma_len(sg) = part1_len;
|
|
|
|
sg_dma_address(sg) = dma_addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
part2_len = dev->buf_len & 0x3;
|
|
|
|
if (part2_len) {
|
|
|
|
sg = &dma->sg[sg_len++];
|
|
|
|
sg_dma_len(sg) = part2_len;
|
|
|
|
sg_dma_address(sg) = dma_addr + part1_len;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DMA controller is triggered when at least 4 data can be
|
|
|
|
* written into the TX FIFO
|
|
|
|
*/
|
|
|
|
fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
|
|
|
|
fifo_mr &= ~AT91_TWI_FMR_TXRDYM_MASK;
|
|
|
|
fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_FOUR_DATA);
|
|
|
|
at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
|
|
|
|
} else {
|
|
|
|
sg_dma_len(&dma->sg[0]) = dev->buf_len;
|
|
|
|
sg_dma_address(&dma->sg[0]) = dma_addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
txdesc = dmaengine_prep_slave_sg(chan_tx, dma->sg, sg_len,
|
|
|
|
DMA_MEM_TO_DEV,
|
2012-11-23 10:09:04 +01:00
|
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
|
if (!txdesc) {
|
|
|
|
dev_err(dev->dev, "dma prep slave sg failed\n");
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
txdesc->callback = at91_twi_write_data_dma_callback;
|
|
|
|
txdesc->callback_param = dev;
|
|
|
|
|
|
|
|
dma->xfer_in_progress = true;
|
|
|
|
dmaengine_submit(txdesc);
|
|
|
|
dma_async_issue_pending(chan_tx);
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
error:
|
|
|
|
at91_twi_dma_cleanup(dev);
|
|
|
|
}
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
|
|
|
|
{
|
2015-10-26 10:38:27 +01:00
|
|
|
/*
|
|
|
|
* If we are in this case, it means there is garbage data in RHR, so
|
|
|
|
* delete them.
|
|
|
|
*/
|
|
|
|
if (!dev->buf_len) {
|
|
|
|
at91_twi_read(dev, AT91_TWI_RHR);
|
2011-11-08 11:49:46 +01:00
|
|
|
return;
|
2015-10-26 10:38:27 +01:00
|
|
|
}
|
2011-11-08 11:49:46 +01:00
|
|
|
|
2015-06-09 18:22:19 +02:00
|
|
|
/* 8bit read works with and without FIFO */
|
|
|
|
*dev->buf = readb_relaxed(dev->base + AT91_TWI_RHR);
|
2011-11-08 11:49:46 +01:00
|
|
|
--dev->buf_len;
|
|
|
|
|
2014-08-21 03:39:41 +02:00
|
|
|
/* return if aborting, we only needed to read RHR to clear RXRDY*/
|
|
|
|
if (dev->recv_len_abort)
|
|
|
|
return;
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
/* handle I2C_SMBUS_BLOCK_DATA */
|
|
|
|
if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
|
2014-08-21 03:39:41 +02:00
|
|
|
/* ensure length byte is a valid value */
|
|
|
|
if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) {
|
|
|
|
dev->msg->flags &= ~I2C_M_RECV_LEN;
|
|
|
|
dev->buf_len += *dev->buf;
|
|
|
|
dev->msg->len = dev->buf_len + 1;
|
2017-05-31 09:15:38 +02:00
|
|
|
dev_dbg(dev->dev, "received block length %zu\n",
|
2014-08-21 03:39:41 +02:00
|
|
|
dev->buf_len);
|
|
|
|
} else {
|
|
|
|
/* abort and send the stop by reading one more byte */
|
|
|
|
dev->recv_len_abort = true;
|
|
|
|
dev->buf_len = 1;
|
|
|
|
}
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* send stop if second but last byte has been read */
|
2016-08-03 16:58:26 +02:00
|
|
|
if (!dev->use_alt_cmd && dev->buf_len == 1)
|
2011-11-08 11:49:46 +01:00
|
|
|
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
|
|
|
|
|
2017-05-31 09:15:38 +02:00
|
|
|
dev_dbg(dev->dev, "read 0x%x, to go %zu\n", *dev->buf, dev->buf_len);
|
2011-11-08 11:49:46 +01:00
|
|
|
|
|
|
|
++dev->buf;
|
|
|
|
}
|
|
|
|
|
2012-11-23 10:09:04 +01:00
|
|
|
static void at91_twi_read_data_dma_callback(void *data)
|
|
|
|
{
|
|
|
|
struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
unsigned ier = AT91_TWI_TXCOMP;
|
2012-11-23 10:09:04 +01:00
|
|
|
|
2015-06-09 18:22:19 +02:00
|
|
|
dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
|
2014-07-21 11:42:03 +02:00
|
|
|
dev->buf_len, DMA_FROM_DEVICE);
|
2012-11-23 10:09:04 +01:00
|
|
|
|
2016-08-03 16:58:26 +02:00
|
|
|
if (!dev->use_alt_cmd) {
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
/* The last two bytes have to be read without using dma */
|
|
|
|
dev->buf += dev->buf_len - 2;
|
|
|
|
dev->buf_len = 2;
|
|
|
|
ier |= AT91_TWI_RXRDY;
|
|
|
|
}
|
|
|
|
at91_twi_write(dev, AT91_TWI_IER, ier);
|
2012-11-23 10:09:04 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
|
|
|
|
{
|
|
|
|
dma_addr_t dma_addr;
|
|
|
|
struct dma_async_tx_descriptor *rxdesc;
|
|
|
|
struct at91_twi_dma *dma = &dev->dma;
|
|
|
|
struct dma_chan *chan_rx = dma->chan_rx;
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
size_t buf_len;
|
2012-11-23 10:09:04 +01:00
|
|
|
|
2016-08-03 16:58:26 +02:00
|
|
|
buf_len = (dev->use_alt_cmd) ? dev->buf_len : dev->buf_len - 2;
|
2012-11-23 10:09:04 +01:00
|
|
|
dma->direction = DMA_FROM_DEVICE;
|
|
|
|
|
|
|
|
/* Keep in mind that we won't use dma to read the last two bytes */
|
|
|
|
at91_twi_irq_save(dev);
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
dma_addr = dma_map_single(dev->dev, dev->buf, buf_len, DMA_FROM_DEVICE);
|
2012-11-23 10:09:04 +01:00
|
|
|
if (dma_mapping_error(dev->dev, dma_addr)) {
|
|
|
|
dev_err(dev->dev, "dma map failed\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
dma->buf_mapped = true;
|
|
|
|
at91_twi_irq_restore(dev);
|
|
|
|
|
2015-06-09 18:22:19 +02:00
|
|
|
if (dev->fifo_size && IS_ALIGNED(buf_len, 4)) {
|
|
|
|
unsigned fifo_mr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DMA controller is triggered when at least 4 data can be
|
|
|
|
* read from the RX FIFO
|
|
|
|
*/
|
|
|
|
fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
|
|
|
|
fifo_mr &= ~AT91_TWI_FMR_RXRDYM_MASK;
|
|
|
|
fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_FOUR_DATA);
|
|
|
|
at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
|
|
|
|
}
|
|
|
|
|
|
|
|
sg_dma_len(&dma->sg[0]) = buf_len;
|
|
|
|
sg_dma_address(&dma->sg[0]) = dma_addr;
|
|
|
|
|
|
|
|
rxdesc = dmaengine_prep_slave_sg(chan_rx, dma->sg, 1, DMA_DEV_TO_MEM,
|
2012-11-23 10:09:04 +01:00
|
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
|
if (!rxdesc) {
|
|
|
|
dev_err(dev->dev, "dma prep slave sg failed\n");
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
rxdesc->callback = at91_twi_read_data_dma_callback;
|
|
|
|
rxdesc->callback_param = dev;
|
|
|
|
|
|
|
|
dma->xfer_in_progress = true;
|
|
|
|
dmaengine_submit(rxdesc);
|
|
|
|
dma_async_issue_pending(dma->chan_rx);
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
error:
|
|
|
|
at91_twi_dma_cleanup(dev);
|
|
|
|
}
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct at91_twi_dev *dev = dev_id;
|
|
|
|
const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
|
|
|
|
const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
|
|
|
|
|
|
|
|
if (!irqstatus)
|
|
|
|
return IRQ_NONE;
|
2015-10-26 10:38:27 +01:00
|
|
|
/*
|
|
|
|
* In reception, the behavior of the twi device (before sama5d2) is
|
|
|
|
* weird. There is some magic about RXRDY flag! When a data has been
|
|
|
|
* almost received, the reception of a new one is anticipated if there
|
|
|
|
* is no stop command to send. That is the reason why ask for sending
|
|
|
|
* the stop command not on the last data but on the second last one.
|
|
|
|
*
|
|
|
|
* Unfortunately, we could still have the RXRDY flag set even if the
|
|
|
|
* transfer is done and we have read the last data. It might happen
|
|
|
|
* when the i2c slave device sends too quickly data after receiving the
|
|
|
|
* ack from the master. The data has been almost received before having
|
|
|
|
* the order to send stop. In this case, sending the stop command could
|
|
|
|
* cause a RXRDY interrupt with a TXCOMP one. It is better to manage
|
|
|
|
* the RXRDY interrupt first in order to not keep garbage data in the
|
|
|
|
* Receive Holding Register for the next transfer.
|
|
|
|
*/
|
2018-04-26 11:53:14 +02:00
|
|
|
if (irqstatus & AT91_TWI_RXRDY) {
|
|
|
|
/*
|
|
|
|
* Read all available bytes at once by polling RXRDY usable w/
|
|
|
|
* and w/o FIFO. With FIFO enabled we could also read RXFL and
|
|
|
|
* avoid polling RXRDY.
|
|
|
|
*/
|
|
|
|
do {
|
|
|
|
at91_twi_read_next_byte(dev);
|
|
|
|
} while (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY);
|
|
|
|
}
|
2011-11-08 11:49:46 +01:00
|
|
|
|
2015-10-21 15:44:03 +02:00
|
|
|
/*
|
|
|
|
* When a NACK condition is detected, the I2C controller sets the NACK,
|
|
|
|
* TXCOMP and TXRDY bits all together in the Status Register (SR).
|
|
|
|
*
|
|
|
|
* 1 - Handling NACK errors with CPU write transfer.
|
|
|
|
*
|
|
|
|
* In such case, we should not write the next byte into the Transmit
|
|
|
|
* Holding Register (THR) otherwise the I2C controller would start a new
|
|
|
|
* transfer and the I2C slave is likely to reply by another NACK.
|
|
|
|
*
|
|
|
|
* 2 - Handling NACK errors with DMA write transfer.
|
|
|
|
*
|
|
|
|
* By setting the TXRDY bit in the SR, the I2C controller also triggers
|
|
|
|
* the DMA controller to write the next data into the THR. Then the
|
|
|
|
* result depends on the hardware version of the I2C controller.
|
|
|
|
*
|
|
|
|
* 2a - Without support of the Alternative Command mode.
|
|
|
|
*
|
|
|
|
* This is the worst case: the DMA controller is triggered to write the
|
|
|
|
* next data into the THR, hence starting a new transfer: the I2C slave
|
|
|
|
* is likely to reply by another NACK.
|
|
|
|
* Concurrently, this interrupt handler is likely to be called to manage
|
|
|
|
* the first NACK before the I2C controller detects the second NACK and
|
|
|
|
* sets once again the NACK bit into the SR.
|
|
|
|
* When handling the first NACK, this interrupt handler disables the I2C
|
|
|
|
* controller interruptions, especially the NACK interrupt.
|
|
|
|
* Hence, the NACK bit is pending into the SR. This is why we should
|
|
|
|
* read the SR to clear all pending interrupts at the beginning of
|
|
|
|
* at91_do_twi_transfer() before actually starting a new transfer.
|
|
|
|
*
|
|
|
|
* 2b - With support of the Alternative Command mode.
|
|
|
|
*
|
|
|
|
* When a NACK condition is detected, the I2C controller also locks the
|
|
|
|
* THR (and sets the LOCK bit in the SR): even though the DMA controller
|
|
|
|
* is triggered by the TXRDY bit to write the next data into the THR,
|
|
|
|
* this data actually won't go on the I2C bus hence a second NACK is not
|
|
|
|
* generated.
|
|
|
|
*/
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
if (irqstatus & (AT91_TWI_TXCOMP | AT91_TWI_NACK)) {
|
2011-11-08 11:49:46 +01:00
|
|
|
at91_disable_twi_interrupts(dev);
|
|
|
|
complete(&dev->cmd_complete);
|
2015-10-21 15:44:03 +02:00
|
|
|
} else if (irqstatus & AT91_TWI_TXRDY) {
|
|
|
|
at91_twi_write_next_byte(dev);
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
|
2015-10-21 15:44:03 +02:00
|
|
|
/* catch error flags */
|
|
|
|
dev->transfer_status |= status;
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int at91_do_twi_transfer(struct at91_twi_dev *dev)
|
|
|
|
{
|
|
|
|
int ret;
|
2015-02-08 17:12:07 +01:00
|
|
|
unsigned long time_left;
|
2011-11-08 11:49:46 +01:00
|
|
|
bool has_unre_flag = dev->pdata->has_unre_flag;
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
bool has_alt_cmd = dev->pdata->has_alt_cmd;
|
2011-11-08 11:49:46 +01:00
|
|
|
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
/*
|
|
|
|
* WARNING: the TXCOMP bit in the Status Register is NOT a clear on
|
|
|
|
* read flag but shows the state of the transmission at the time the
|
|
|
|
* Status Register is read. According to the programmer datasheet,
|
|
|
|
* TXCOMP is set when both holding register and internal shifter are
|
|
|
|
* empty and STOP condition has been sent.
|
|
|
|
* Consequently, we should enable NACK interrupt rather than TXCOMP to
|
|
|
|
* detect transmission failure.
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
* Indeed let's take the case of an i2c write command using DMA.
|
|
|
|
* Whenever the slave doesn't acknowledge a byte, the LOCK, NACK and
|
|
|
|
* TXCOMP bits are set together into the Status Register.
|
|
|
|
* LOCK is a clear on write bit, which is set to prevent the DMA
|
|
|
|
* controller from sending new data on the i2c bus after a NACK
|
|
|
|
* condition has happened. Once locked, this i2c peripheral stops
|
|
|
|
* triggering the DMA controller for new data but it is more than
|
|
|
|
* likely that a new DMA transaction is already in progress, writing
|
|
|
|
* into the Transmit Holding Register. Since the peripheral is locked,
|
|
|
|
* these new data won't be sent to the i2c bus but they will remain
|
|
|
|
* into the Transmit Holding Register, so TXCOMP bit is cleared.
|
|
|
|
* Then when the interrupt handler is called, the Status Register is
|
|
|
|
* read: the TXCOMP bit is clear but NACK bit is still set. The driver
|
|
|
|
* manage the error properly, without waiting for timeout.
|
|
|
|
* This case can be reproduced easyly when writing into an at24 eeprom.
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
*
|
|
|
|
* Besides, the TXCOMP bit is already set before the i2c transaction
|
|
|
|
* has been started. For read transactions, this bit is cleared when
|
|
|
|
* writing the START bit into the Control Register. So the
|
|
|
|
* corresponding interrupt can safely be enabled just after.
|
|
|
|
* However for write transactions managed by the CPU, we first write
|
|
|
|
* into THR, so TXCOMP is cleared. Then we can safely enable TXCOMP
|
|
|
|
* interrupt. If TXCOMP interrupt were enabled before writing into THR,
|
|
|
|
* the interrupt handler would be called immediately and the i2c command
|
|
|
|
* would be reported as completed.
|
|
|
|
* Also when a write transaction is managed by the DMA controller,
|
|
|
|
* enabling the TXCOMP interrupt in this function may lead to a race
|
|
|
|
* condition since we don't know whether the TXCOMP interrupt is enabled
|
|
|
|
* before or after the DMA has started to write into THR. So the TXCOMP
|
|
|
|
* interrupt is enabled later by at91_twi_write_data_dma_callback().
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
* Immediately after in that DMA callback, if the alternative command
|
|
|
|
* mode is not used, we still need to send the STOP condition manually
|
|
|
|
* writing the corresponding bit into the Control Register.
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
*/
|
|
|
|
|
2017-05-31 09:15:38 +02:00
|
|
|
dev_dbg(dev->dev, "transfer: %s %zu bytes.\n",
|
2011-11-08 11:49:46 +01:00
|
|
|
(dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
|
|
|
|
|
2013-11-14 23:32:02 +01:00
|
|
|
reinit_completion(&dev->cmd_complete);
|
2011-11-08 11:49:46 +01:00
|
|
|
dev->transfer_status = 0;
|
2012-11-13 16:43:21 +01:00
|
|
|
|
2015-10-21 15:44:03 +02:00
|
|
|
/* Clear pending interrupts, such as NACK. */
|
2015-10-26 10:38:27 +01:00
|
|
|
at91_twi_read(dev, AT91_TWI_SR);
|
2015-10-21 15:44:03 +02:00
|
|
|
|
2015-06-09 18:22:19 +02:00
|
|
|
if (dev->fifo_size) {
|
|
|
|
unsigned fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
|
|
|
|
|
|
|
|
/* Reset FIFO mode register */
|
|
|
|
fifo_mr &= ~(AT91_TWI_FMR_TXRDYM_MASK |
|
|
|
|
AT91_TWI_FMR_RXRDYM_MASK);
|
|
|
|
fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_ONE_DATA);
|
|
|
|
fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_ONE_DATA);
|
|
|
|
at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
|
|
|
|
|
|
|
|
/* Flush FIFOs */
|
|
|
|
at91_twi_write(dev, AT91_TWI_CR,
|
|
|
|
AT91_TWI_THRCLR | AT91_TWI_RHRCLR);
|
|
|
|
}
|
|
|
|
|
2012-11-13 16:43:21 +01:00
|
|
|
if (!dev->buf_len) {
|
|
|
|
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
|
|
|
|
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
|
|
|
|
} else if (dev->msg->flags & I2C_M_RD) {
|
2011-11-08 11:49:46 +01:00
|
|
|
unsigned start_flags = AT91_TWI_START;
|
|
|
|
|
|
|
|
/* if only one byte is to be read, immediately stop transfer */
|
2016-08-03 16:58:26 +02:00
|
|
|
if (!dev->use_alt_cmd && dev->buf_len <= 1 &&
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
!(dev->msg->flags & I2C_M_RECV_LEN))
|
2011-11-08 11:49:46 +01:00
|
|
|
start_flags |= AT91_TWI_STOP;
|
|
|
|
at91_twi_write(dev, AT91_TWI_CR, start_flags);
|
2012-11-23 10:09:04 +01:00
|
|
|
/*
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
* When using dma without alternative command mode, the last
|
|
|
|
* byte has to be read manually in order to not send the stop
|
|
|
|
* command too late and then to receive extra data.
|
|
|
|
* In practice, there are some issues if you use the dma to
|
|
|
|
* read n-1 bytes because of latency.
|
2012-11-23 10:09:04 +01:00
|
|
|
* Reading n-2 bytes with dma and the two last ones manually
|
|
|
|
* seems to be the best solution.
|
|
|
|
*/
|
|
|
|
if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
|
2012-11-23 10:09:04 +01:00
|
|
|
at91_twi_read_data_dma(dev);
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
} else {
|
2012-11-23 10:09:04 +01:00
|
|
|
at91_twi_write(dev, AT91_TWI_IER,
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
AT91_TWI_TXCOMP |
|
|
|
|
AT91_TWI_NACK |
|
|
|
|
AT91_TWI_RXRDY);
|
|
|
|
}
|
2011-11-08 11:49:46 +01:00
|
|
|
} else {
|
2012-11-23 10:09:04 +01:00
|
|
|
if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
|
2012-11-23 10:09:04 +01:00
|
|
|
at91_twi_write_data_dma(dev);
|
|
|
|
} else {
|
|
|
|
at91_twi_write_next_byte(dev);
|
|
|
|
at91_twi_write(dev, AT91_TWI_IER,
|
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().
Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.
For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:14 +02:00
|
|
|
AT91_TWI_TXCOMP |
|
|
|
|
AT91_TWI_NACK |
|
|
|
|
AT91_TWI_TXRDY);
|
2012-11-23 10:09:04 +01:00
|
|
|
}
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
|
2015-02-08 17:12:07 +01:00
|
|
|
time_left = wait_for_completion_timeout(&dev->cmd_complete,
|
|
|
|
dev->adapter.timeout);
|
|
|
|
if (time_left == 0) {
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
dev->transfer_status |= at91_twi_read(dev, AT91_TWI_SR);
|
2011-11-08 11:49:46 +01:00
|
|
|
dev_err(dev->dev, "controller timed out\n");
|
|
|
|
at91_init_twi_bus(dev);
|
2012-11-23 10:09:04 +01:00
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
goto error;
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
if (dev->transfer_status & AT91_TWI_NACK) {
|
|
|
|
dev_dbg(dev->dev, "received nack\n");
|
2012-11-23 10:09:04 +01:00
|
|
|
ret = -EREMOTEIO;
|
|
|
|
goto error;
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
if (dev->transfer_status & AT91_TWI_OVRE) {
|
|
|
|
dev_err(dev->dev, "overrun while reading\n");
|
2012-11-23 10:09:04 +01:00
|
|
|
ret = -EIO;
|
|
|
|
goto error;
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
|
|
|
|
dev_err(dev->dev, "underrun while writing\n");
|
2012-11-23 10:09:04 +01:00
|
|
|
ret = -EIO;
|
|
|
|
goto error;
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
2015-06-09 18:22:19 +02:00
|
|
|
if ((has_alt_cmd || dev->fifo_size) &&
|
|
|
|
(dev->transfer_status & AT91_TWI_LOCK)) {
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
dev_err(dev->dev, "tx locked\n");
|
|
|
|
ret = -EIO;
|
|
|
|
goto error;
|
|
|
|
}
|
2014-08-21 03:39:41 +02:00
|
|
|
if (dev->recv_len_abort) {
|
|
|
|
dev_err(dev->dev, "invalid smbus block length recvd\n");
|
|
|
|
ret = -EPROTO;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
dev_dbg(dev->dev, "transfer complete\n");
|
|
|
|
|
|
|
|
return 0;
|
2012-11-23 10:09:04 +01:00
|
|
|
|
|
|
|
error:
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
/* first stop DMA transfer if still in progress */
|
2012-11-23 10:09:04 +01:00
|
|
|
at91_twi_dma_cleanup(dev);
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
/* then flush THR/FIFO and unlock TX if locked */
|
2015-06-09 18:22:19 +02:00
|
|
|
if ((has_alt_cmd || dev->fifo_size) &&
|
|
|
|
(dev->transfer_status & AT91_TWI_LOCK)) {
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
dev_dbg(dev->dev, "unlock tx\n");
|
|
|
|
at91_twi_write(dev, AT91_TWI_CR,
|
|
|
|
AT91_TWI_THRCLR | AT91_TWI_LOCKCLR);
|
|
|
|
}
|
2012-11-23 10:09:04 +01:00
|
|
|
return ret;
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
|
|
|
|
{
|
|
|
|
struct at91_twi_dev *dev = i2c_get_adapdata(adap);
|
|
|
|
int ret;
|
|
|
|
unsigned int_addr_flag = 0;
|
|
|
|
struct i2c_msg *m_start = msg;
|
2016-08-03 16:58:26 +02:00
|
|
|
bool is_read;
|
2011-11-08 11:49:46 +01:00
|
|
|
|
|
|
|
dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
|
|
|
|
|
2014-10-24 08:50:15 +02:00
|
|
|
ret = pm_runtime_get_sync(dev->dev);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
2015-01-07 12:24:10 +01:00
|
|
|
if (num == 2) {
|
2011-11-08 11:49:46 +01:00
|
|
|
int internal_address = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* 1st msg is put into the internal address, start with 2nd */
|
|
|
|
m_start = &msg[1];
|
|
|
|
for (i = 0; i < msg->len; ++i) {
|
|
|
|
const unsigned addr = msg->buf[msg->len - 1 - i];
|
|
|
|
|
|
|
|
internal_address |= addr << (8 * i);
|
|
|
|
int_addr_flag += AT91_TWI_IADRSZ_1;
|
|
|
|
}
|
|
|
|
at91_twi_write(dev, AT91_TWI_IADR, internal_address);
|
|
|
|
}
|
|
|
|
|
2016-08-03 16:58:26 +02:00
|
|
|
dev->use_alt_cmd = false;
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
is_read = (m_start->flags & I2C_M_RD);
|
|
|
|
if (dev->pdata->has_alt_cmd) {
|
2016-08-03 16:58:26 +02:00
|
|
|
if (m_start->len > 0 &&
|
|
|
|
m_start->len < AT91_I2C_MAX_ALT_CMD_DATA_SIZE) {
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMEN);
|
|
|
|
at91_twi_write(dev, AT91_TWI_ACR,
|
|
|
|
AT91_TWI_ACR_DATAL(m_start->len) |
|
|
|
|
((is_read) ? AT91_TWI_ACR_DIR : 0));
|
2016-08-03 16:58:26 +02:00
|
|
|
dev->use_alt_cmd = true;
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
} else {
|
|
|
|
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMDIS);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
at91_twi_write(dev, AT91_TWI_MMR,
|
|
|
|
(m_start->addr << 16) |
|
|
|
|
int_addr_flag |
|
2016-08-03 16:58:26 +02:00
|
|
|
((!dev->use_alt_cmd && is_read) ? AT91_TWI_MREAD : 0));
|
2011-11-08 11:49:46 +01:00
|
|
|
|
|
|
|
dev->buf_len = m_start->len;
|
|
|
|
dev->buf = m_start->buf;
|
|
|
|
dev->msg = m_start;
|
2014-08-21 03:39:41 +02:00
|
|
|
dev->recv_len_abort = false;
|
2011-11-08 11:49:46 +01:00
|
|
|
|
|
|
|
ret = at91_do_twi_transfer(dev);
|
|
|
|
|
2014-10-24 08:50:15 +02:00
|
|
|
ret = (ret < 0) ? ret : num;
|
|
|
|
out:
|
|
|
|
pm_runtime_mark_last_busy(dev->dev);
|
|
|
|
pm_runtime_put_autosuspend(dev->dev);
|
|
|
|
|
|
|
|
return ret;
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
|
2015-01-07 12:24:10 +01:00
|
|
|
/*
|
|
|
|
* The hardware can handle at most two messages concatenated by a
|
|
|
|
* repeated start via it's internal address feature.
|
|
|
|
*/
|
2017-08-21 14:12:04 +02:00
|
|
|
static const struct i2c_adapter_quirks at91_twi_quirks = {
|
2015-01-07 12:24:10 +01:00
|
|
|
.flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
|
|
|
|
.max_comb_1st_msg_len = 3,
|
|
|
|
};
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
static u32 at91_twi_func(struct i2c_adapter *adapter)
|
|
|
|
{
|
|
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
|
|
|
|
| I2C_FUNC_SMBUS_READ_BLOCK_DATA;
|
|
|
|
}
|
|
|
|
|
2017-01-27 19:06:17 +01:00
|
|
|
static const struct i2c_algorithm at91_twi_algorithm = {
|
2011-11-08 11:49:46 +01:00
|
|
|
.master_xfer = at91_twi_xfer,
|
|
|
|
.functionality = at91_twi_func,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct at91_twi_pdata at91rm9200_config = {
|
|
|
|
.clk_max_div = 5,
|
|
|
|
.clk_offset = 3,
|
|
|
|
.has_unre_flag = true,
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
.has_alt_cmd = false,
|
2015-12-03 10:53:50 +01:00
|
|
|
.has_hold_field = false,
|
2011-11-08 11:49:46 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct at91_twi_pdata at91sam9261_config = {
|
|
|
|
.clk_max_div = 5,
|
|
|
|
.clk_offset = 4,
|
|
|
|
.has_unre_flag = false,
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
.has_alt_cmd = false,
|
2015-12-03 10:53:50 +01:00
|
|
|
.has_hold_field = false,
|
2011-11-08 11:49:46 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct at91_twi_pdata at91sam9260_config = {
|
|
|
|
.clk_max_div = 7,
|
|
|
|
.clk_offset = 4,
|
|
|
|
.has_unre_flag = false,
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
.has_alt_cmd = false,
|
2015-12-03 10:53:50 +01:00
|
|
|
.has_hold_field = false,
|
2011-11-08 11:49:46 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct at91_twi_pdata at91sam9g20_config = {
|
|
|
|
.clk_max_div = 7,
|
|
|
|
.clk_offset = 4,
|
|
|
|
.has_unre_flag = false,
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
.has_alt_cmd = false,
|
2015-12-03 10:53:50 +01:00
|
|
|
.has_hold_field = false,
|
2011-11-08 11:49:46 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct at91_twi_pdata at91sam9g10_config = {
|
|
|
|
.clk_max_div = 7,
|
|
|
|
.clk_offset = 4,
|
|
|
|
.has_unre_flag = false,
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
.has_alt_cmd = false,
|
2015-12-03 10:53:50 +01:00
|
|
|
.has_hold_field = false,
|
2011-11-08 11:49:46 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct platform_device_id at91_twi_devtypes[] = {
|
|
|
|
{
|
|
|
|
.name = "i2c-at91rm9200",
|
|
|
|
.driver_data = (unsigned long) &at91rm9200_config,
|
|
|
|
}, {
|
|
|
|
.name = "i2c-at91sam9261",
|
|
|
|
.driver_data = (unsigned long) &at91sam9261_config,
|
|
|
|
}, {
|
|
|
|
.name = "i2c-at91sam9260",
|
|
|
|
.driver_data = (unsigned long) &at91sam9260_config,
|
|
|
|
}, {
|
|
|
|
.name = "i2c-at91sam9g20",
|
|
|
|
.driver_data = (unsigned long) &at91sam9g20_config,
|
|
|
|
}, {
|
|
|
|
.name = "i2c-at91sam9g10",
|
|
|
|
.driver_data = (unsigned long) &at91sam9g10_config,
|
|
|
|
}, {
|
|
|
|
/* sentinel */
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2012-09-12 08:42:14 +02:00
|
|
|
#if defined(CONFIG_OF)
|
2013-02-09 19:14:00 +01:00
|
|
|
static struct at91_twi_pdata at91sam9x5_config = {
|
|
|
|
.clk_max_div = 7,
|
|
|
|
.clk_offset = 4,
|
|
|
|
.has_unre_flag = false,
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
.has_alt_cmd = false,
|
2015-12-03 10:53:50 +01:00
|
|
|
.has_hold_field = false,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct at91_twi_pdata sama5d4_config = {
|
|
|
|
.clk_max_div = 7,
|
|
|
|
.clk_offset = 4,
|
|
|
|
.has_unre_flag = false,
|
|
|
|
.has_alt_cmd = false,
|
|
|
|
.has_hold_field = true,
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct at91_twi_pdata sama5d2_config = {
|
|
|
|
.clk_max_div = 7,
|
|
|
|
.clk_offset = 4,
|
|
|
|
.has_unre_flag = true,
|
|
|
|
.has_alt_cmd = true,
|
2015-12-03 10:53:50 +01:00
|
|
|
.has_hold_field = true,
|
2013-02-09 19:14:00 +01:00
|
|
|
};
|
|
|
|
|
2012-09-12 08:42:14 +02:00
|
|
|
static const struct of_device_id atmel_twi_dt_ids[] = {
|
|
|
|
{
|
2012-12-05 22:42:12 +01:00
|
|
|
.compatible = "atmel,at91rm9200-i2c",
|
|
|
|
.data = &at91rm9200_config,
|
|
|
|
} , {
|
2012-09-12 08:42:14 +02:00
|
|
|
.compatible = "atmel,at91sam9260-i2c",
|
|
|
|
.data = &at91sam9260_config,
|
2014-01-15 14:17:13 +01:00
|
|
|
} , {
|
|
|
|
.compatible = "atmel,at91sam9261-i2c",
|
|
|
|
.data = &at91sam9261_config,
|
2012-09-12 08:42:14 +02:00
|
|
|
} , {
|
|
|
|
.compatible = "atmel,at91sam9g20-i2c",
|
|
|
|
.data = &at91sam9g20_config,
|
|
|
|
} , {
|
|
|
|
.compatible = "atmel,at91sam9g10-i2c",
|
|
|
|
.data = &at91sam9g10_config,
|
|
|
|
}, {
|
|
|
|
.compatible = "atmel,at91sam9x5-i2c",
|
|
|
|
.data = &at91sam9x5_config,
|
2015-12-03 10:53:50 +01:00
|
|
|
}, {
|
|
|
|
.compatible = "atmel,sama5d4-i2c",
|
|
|
|
.data = &sama5d4_config,
|
i2c: at91: add support for new alternative command mode
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.
Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.
In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.
Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.
For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-09 18:22:17 +02:00
|
|
|
}, {
|
|
|
|
.compatible = "atmel,sama5d2-i2c",
|
|
|
|
.data = &sama5d2_config,
|
2012-09-12 08:42:14 +02:00
|
|
|
}, {
|
|
|
|
/* sentinel */
|
|
|
|
}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
|
|
|
|
#endif
|
|
|
|
|
2012-11-27 21:59:38 +01:00
|
|
|
static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
|
2012-11-23 10:09:04 +01:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
struct dma_slave_config slave_config;
|
|
|
|
struct at91_twi_dma *dma = &dev->dma;
|
2015-06-09 18:22:19 +02:00
|
|
|
enum dma_slave_buswidth addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The actual width of the access will be chosen in
|
|
|
|
* dmaengine_prep_slave_sg():
|
|
|
|
* for each buffer in the scatter-gather list, if its size is aligned
|
|
|
|
* to addr_width then addr_width accesses will be performed to transfer
|
|
|
|
* the buffer. On the other hand, if the buffer size is not aligned to
|
|
|
|
* addr_width then the buffer is transferred using single byte accesses.
|
|
|
|
* Please refer to the Atmel eXtended DMA controller driver.
|
|
|
|
* When FIFOs are used, the TXRDYM threshold can always be set to
|
|
|
|
* trigger the XDMAC when at least 4 data can be written into the TX
|
|
|
|
* FIFO, even if single byte accesses are performed.
|
|
|
|
* However the RXRDYM threshold must be set to fit the access width,
|
|
|
|
* deduced from buffer length, so the XDMAC is triggered properly to
|
|
|
|
* read data from the RX FIFO.
|
|
|
|
*/
|
|
|
|
if (dev->fifo_size)
|
|
|
|
addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
2012-11-23 10:09:04 +01:00
|
|
|
|
|
|
|
memset(&slave_config, 0, sizeof(slave_config));
|
|
|
|
slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
|
2015-06-09 18:22:19 +02:00
|
|
|
slave_config.src_addr_width = addr_width;
|
2012-11-23 10:09:04 +01:00
|
|
|
slave_config.src_maxburst = 1;
|
|
|
|
slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
|
2015-06-09 18:22:19 +02:00
|
|
|
slave_config.dst_addr_width = addr_width;
|
2012-11-23 10:09:04 +01:00
|
|
|
slave_config.dst_maxburst = 1;
|
|
|
|
slave_config.device_fc = false;
|
|
|
|
|
2014-11-21 14:44:32 +01:00
|
|
|
dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx");
|
|
|
|
if (IS_ERR(dma->chan_tx)) {
|
|
|
|
ret = PTR_ERR(dma->chan_tx);
|
|
|
|
dma->chan_tx = NULL;
|
2013-04-15 04:16:56 +02:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2014-11-21 14:44:32 +01:00
|
|
|
dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx");
|
|
|
|
if (IS_ERR(dma->chan_rx)) {
|
|
|
|
ret = PTR_ERR(dma->chan_rx);
|
|
|
|
dma->chan_rx = NULL;
|
2012-11-23 10:09:04 +01:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
slave_config.direction = DMA_MEM_TO_DEV;
|
|
|
|
if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
|
|
|
|
dev_err(dev->dev, "failed to configure tx channel\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
slave_config.direction = DMA_DEV_TO_MEM;
|
|
|
|
if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
|
|
|
|
dev_err(dev->dev, "failed to configure rx channel\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2015-06-09 18:22:19 +02:00
|
|
|
sg_init_table(dma->sg, 2);
|
2012-11-23 10:09:04 +01:00
|
|
|
dma->buf_mapped = false;
|
|
|
|
dma->xfer_in_progress = false;
|
2014-11-21 14:44:32 +01:00
|
|
|
dev->use_dma = true;
|
2012-11-23 10:09:04 +01:00
|
|
|
|
|
|
|
dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
|
|
|
|
dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
error:
|
2014-11-21 14:44:32 +01:00
|
|
|
if (ret != -EPROBE_DEFER)
|
2016-05-20 14:06:31 +02:00
|
|
|
dev_info(dev->dev, "can't get DMA channel, continue without DMA support\n");
|
2012-11-23 10:09:04 +01:00
|
|
|
if (dma->chan_rx)
|
|
|
|
dma_release_channel(dma->chan_rx);
|
|
|
|
if (dma->chan_tx)
|
|
|
|
dma_release_channel(dma->chan_tx);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-27 21:59:38 +01:00
|
|
|
static struct at91_twi_pdata *at91_twi_get_driver_data(
|
2012-09-12 08:42:14 +02:00
|
|
|
struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
if (pdev->dev.of_node) {
|
|
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
|
|
|
|
if (!match)
|
|
|
|
return NULL;
|
2012-11-23 17:03:16 +01:00
|
|
|
return (struct at91_twi_pdata *)match->data;
|
2012-09-12 08:42:14 +02:00
|
|
|
}
|
|
|
|
return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
|
|
|
|
}
|
|
|
|
|
2012-11-27 21:59:38 +01:00
|
|
|
static int at91_twi_probe(struct platform_device *pdev)
|
2011-11-08 11:49:46 +01:00
|
|
|
{
|
|
|
|
struct at91_twi_dev *dev;
|
|
|
|
struct resource *mem;
|
|
|
|
int rc;
|
2012-11-23 10:09:04 +01:00
|
|
|
u32 phy_addr;
|
2014-03-11 05:25:38 +01:00
|
|
|
u32 bus_clk_rate;
|
2011-11-08 11:49:46 +01:00
|
|
|
|
|
|
|
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
|
|
|
|
if (!dev)
|
|
|
|
return -ENOMEM;
|
|
|
|
init_completion(&dev->cmd_complete);
|
|
|
|
dev->dev = &pdev->dev;
|
|
|
|
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!mem)
|
|
|
|
return -ENODEV;
|
2012-11-23 10:09:04 +01:00
|
|
|
phy_addr = mem->start;
|
2011-11-08 11:49:46 +01:00
|
|
|
|
|
|
|
dev->pdata = at91_twi_get_driver_data(pdev);
|
|
|
|
if (!dev->pdata)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2013-01-21 11:09:03 +01:00
|
|
|
dev->base = devm_ioremap_resource(&pdev->dev, mem);
|
|
|
|
if (IS_ERR(dev->base))
|
|
|
|
return PTR_ERR(dev->base);
|
2011-11-08 11:49:46 +01:00
|
|
|
|
|
|
|
dev->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (dev->irq < 0)
|
|
|
|
return dev->irq;
|
|
|
|
|
|
|
|
rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
|
|
|
|
dev_name(dev->dev), dev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
|
|
|
|
dev->clk = devm_clk_get(dev->dev, NULL);
|
|
|
|
if (IS_ERR(dev->clk)) {
|
|
|
|
dev_err(dev->dev, "no clock defined\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2017-05-31 08:57:44 +02:00
|
|
|
rc = clk_prepare_enable(dev->clk);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2011-11-08 11:49:46 +01:00
|
|
|
|
2014-11-21 14:44:31 +01:00
|
|
|
if (dev->dev->of_node) {
|
2014-11-21 14:44:32 +01:00
|
|
|
rc = at91_twi_configure_dma(dev, phy_addr);
|
2017-05-31 08:57:44 +02:00
|
|
|
if (rc == -EPROBE_DEFER) {
|
|
|
|
clk_disable_unprepare(dev->clk);
|
2014-11-21 14:44:32 +01:00
|
|
|
return rc;
|
2017-05-31 08:57:44 +02:00
|
|
|
}
|
2012-11-23 10:09:04 +01:00
|
|
|
}
|
|
|
|
|
2015-06-09 18:22:19 +02:00
|
|
|
if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
|
|
|
|
&dev->fifo_size)) {
|
|
|
|
dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size);
|
|
|
|
}
|
|
|
|
|
2014-03-11 05:25:38 +01:00
|
|
|
rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
|
|
|
|
&bus_clk_rate);
|
|
|
|
if (rc)
|
|
|
|
bus_clk_rate = DEFAULT_TWI_CLK_HZ;
|
|
|
|
|
|
|
|
at91_calc_twi_clock(dev, bus_clk_rate);
|
2011-11-08 11:49:46 +01:00
|
|
|
at91_init_twi_bus(dev);
|
|
|
|
|
|
|
|
snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
|
|
|
|
i2c_set_adapdata(&dev->adapter, dev);
|
|
|
|
dev->adapter.owner = THIS_MODULE;
|
2014-07-10 13:46:22 +02:00
|
|
|
dev->adapter.class = I2C_CLASS_DEPRECATED;
|
2011-11-08 11:49:46 +01:00
|
|
|
dev->adapter.algo = &at91_twi_algorithm;
|
2015-01-07 12:24:10 +01:00
|
|
|
dev->adapter.quirks = &at91_twi_quirks;
|
2011-11-08 11:49:46 +01:00
|
|
|
dev->adapter.dev.parent = dev->dev;
|
|
|
|
dev->adapter.nr = pdev->id;
|
|
|
|
dev->adapter.timeout = AT91_I2C_TIMEOUT;
|
2012-09-12 08:42:14 +02:00
|
|
|
dev->adapter.dev.of_node = pdev->dev.of_node;
|
2011-11-08 11:49:46 +01:00
|
|
|
|
2014-10-24 08:50:15 +02:00
|
|
|
pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
|
|
|
|
pm_runtime_use_autosuspend(dev->dev);
|
|
|
|
pm_runtime_set_active(dev->dev);
|
|
|
|
pm_runtime_enable(dev->dev);
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
rc = i2c_add_numbered_adapter(&dev->adapter);
|
|
|
|
if (rc) {
|
|
|
|
clk_disable_unprepare(dev->clk);
|
2014-10-24 08:50:15 +02:00
|
|
|
|
|
|
|
pm_runtime_disable(dev->dev);
|
|
|
|
pm_runtime_set_suspended(dev->dev);
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2015-06-09 18:22:18 +02:00
|
|
|
dev_info(dev->dev, "AT91 i2c bus driver (hw version: %#x).\n",
|
|
|
|
at91_twi_read(dev, AT91_TWI_VER));
|
2011-11-08 11:49:46 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-27 21:59:38 +01:00
|
|
|
static int at91_twi_remove(struct platform_device *pdev)
|
2011-11-08 11:49:46 +01:00
|
|
|
{
|
|
|
|
struct at91_twi_dev *dev = platform_get_drvdata(pdev);
|
|
|
|
|
2013-03-09 09:16:46 +01:00
|
|
|
i2c_del_adapter(&dev->adapter);
|
2011-11-08 11:49:46 +01:00
|
|
|
clk_disable_unprepare(dev->clk);
|
|
|
|
|
2014-10-24 08:50:15 +02:00
|
|
|
pm_runtime_disable(dev->dev);
|
|
|
|
pm_runtime_set_suspended(dev->dev);
|
|
|
|
|
2013-03-09 09:16:46 +01:00
|
|
|
return 0;
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
|
|
|
|
static int at91_twi_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
|
|
|
|
|
2014-10-24 08:50:15 +02:00
|
|
|
clk_disable_unprepare(twi_dev->clk);
|
2011-11-08 11:49:46 +01:00
|
|
|
|
2014-11-10 02:55:52 +01:00
|
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int at91_twi_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
|
|
|
|
|
2014-11-10 02:55:52 +01:00
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
|
2014-10-24 08:50:15 +02:00
|
|
|
return clk_prepare_enable(twi_dev->clk);
|
2011-11-08 11:49:46 +01:00
|
|
|
}
|
|
|
|
|
2014-10-24 08:50:16 +02:00
|
|
|
static int at91_twi_suspend_noirq(struct device *dev)
|
|
|
|
{
|
|
|
|
if (!pm_runtime_status_suspended(dev))
|
|
|
|
at91_twi_runtime_suspend(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int at91_twi_resume_noirq(struct device *dev)
|
|
|
|
{
|
2017-02-16 18:27:59 +01:00
|
|
|
struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
|
2014-10-24 08:50:16 +02:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!pm_runtime_status_suspended(dev)) {
|
|
|
|
ret = at91_twi_runtime_resume(dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
|
|
pm_request_autosuspend(dev);
|
|
|
|
|
2017-02-16 18:27:59 +01:00
|
|
|
at91_init_twi_bus(twi_dev);
|
|
|
|
|
2014-10-24 08:50:16 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-11-08 11:49:46 +01:00
|
|
|
static const struct dev_pm_ops at91_twi_pm = {
|
2014-10-24 08:50:16 +02:00
|
|
|
.suspend_noirq = at91_twi_suspend_noirq,
|
|
|
|
.resume_noirq = at91_twi_resume_noirq,
|
2011-11-08 11:49:46 +01:00
|
|
|
.runtime_suspend = at91_twi_runtime_suspend,
|
|
|
|
.runtime_resume = at91_twi_runtime_resume,
|
|
|
|
};
|
|
|
|
|
|
|
|
#define at91_twi_pm_ops (&at91_twi_pm)
|
|
|
|
#else
|
|
|
|
#define at91_twi_pm_ops NULL
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static struct platform_driver at91_twi_driver = {
|
|
|
|
.probe = at91_twi_probe,
|
2012-11-27 21:59:38 +01:00
|
|
|
.remove = at91_twi_remove,
|
2011-11-08 11:49:46 +01:00
|
|
|
.id_table = at91_twi_devtypes,
|
|
|
|
.driver = {
|
|
|
|
.name = "at91_i2c",
|
2013-03-14 01:13:03 +01:00
|
|
|
.of_match_table = of_match_ptr(atmel_twi_dt_ids),
|
2011-11-08 11:49:46 +01:00
|
|
|
.pm = at91_twi_pm_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init at91_twi_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&at91_twi_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit at91_twi_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&at91_twi_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
subsys_initcall(at91_twi_init);
|
|
|
|
module_exit(at91_twi_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
|
|
|
|
MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_ALIAS("platform:at91_i2c");
|