2005-04-17 00:20:36 +02:00
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/*
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Copyright (c) 2002,2003 Alexander Malysh <amalysh@web.de>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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*/
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/*
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Status: beta
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Supports:
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SIS 630
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SIS 730
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2013-01-28 22:21:05 +01:00
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SIS 964
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Notable differences between chips:
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+------------------------+--------------------+-------------------+
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| | SIS630/730 | SIS964 |
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+------------------------+--------------------+-------------------+
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| Clock | 14kHz/56kHz | 55.56kHz/27.78kHz |
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| SMBus registers offset | 0x80 | 0xE0 |
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| SMB_CNT | Bit 1 = Slave Busy | Bit 1 = Bus probe |
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| (not used yet) | Bit 3 is reserved | Bit 3 = Last byte |
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| SMB_PCOUNT | Offset + 0x06 | Offset + 0x14 |
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| SMB_COUNT | 4:0 bits | 5:0 bits |
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+------------------------+--------------------+-------------------+
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(Other differences don't affect the functions provided by the driver)
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2005-04-17 00:20:36 +02:00
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Note: we assume there can only be one device, with one SMBus interface.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/i2c.h>
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2008-07-14 22:38:33 +02:00
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#include <linux/acpi.h>
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2010-05-21 18:41:01 +02:00
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#include <linux/io.h>
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2005-04-17 00:20:36 +02:00
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2013-01-28 22:21:05 +01:00
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/* SIS964 id is defined here as we are the only file using it */
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#define PCI_DEVICE_ID_SI_964 0x0964
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/* SIS630/730/964 SMBus registers */
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#define SMB_STS 0x00 /* status */
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#define SMB_CNT 0x02 /* control */
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#define SMBHOST_CNT 0x03 /* host control */
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#define SMB_ADDR 0x04 /* address */
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#define SMB_CMD 0x05 /* command */
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#define SMB_COUNT 0x07 /* byte count */
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#define SMB_BYTE 0x08 /* ~0x8F data byte field */
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2013-01-28 22:21:08 +01:00
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/* SMB_STS register */
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#define BYTE_DONE_STS 0x10 /* Byte Done Status / Block Array */
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#define SMBCOL_STS 0x04 /* Collision */
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#define SMBERR_STS 0x02 /* Device error */
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/* SMB_CNT register */
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#define MSTO_EN 0x40 /* Host Master Timeout Enable */
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#define SMBCLK_SEL 0x20 /* Host master clock selection */
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#define SMB_PROBE 0x02 /* Bus Probe/Slave busy */
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#define SMB_HOSTBUSY 0x01 /* Host Busy */
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/* SMBHOST_CNT register */
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#define SMB_KILL 0x20 /* Kill */
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#define SMB_START 0x10 /* Start */
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2013-01-28 22:21:05 +01:00
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/* register count for request_region
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* As we don't use SMB_PCOUNT, 20 is ok for SiS630 and SiS964
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*/
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2005-04-17 00:20:36 +02:00
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#define SIS630_SMB_IOREGION 20
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/* PCI address constants */
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/* acpi base address register */
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#define SIS630_ACPI_BASE_REG 0x74
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/* bios control register */
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#define SIS630_BIOS_CTL_REG 0x40
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/* Other settings */
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#define MAX_TIMEOUT 500
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/* SIS630 constants */
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#define SIS630_QUICK 0x00
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#define SIS630_BYTE 0x01
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#define SIS630_BYTE_DATA 0x02
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#define SIS630_WORD_DATA 0x03
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#define SIS630_PCALL 0x04
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#define SIS630_BLOCK_DATA 0x05
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2005-09-25 16:37:04 +02:00
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static struct pci_driver sis630_driver;
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2005-04-17 00:20:36 +02:00
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/* insmod parameters */
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2012-01-13 00:02:20 +01:00
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static bool high_clock;
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static bool force;
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2005-04-17 00:20:36 +02:00
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module_param(high_clock, bool, 0);
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2013-01-28 22:21:05 +01:00
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MODULE_PARM_DESC(high_clock,
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"Set Host Master Clock to 56KHz (default 14KHz) (SIS630/730 only).");
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2005-04-17 00:20:36 +02:00
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module_param(force, bool, 0);
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MODULE_PARM_DESC(force, "Forcibly enable the SIS630. DANGEROUS!");
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2013-01-28 22:21:05 +01:00
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/* SMBus base adress */
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static unsigned short smbus_base;
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2005-04-17 00:20:36 +02:00
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/* supported chips */
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static int supported[] = {
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PCI_DEVICE_ID_SI_630,
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PCI_DEVICE_ID_SI_730,
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2013-01-28 22:21:05 +01:00
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PCI_DEVICE_ID_SI_760,
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2005-04-17 00:20:36 +02:00
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0 /* terminates the list */
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};
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static inline u8 sis630_read(u8 reg)
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{
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2013-01-28 22:21:05 +01:00
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return inb(smbus_base + reg);
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2005-04-17 00:20:36 +02:00
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}
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static inline void sis630_write(u8 reg, u8 data)
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{
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2013-01-28 22:21:05 +01:00
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outb(data, smbus_base + reg);
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2005-04-17 00:20:36 +02:00
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}
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2013-01-29 21:22:26 +01:00
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static int sis630_transaction_start(struct i2c_adapter *adap, int size,
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u8 *oldclock)
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2005-04-17 00:20:36 +02:00
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{
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2013-01-29 21:22:26 +01:00
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int temp;
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2005-04-17 00:20:36 +02:00
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/* Make sure the SMBus host is ready to start transmitting. */
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2013-01-28 22:21:08 +01:00
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temp = sis630_read(SMB_CNT);
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if ((temp & (SMB_PROBE | SMB_HOSTBUSY)) != 0x00) {
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dev_dbg(&adap->dev, "SMBus busy (%02x). Resetting...\n", temp);
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2005-04-17 00:20:36 +02:00
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/* kill smbus transaction */
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2013-01-28 22:21:08 +01:00
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sis630_write(SMBHOST_CNT, SMB_KILL);
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2005-04-17 00:20:36 +02:00
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2013-01-28 22:21:08 +01:00
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temp = sis630_read(SMB_CNT);
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if (temp & (SMB_PROBE | SMB_HOSTBUSY)) {
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2005-04-17 00:20:36 +02:00
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dev_dbg(&adap->dev, "Failed! (%02x)\n", temp);
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2008-07-14 22:38:25 +02:00
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return -EBUSY;
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2013-01-29 21:22:26 +01:00
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} else {
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2008-04-29 23:11:37 +02:00
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dev_dbg(&adap->dev, "Successful!\n");
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2005-04-17 00:20:36 +02:00
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}
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2013-01-29 21:22:26 +01:00
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}
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2005-04-17 00:20:36 +02:00
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/* save old clock, so we can prevent machine for hung */
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*oldclock = sis630_read(SMB_CNT);
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dev_dbg(&adap->dev, "saved clock 0x%02x\n", *oldclock);
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2013-01-29 21:22:26 +01:00
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/* disable timeout interrupt,
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* set Host Master Clock to 56KHz if requested */
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2005-04-17 00:20:36 +02:00
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if (high_clock)
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2013-01-28 22:21:08 +01:00
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sis630_write(SMB_CNT, SMBCLK_SEL);
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2005-04-17 00:20:36 +02:00
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else
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2013-01-28 22:21:08 +01:00
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sis630_write(SMB_CNT, (*oldclock & ~MSTO_EN));
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2005-04-17 00:20:36 +02:00
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/* clear all sticky bits */
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temp = sis630_read(SMB_STS);
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sis630_write(SMB_STS, temp & 0x1e);
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/* start the transaction by setting bit 4 and size */
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2013-01-28 22:21:08 +01:00
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sis630_write(SMBHOST_CNT, SMB_START | (size & 0x07));
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2005-04-17 00:20:36 +02:00
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return 0;
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}
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static int sis630_transaction_wait(struct i2c_adapter *adap, int size)
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{
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int temp, result = 0, timeout = 0;
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/* We will always wait for a fraction of a second! */
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do {
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msleep(1);
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temp = sis630_read(SMB_STS);
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/* check if block transmitted */
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2013-01-28 22:21:08 +01:00
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if (size == SIS630_BLOCK_DATA && (temp & BYTE_DONE_STS))
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2005-04-17 00:20:36 +02:00
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break;
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} while (!(temp & 0x0e) && (timeout++ < MAX_TIMEOUT));
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/* If the SMBus is still busy, we give up */
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2009-05-05 08:39:24 +02:00
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if (timeout > MAX_TIMEOUT) {
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2005-04-17 00:20:36 +02:00
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dev_dbg(&adap->dev, "SMBus Timeout!\n");
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2008-07-14 22:38:25 +02:00
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result = -ETIMEDOUT;
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2005-04-17 00:20:36 +02:00
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}
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2013-01-28 22:21:08 +01:00
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if (temp & SMBERR_STS) {
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2005-04-17 00:20:36 +02:00
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dev_dbg(&adap->dev, "Error: Failed bus transaction\n");
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2008-07-14 22:38:25 +02:00
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result = -ENXIO;
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2005-04-17 00:20:36 +02:00
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}
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2013-01-28 22:21:08 +01:00
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if (temp & SMBCOL_STS) {
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2005-04-17 00:20:36 +02:00
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dev_err(&adap->dev, "Bus collision!\n");
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2013-01-28 22:21:07 +01:00
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result = -EAGAIN;
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2005-04-17 00:20:36 +02:00
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}
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return result;
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}
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static void sis630_transaction_end(struct i2c_adapter *adap, u8 oldclock)
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{
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/* clear all status "sticky" bits */
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2013-01-28 22:21:06 +01:00
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sis630_write(SMB_STS, 0xFF);
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2005-04-17 00:20:36 +02:00
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2013-01-29 21:22:26 +01:00
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dev_dbg(&adap->dev,
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"SMB_CNT before clock restore 0x%02x\n", sis630_read(SMB_CNT));
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2005-04-17 00:20:36 +02:00
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/*
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* restore old Host Master Clock if high_clock is set
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* and oldclock was not 56KHz
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*/
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2013-01-28 22:21:08 +01:00
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if (high_clock && !(oldclock & SMBCLK_SEL))
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sis630_write(SMB_CNT, sis630_read(SMB_CNT) & ~SMBCLK_SEL);
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2005-04-17 00:20:36 +02:00
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2013-01-29 21:22:26 +01:00
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dev_dbg(&adap->dev,
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"SMB_CNT after clock restore 0x%02x\n", sis630_read(SMB_CNT));
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2005-04-17 00:20:36 +02:00
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}
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static int sis630_transaction(struct i2c_adapter *adap, int size)
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{
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int result = 0;
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u8 oldclock = 0;
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result = sis630_transaction_start(adap, size, &oldclock);
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if (!result) {
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result = sis630_transaction_wait(adap, size);
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sis630_transaction_end(adap, oldclock);
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}
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return result;
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}
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2013-01-29 21:22:26 +01:00
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static int sis630_block_data(struct i2c_adapter *adap,
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union i2c_smbus_data *data, int read_write)
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2005-04-17 00:20:36 +02:00
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{
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int i, len = 0, rc = 0;
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u8 oldclock = 0;
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if (read_write == I2C_SMBUS_WRITE) {
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len = data->block[0];
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if (len < 0)
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len = 0;
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else if (len > 32)
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len = 32;
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sis630_write(SMB_COUNT, len);
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2013-01-29 21:22:26 +01:00
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for (i = 1; i <= len; i++) {
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dev_dbg(&adap->dev,
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"set data 0x%02x\n", data->block[i]);
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2005-04-17 00:20:36 +02:00
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/* set data */
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2013-01-29 21:22:26 +01:00
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sis630_write(SMB_BYTE + (i - 1) % 8, data->block[i]);
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if (i == 8 || (len < 8 && i == len)) {
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dev_dbg(&adap->dev,
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"start trans len=%d i=%d\n", len, i);
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2005-04-17 00:20:36 +02:00
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/* first transaction */
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2008-07-14 22:38:25 +02:00
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rc = sis630_transaction_start(adap,
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SIS630_BLOCK_DATA, &oldclock);
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if (rc)
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return rc;
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2013-01-29 21:22:26 +01:00
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} else if ((i - 1) % 8 == 7 || i == len) {
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dev_dbg(&adap->dev,
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"trans_wait len=%d i=%d\n", len, i);
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if (i > 8) {
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dev_dbg(&adap->dev,
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"clear smbary_sts"
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" len=%d i=%d\n", len, i);
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2005-04-17 00:20:36 +02:00
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/*
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If this is not first transaction,
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we must clear sticky bit.
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clear SMBARY_STS
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*/
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2013-01-28 22:21:08 +01:00
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sis630_write(SMB_STS, BYTE_DONE_STS);
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2005-04-17 00:20:36 +02:00
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}
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2008-07-14 22:38:25 +02:00
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rc = sis630_transaction_wait(adap,
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SIS630_BLOCK_DATA);
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if (rc) {
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2013-01-29 21:22:26 +01:00
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dev_dbg(&adap->dev,
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"trans_wait failed\n");
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2005-04-17 00:20:36 +02:00
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break;
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}
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}
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}
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2013-01-29 21:22:26 +01:00
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} else {
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2005-04-17 00:20:36 +02:00
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/* read request */
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data->block[0] = len = 0;
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2008-07-14 22:38:25 +02:00
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rc = sis630_transaction_start(adap,
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SIS630_BLOCK_DATA, &oldclock);
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if (rc)
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return rc;
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2005-04-17 00:20:36 +02:00
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do {
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2008-07-14 22:38:25 +02:00
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rc = sis630_transaction_wait(adap, SIS630_BLOCK_DATA);
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if (rc) {
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2005-04-17 00:20:36 +02:00
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dev_dbg(&adap->dev, "trans_wait failed\n");
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break;
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}
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/* if this first transaction then read byte count */
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if (len == 0)
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data->block[0] = sis630_read(SMB_COUNT);
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/* just to be sure */
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if (data->block[0] > 32)
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data->block[0] = 32;
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|
|
2013-01-29 21:22:26 +01:00
|
|
|
dev_dbg(&adap->dev,
|
|
|
|
"block data read len=0x%x\n", data->block[0]);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2013-01-29 21:22:26 +01:00
|
|
|
for (i = 0; i < 8 && len < data->block[0]; i++, len++) {
|
|
|
|
dev_dbg(&adap->dev,
|
|
|
|
"read i=%d len=%d\n", i, len);
|
|
|
|
data->block[len + 1] = sis630_read(SMB_BYTE +
|
|
|
|
i);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2013-01-29 21:22:26 +01:00
|
|
|
dev_dbg(&adap->dev,
|
|
|
|
"clear smbary_sts len=%d i=%d\n", len, i);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* clear SMBARY_STS */
|
2013-01-28 22:21:08 +01:00
|
|
|
sis630_write(SMB_STS, BYTE_DONE_STS);
|
2013-01-29 21:22:26 +01:00
|
|
|
} while (len < data->block[0]);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
sis630_transaction_end(adap, oldclock);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2008-07-14 22:38:25 +02:00
|
|
|
/* Return negative errno on error. */
|
2005-04-17 00:20:36 +02:00
|
|
|
static s32 sis630_access(struct i2c_adapter *adap, u16 addr,
|
|
|
|
unsigned short flags, char read_write,
|
|
|
|
u8 command, int size, union i2c_smbus_data *data)
|
|
|
|
{
|
2008-07-14 22:38:25 +02:00
|
|
|
int status;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
switch (size) {
|
2013-01-29 21:22:26 +01:00
|
|
|
case I2C_SMBUS_QUICK:
|
|
|
|
sis630_write(SMB_ADDR,
|
|
|
|
((addr & 0x7f) << 1) | (read_write & 0x01));
|
|
|
|
size = SIS630_QUICK;
|
|
|
|
break;
|
|
|
|
case I2C_SMBUS_BYTE:
|
|
|
|
sis630_write(SMB_ADDR,
|
|
|
|
((addr & 0x7f) << 1) | (read_write & 0x01));
|
|
|
|
if (read_write == I2C_SMBUS_WRITE)
|
2005-04-17 00:20:36 +02:00
|
|
|
sis630_write(SMB_CMD, command);
|
2013-01-29 21:22:26 +01:00
|
|
|
size = SIS630_BYTE;
|
|
|
|
break;
|
|
|
|
case I2C_SMBUS_BYTE_DATA:
|
|
|
|
sis630_write(SMB_ADDR,
|
|
|
|
((addr & 0x7f) << 1) | (read_write & 0x01));
|
|
|
|
sis630_write(SMB_CMD, command);
|
|
|
|
if (read_write == I2C_SMBUS_WRITE)
|
|
|
|
sis630_write(SMB_BYTE, data->byte);
|
|
|
|
size = SIS630_BYTE_DATA;
|
|
|
|
break;
|
|
|
|
case I2C_SMBUS_PROC_CALL:
|
|
|
|
case I2C_SMBUS_WORD_DATA:
|
|
|
|
sis630_write(SMB_ADDR,
|
|
|
|
((addr & 0x7f) << 1) | (read_write & 0x01));
|
|
|
|
sis630_write(SMB_CMD, command);
|
|
|
|
if (read_write == I2C_SMBUS_WRITE) {
|
|
|
|
sis630_write(SMB_BYTE, data->word & 0xff);
|
|
|
|
sis630_write(SMB_BYTE + 1, (data->word & 0xff00) >> 8);
|
|
|
|
}
|
|
|
|
size = (size == I2C_SMBUS_PROC_CALL ?
|
|
|
|
SIS630_PCALL : SIS630_WORD_DATA);
|
|
|
|
break;
|
|
|
|
case I2C_SMBUS_BLOCK_DATA:
|
|
|
|
sis630_write(SMB_ADDR,
|
|
|
|
((addr & 0x7f) << 1) | (read_write & 0x01));
|
|
|
|
sis630_write(SMB_CMD, command);
|
|
|
|
size = SIS630_BLOCK_DATA;
|
|
|
|
return sis630_block_data(adap, data, read_write);
|
|
|
|
default:
|
|
|
|
dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
|
|
|
|
return -EOPNOTSUPP;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2008-07-14 22:38:25 +02:00
|
|
|
status = sis630_transaction(adap, size);
|
|
|
|
if (status)
|
|
|
|
return status;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
if ((size != SIS630_PCALL) &&
|
|
|
|
((read_write == I2C_SMBUS_WRITE) || (size == SIS630_QUICK))) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-01-29 21:22:26 +01:00
|
|
|
switch (size) {
|
|
|
|
case SIS630_BYTE:
|
|
|
|
case SIS630_BYTE_DATA:
|
|
|
|
data->byte = sis630_read(SMB_BYTE);
|
|
|
|
break;
|
|
|
|
case SIS630_PCALL:
|
|
|
|
case SIS630_WORD_DATA:
|
|
|
|
data->word = sis630_read(SMB_BYTE) +
|
|
|
|
(sis630_read(SMB_BYTE + 1) << 8);
|
|
|
|
break;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 sis630_func(struct i2c_adapter *adapter)
|
|
|
|
{
|
2013-01-29 21:22:26 +01:00
|
|
|
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
|
|
|
|
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
|
|
|
|
I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_DATA;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2012-11-27 21:59:38 +01:00
|
|
|
static int sis630_setup(struct pci_dev *sis630_dev)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
unsigned char b;
|
|
|
|
struct pci_dev *dummy = NULL;
|
2012-01-12 20:32:03 +01:00
|
|
|
int retval, i;
|
2013-01-28 22:21:05 +01:00
|
|
|
/* acpi base address */
|
|
|
|
unsigned short acpi_base;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* check for supported SiS devices */
|
2013-01-29 21:22:26 +01:00
|
|
|
for (i = 0; supported[i] > 0; i++) {
|
|
|
|
dummy = pci_get_device(PCI_VENDOR_ID_SI, supported[i], dummy);
|
|
|
|
if (dummy)
|
2005-04-17 00:20:36 +02:00
|
|
|
break; /* found */
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dummy) {
|
|
|
|
pci_dev_put(dummy);
|
2013-01-29 21:22:26 +01:00
|
|
|
} else if (force) {
|
|
|
|
dev_err(&sis630_dev->dev,
|
|
|
|
"WARNING: Can't detect SIS630 compatible device, but "
|
2005-04-17 00:20:36 +02:00
|
|
|
"loading because of force option enabled\n");
|
2013-01-29 21:22:26 +01:00
|
|
|
} else {
|
2005-04-17 00:20:36 +02:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
Enable ACPI first , so we can accsess reg 74-75
|
|
|
|
in acpi io space and read acpi base addr
|
|
|
|
*/
|
2013-01-29 21:22:26 +01:00
|
|
|
if (pci_read_config_byte(sis630_dev, SIS630_BIOS_CTL_REG, &b)) {
|
2005-04-17 00:20:36 +02:00
|
|
|
dev_err(&sis630_dev->dev, "Error: Can't read bios ctl reg\n");
|
2012-01-12 20:32:03 +01:00
|
|
|
retval = -ENODEV;
|
2005-04-17 00:20:36 +02:00
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
/* if ACPI already enabled , do nothing */
|
|
|
|
if (!(b & 0x80) &&
|
|
|
|
pci_write_config_byte(sis630_dev, SIS630_BIOS_CTL_REG, b | 0x80)) {
|
|
|
|
dev_err(&sis630_dev->dev, "Error: Can't enable ACPI\n");
|
2012-01-12 20:32:03 +01:00
|
|
|
retval = -ENODEV;
|
2005-04-17 00:20:36 +02:00
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Determine the ACPI base address */
|
2013-01-29 21:22:26 +01:00
|
|
|
if (pci_read_config_word(sis630_dev,
|
|
|
|
SIS630_ACPI_BASE_REG, &acpi_base)) {
|
|
|
|
dev_err(&sis630_dev->dev,
|
|
|
|
"Error: Can't determine ACPI base address\n");
|
2012-01-12 20:32:03 +01:00
|
|
|
retval = -ENODEV;
|
2005-04-17 00:20:36 +02:00
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
2013-01-28 22:21:09 +01:00
|
|
|
dev_dbg(&sis630_dev->dev, "ACPI base at 0x%04hx\n", acpi_base);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2013-01-28 22:21:05 +01:00
|
|
|
if (supported[i] == PCI_DEVICE_ID_SI_760)
|
|
|
|
smbus_base = acpi_base + 0xE0;
|
|
|
|
else
|
|
|
|
smbus_base = acpi_base + 0x80;
|
|
|
|
|
|
|
|
dev_dbg(&sis630_dev->dev, "SMBus base at 0x%04hx\n", smbus_base);
|
|
|
|
|
|
|
|
retval = acpi_check_region(smbus_base + SMB_STS, SIS630_SMB_IOREGION,
|
2008-07-14 22:38:33 +02:00
|
|
|
sis630_driver.name);
|
|
|
|
if (retval)
|
|
|
|
goto exit;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/* Everything is happy, let's grab the memory and set things up. */
|
2013-01-28 22:21:05 +01:00
|
|
|
if (!request_region(smbus_base + SMB_STS, SIS630_SMB_IOREGION,
|
2005-09-25 16:37:04 +02:00
|
|
|
sis630_driver.name)) {
|
2013-01-28 22:21:05 +01:00
|
|
|
dev_err(&sis630_dev->dev,
|
|
|
|
"I/O Region 0x%04hx-0x%04hx for SMBus already in use.\n",
|
|
|
|
smbus_base + SMB_STS,
|
|
|
|
smbus_base + SMB_STS + SIS630_SMB_IOREGION - 1);
|
2012-01-12 20:32:03 +01:00
|
|
|
retval = -EBUSY;
|
2005-04-17 00:20:36 +02:00
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
retval = 0;
|
|
|
|
|
|
|
|
exit:
|
|
|
|
if (retval)
|
2013-01-28 22:21:05 +01:00
|
|
|
smbus_base = 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-09-03 22:39:46 +02:00
|
|
|
static const struct i2c_algorithm smbus_algorithm = {
|
2005-04-17 00:20:36 +02:00
|
|
|
.smbus_xfer = sis630_access,
|
|
|
|
.functionality = sis630_func,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct i2c_adapter sis630_adapter = {
|
|
|
|
.owner = THIS_MODULE,
|
2008-07-14 22:38:29 +02:00
|
|
|
.class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
|
2005-04-17 00:20:36 +02:00
|
|
|
.algo = &smbus_algorithm,
|
2013-01-28 22:21:05 +01:00
|
|
|
.retries = 3
|
2005-04-17 00:20:36 +02:00
|
|
|
};
|
|
|
|
|
2013-12-03 00:11:20 +01:00
|
|
|
static const struct pci_device_id sis630_ids[] = {
|
2005-04-17 00:20:36 +02:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503) },
|
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC) },
|
2013-01-28 22:21:05 +01:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_964) },
|
2005-04-17 00:20:36 +02:00
|
|
|
{ 0, }
|
|
|
|
};
|
|
|
|
|
2013-01-29 21:22:26 +01:00
|
|
|
MODULE_DEVICE_TABLE(pci, sis630_ids);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2012-11-27 21:59:38 +01:00
|
|
|
static int sis630_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
if (sis630_setup(dev)) {
|
2013-01-29 21:22:26 +01:00
|
|
|
dev_err(&dev->dev,
|
|
|
|
"SIS630 compatible bus not detected, "
|
|
|
|
"module not inserted.\n");
|
2005-04-17 00:20:36 +02:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2007-02-17 19:13:42 +01:00
|
|
|
/* set up the sysfs linkage to our parent device */
|
2005-04-17 00:20:36 +02:00
|
|
|
sis630_adapter.dev.parent = &dev->dev;
|
|
|
|
|
2009-01-07 14:29:18 +01:00
|
|
|
snprintf(sis630_adapter.name, sizeof(sis630_adapter.name),
|
2013-01-28 22:21:05 +01:00
|
|
|
"SMBus SIS630 adapter at %04hx", smbus_base + SMB_STS);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return i2c_add_adapter(&sis630_adapter);
|
|
|
|
}
|
|
|
|
|
2012-11-27 21:59:38 +01:00
|
|
|
static void sis630_remove(struct pci_dev *dev)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2013-01-28 22:21:05 +01:00
|
|
|
if (smbus_base) {
|
2005-04-17 00:20:36 +02:00
|
|
|
i2c_del_adapter(&sis630_adapter);
|
2013-01-28 22:21:05 +01:00
|
|
|
release_region(smbus_base + SMB_STS, SIS630_SMB_IOREGION);
|
|
|
|
smbus_base = 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static struct pci_driver sis630_driver = {
|
|
|
|
.name = "sis630_smbus",
|
|
|
|
.id_table = sis630_ids,
|
|
|
|
.probe = sis630_probe,
|
2012-11-27 21:59:38 +01:00
|
|
|
.remove = sis630_remove,
|
2005-04-17 00:20:36 +02:00
|
|
|
};
|
|
|
|
|
2012-07-24 14:13:56 +02:00
|
|
|
module_pci_driver(sis630_driver);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Alexander Malysh <amalysh@web.de>");
|
|
|
|
MODULE_DESCRIPTION("SIS630 SMBus driver");
|