2009-04-23 00:57:05 +02:00
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/*
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* Freescale STMP37XX platform support
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*
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* Embedded Alley Solutions, Inc <source@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/stmp3xxx.h>
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#include <mach/dma.h>
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2009-05-31 14:32:11 +02:00
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#include <mach/platform.h>
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2009-04-23 00:57:05 +02:00
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#include <mach/regs-icoll.h>
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#include <mach/regs-apbh.h>
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#include <mach/regs-apbx.h>
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#include "stmp37xx.h"
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/*
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* IRQ handling
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*/
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2010-11-29 11:13:59 +01:00
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static void stmp37xx_ack_irq(struct irq_data *d)
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2009-04-23 00:57:05 +02:00
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{
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/* Disable IRQ */
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2010-11-29 11:13:59 +01:00
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stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
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REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
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2009-04-23 00:57:05 +02:00
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/* ACK current interrupt */
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2009-05-31 14:32:11 +02:00
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__raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
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2009-04-23 00:57:05 +02:00
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/* Barrier */
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2009-05-31 14:32:11 +02:00
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(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
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2009-04-23 00:57:05 +02:00
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}
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2010-11-29 11:13:59 +01:00
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static void stmp37xx_mask_irq(struct irq_data *d)
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2009-04-23 00:57:05 +02:00
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{
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/* IRQ disable */
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2010-11-29 11:13:59 +01:00
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stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
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REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
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2009-04-23 00:57:05 +02:00
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}
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2010-11-29 11:13:59 +01:00
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static void stmp37xx_unmask_irq(struct irq_data *d)
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2009-04-23 00:57:05 +02:00
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{
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/* IRQ enable */
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2010-11-29 11:13:59 +01:00
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stmp3xxx_setl(0x04 << ((d->irq % 4) * 8),
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REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
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2009-04-23 00:57:05 +02:00
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}
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static struct irq_chip stmp37xx_chip = {
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2010-11-29 11:13:59 +01:00
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.irq_ack = stmp37xx_ack_irq,
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.irq_mask = stmp37xx_mask_irq,
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.irq_unmask = stmp37xx_unmask_irq,
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2009-04-23 00:57:05 +02:00
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};
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void __init stmp37xx_init_irq(void)
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{
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stmp3xxx_init_irq(&stmp37xx_chip);
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}
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/*
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* DMA interrupt handling
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*/
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void stmp3xxx_arch_dma_enable_interrupt(int channel)
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{
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2009-05-31 14:32:11 +02:00
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switch (STMP3XXX_DMA_BUS(channel)) {
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2009-04-23 00:57:05 +02:00
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case STMP3XXX_BUS_APBH:
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2009-05-31 14:32:11 +02:00
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stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
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REGS_APBH_BASE + HW_APBH_CTRL1);
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2009-04-23 00:57:05 +02:00
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break;
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case STMP3XXX_BUS_APBX:
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2009-05-31 14:32:11 +02:00
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stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
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REGS_APBX_BASE + HW_APBX_CTRL1);
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2009-04-23 00:57:05 +02:00
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break;
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}
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}
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EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
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void stmp3xxx_arch_dma_clear_interrupt(int channel)
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{
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2009-05-31 14:32:11 +02:00
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switch (STMP3XXX_DMA_BUS(channel)) {
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2009-04-23 00:57:05 +02:00
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case STMP3XXX_BUS_APBH:
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2009-05-31 14:32:11 +02:00
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stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
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REGS_APBH_BASE + HW_APBH_CTRL1);
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2009-04-23 00:57:05 +02:00
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break;
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case STMP3XXX_BUS_APBX:
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2009-05-31 14:32:11 +02:00
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stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
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REGS_APBX_BASE + HW_APBX_CTRL1);
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2009-04-23 00:57:05 +02:00
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break;
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}
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}
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EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
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int stmp3xxx_arch_dma_is_interrupt(int channel)
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{
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int r = 0;
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2009-05-31 14:32:11 +02:00
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switch (STMP3XXX_DMA_BUS(channel)) {
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2009-04-23 00:57:05 +02:00
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case STMP3XXX_BUS_APBH:
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2009-05-31 14:32:11 +02:00
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r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
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(1 << STMP3XXX_DMA_CHANNEL(channel));
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2009-04-23 00:57:05 +02:00
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break;
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case STMP3XXX_BUS_APBX:
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2009-05-31 14:32:11 +02:00
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r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
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(1 << STMP3XXX_DMA_CHANNEL(channel));
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2009-04-23 00:57:05 +02:00
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break;
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}
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return r;
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}
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EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
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void stmp3xxx_arch_dma_reset_channel(int channel)
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{
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2009-05-31 14:32:11 +02:00
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unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
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2009-04-23 00:57:05 +02:00
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2009-05-31 14:32:11 +02:00
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switch (STMP3XXX_DMA_BUS(channel)) {
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2009-04-23 00:57:05 +02:00
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case STMP3XXX_BUS_APBH:
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/* Reset channel and wait for it to complete */
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2009-05-31 14:32:11 +02:00
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stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
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REGS_APBH_BASE + HW_APBH_CTRL0);
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while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
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2009-04-23 00:57:05 +02:00
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(chbit << BP_APBH_CTRL0_RESET_CHANNEL))
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2009-05-31 14:32:11 +02:00
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cpu_relax();
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2009-04-23 00:57:05 +02:00
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break;
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case STMP3XXX_BUS_APBX:
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2009-05-31 14:32:11 +02:00
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stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
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REGS_APBX_BASE + HW_APBX_CTRL0);
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while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
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2009-04-23 00:57:05 +02:00
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(chbit << BP_APBX_CTRL0_RESET_CHANNEL))
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2009-05-31 14:32:11 +02:00
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cpu_relax();
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2009-04-23 00:57:05 +02:00
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break;
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}
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}
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EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
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void stmp3xxx_arch_dma_freeze(int channel)
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{
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2009-05-31 14:32:11 +02:00
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unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
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2009-04-23 00:57:05 +02:00
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2009-05-31 14:32:11 +02:00
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switch (STMP3XXX_DMA_BUS(channel)) {
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2009-04-23 00:57:05 +02:00
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case STMP3XXX_BUS_APBH:
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2009-05-31 14:32:11 +02:00
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stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
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2009-04-23 00:57:05 +02:00
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break;
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case STMP3XXX_BUS_APBX:
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2009-05-31 14:32:11 +02:00
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stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
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2009-04-23 00:57:05 +02:00
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break;
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}
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}
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EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
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void stmp3xxx_arch_dma_unfreeze(int channel)
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{
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2009-05-31 14:32:11 +02:00
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unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
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2009-04-23 00:57:05 +02:00
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2009-05-31 14:32:11 +02:00
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switch (STMP3XXX_DMA_BUS(channel)) {
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2009-04-23 00:57:05 +02:00
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case STMP3XXX_BUS_APBH:
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2009-05-31 14:32:11 +02:00
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stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
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2009-04-23 00:57:05 +02:00
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break;
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case STMP3XXX_BUS_APBX:
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2009-05-31 14:32:11 +02:00
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stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
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2009-04-23 00:57:05 +02:00
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break;
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}
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}
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EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
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/*
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* The registers are all very closely mapped, so we might as well map them all
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* with a single mapping
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*
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* Logical Physical
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* f0000000 80000000 On-chip registers
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2009-05-31 14:32:11 +02:00
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* f1000000 00000000 32k on-chip SRAM
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2009-04-23 00:57:05 +02:00
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*/
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static struct map_desc stmp37xx_io_desc[] __initdata = {
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{
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.virtual = (u32)STMP3XXX_REGS_BASE,
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.pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
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.length = SZ_1M,
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.type = MT_DEVICE
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},
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{
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.virtual = (u32)STMP3XXX_OCRAM_BASE,
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.pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
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.length = STMP3XXX_OCRAM_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init stmp37xx_map_io(void)
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{
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iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc));
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}
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